Rewrote the VRC2/4 emulation for modularity, and separate individual mappers into separate source files.
This commit is contained in:
NewRisingSun
committed by
LibretroAdmin
LibretroAdmin
parent
b349f7f3e2
commit
6cbb11bdd1
69
src/boards/21_22_23_25.c
Normal file
69
src/boards/21_22_23_25.c
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@@ -0,0 +1,69 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static void sync () {
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VRC24_syncPRG(0x01F, 0x000);
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VRC24_syncCHR(0x1FF, 0x000);
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VRC24_syncMirror();
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}
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void Mapper21_Init (CartInfo *info) {
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switch(info->submapper) {
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case 1: VRC24_init(info, sync, 0x02, 0x04, 1, 1, 8); break;
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case 2: VRC24_init(info, sync, 0x40, 0x80, 1, 1, 8); break;
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default: VRC24_init(info, sync, 0x42, 0x84, 1, 1, 8); break;
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}
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}
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int Mapper22_getCHRBank(int bank) {
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return VRC24_chr[bank &7] >>1;
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}
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void Mapper22_Init (CartInfo *info) {
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VRC24_init(info, sync, 0x02, 0x01, 0, 0, 8);
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VRC24_GetCHRBank =Mapper22_getCHRBank;
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}
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DECLFR(Mapper23_readProtection) {
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return VRC2_pins;
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}
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void Mapper23_Init (CartInfo *info) {
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switch(info->submapper) {
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case 1: VRC24_init(info, sync, 0x01, 0x02, 1, 1, 8); break;
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case 2: VRC24_init(info, sync, 0x04, 0x08, 1, 1, 8); break;
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case 3: VRC24_init(info, sync, 0x01, 0x02, 0, 0, 8);
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VRC24_WRAMRead =Mapper23_readProtection;
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break;
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default: VRC24_init(info, sync, 0x05, 0x0A, 1, 1, 8); break;
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}
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}
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void Mapper25_Init (CartInfo *info) {
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switch(info->submapper) {
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case 1: VRC24_init(info, sync, 0x02, 0x01, 1, 1, 8); break;
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case 2: VRC24_init(info, sync, 0x08, 0x04, 1, 1, 8); break;
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case 3: VRC24_init(info, sync, 0x02, 0x01, 0, 0, 8); break;
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default: VRC24_init(info, sync, 0x0A, 0x05, 1, 1, 8); break;
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}
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}
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72
src/boards/308.c
Normal file
72
src/boards/308.c
Normal file
@@ -0,0 +1,72 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static uint8 irqEnabled;
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static uint16 irqCounterLow;
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static uint8 irqCounterHigh;
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static SFORMAT UNLTH21311_stateRegs[] ={
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{ &irqEnabled, 1, "IRQE" },
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{ &irqCounterLow, 2 | FCEUSTATE_RLSB, "CNTL" },
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{ &irqCounterHigh, 1, "CNTH" },
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{ 0 }
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};
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static void sync () {
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VRC24_syncPRG(0x01F, 0x000);
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VRC24_syncCHR(0x1FF, 0x000);
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VRC24_syncMirror();
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}
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DECLFW(UNLTH21311_writeIRQ) {
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switch(A &3) {
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case 0: X6502_IRQEnd(FCEU_IQEXT);
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irqEnabled =0;
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irqCounterLow =0;
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break;
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case 1: irqEnabled =1;
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break;
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case 3: irqCounterHigh =V >>4;
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break;
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}
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}
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void FP_FASTAPASS(1) UNLTH21311_cpuCycle(int a) {
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while (a--) if (irqEnabled) {
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if ((++irqCounterLow &4095) ==2048) irqCounterHigh--;
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if (!irqCounterHigh && (irqCounterLow &4095) <2048) X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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void UNLTH21311_power(void) {
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irqEnabled =irqCounterLow =irqCounterHigh =0;
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VRC24_power();
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SetWriteHandler(0xF000, 0xFFFF, UNLTH21311_writeIRQ);
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}
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void UNLTH21311_Init (CartInfo *info) {
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VRC24_init(info, sync, 0x01, 0x02, 0, 0, 0);
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AddExState(UNLTH21311_stateRegs, ~0, 0, 0);
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info->Power =UNLTH21311_power;
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MapIRQHook =UNLTH21311_cpuCycle;
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}
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65
src/boards/524.c
Normal file
65
src/boards/524.c
Normal file
@@ -0,0 +1,65 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static uint8 irqEnabled;
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static uint16 irqCounter;
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static SFORMAT BTL900218_stateRegs[] ={
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{ &irqEnabled, 1, "IRQE" },
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{ &irqCounter, 2 | FCEUSTATE_RLSB, "CNTL" },
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{ 0 }
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};
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static void sync () {
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VRC24_syncPRG(0x01F, 0x000);
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VRC24_syncCHR(0x1FF, 0x000);
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VRC24_syncMirror();
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}
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DECLFW(BTL900218_writeIRQ) {
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if (A &8) {
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if (A &4) {
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irqEnabled =0;
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irqCounter =0;
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X6502_IRQEnd(FCEU_IQEXT);
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} else
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irqEnabled =1;
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}
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}
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void FP_FASTAPASS(1) BTL900218_cpuCycle(int a) {
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while (a--) if (irqEnabled && ++irqCounter &1024) X6502_IRQBegin(FCEU_IQEXT);
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}
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void BTL900218_power(void) {
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irqEnabled =irqCounter =0;
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VRC24_power();
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SetWriteHandler(0xF000, 0xFFFF, BTL900218_writeIRQ);
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}
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void BTL900218_Init (CartInfo *info) {
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VRC24_init(info, sync, 0x01, 0x02, 0, 0, 0);
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AddExState(BTL900218_stateRegs, ~0, 0, 0);
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info->Power =BTL900218_power;
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MapIRQHook =BTL900218_cpuCycle;
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}
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43
src/boards/525.c
Normal file
43
src/boards/525.c
Normal file
@@ -0,0 +1,43 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static void sync () {
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VRC24_syncPRG(0x01F, 0x000);
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VRC24_syncCHR(0x1FF, 0x000);
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VRC24_syncMirror();
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}
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DECLFW(UNLKS7021A_writeCHR) {
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VRC24_chr[A &7] =V;
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VRC24_Sync();
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}
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void UNLKS7021A_power (void) {
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VRC24_power();
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SetWriteHandler(0xB000, 0xEFFF, UNLKS7021A_writeCHR);
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}
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void UNLKS7021A_Init (CartInfo *info) {
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VRC24_init(info, sync, 0x01, 0x02, 0, 0, 0);
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info->Power =UNLKS7021A_power;
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}
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47
src/boards/529.c
Normal file
47
src/boards/529.c
Normal file
@@ -0,0 +1,47 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
|
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static void sync () {
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setprg16(0x8000, VRC24_prg[1]);
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setprg16(0xC000, 0xFF);
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VRC24_syncCHR(0x1FF, 0x000);
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VRC24_syncMirror();
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}
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DECLFR(UNLT230_readEEPROM) {
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return 0xFF;
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}
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DECLFW(UNLT230_writeEEPROM) {
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}
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void UNLT230_power (void) {
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VRC24_power();
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SetReadHandler(0x5000, 0x5FFF, UNLT230_readEEPROM);
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SetWriteHandler(0xF800, 0xFFFF, UNLT230_writeEEPROM);
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}
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void UNLT230_Init (CartInfo *info) {
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VRC24_init(info, sync, 0x04, 0x08, 1, 1, 0);
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info->Power =UNLT230_power;
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}
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@@ -1,7 +1,7 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
|
||||
* Copyright (C) 2007 CaH4e3
|
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* Copyright (C) 2025 NewRisingSun
|
||||
*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@@ -16,374 +16,218 @@
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
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*
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* VRC-2/VRC-4 Konami
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* VRC-4 Pirate
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*
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*/
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#include "mapinc.h"
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#include "vrc2and4.h"
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static uint8 isPirate, is22;
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static uint16 IRQCount;
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static uint8 IRQLatch, IRQa;
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static uint8 prgreg[4], chrreg[8];
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static uint16 chrhi[8];
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static uint8 regcmd, irqcmd, mirr, big_bank;
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static uint16 acount = 0;
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uint8 VRC24_A0, VRC24_A1; /* What cartridge connector address pins are connected to the chip's A0 and A1 input pins? */
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uint8 VRC24_isVRC4; /* VRC2 or VRC4? VRC2 has no single-screen mirroring, no PRG A14 swap and no IRQ counter */
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uint8 VRC24_useRepeatBit; /* VRC4 clones ignore the "repeat" bit in the IRQ Mode register */
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uint8 VRC24_prg[2];
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uint16 VRC24_chr[8];
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uint8 VRC24_mirroring;
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uint8 VRC24_misc;
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uint8 VRC2_pins; /* EEPROM interface */
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uint8 VRC4_latch;
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uint8 VRC4_mode;
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uint8 VRC4_count;
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signed short int VRC4_cycles;
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static uint8 *WRAM = NULL;
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static uint32 WRAMSIZE;
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static uint8 *WRAM;
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static uint32 WRAMSize;
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static uint8 prgMask = 0x1F;
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int (*VRC24_GetPRGBank)(int);
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int (*VRC24_GetCHRBank)(int);
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void (*VRC24_Sync)();
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DECLFW((*VRC24_ExternalSelect));
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DECLFR((*VRC24_WRAMRead));
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DECLFW((*VRC24_WRAMWrite));
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static SFORMAT StateRegs[] =
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{
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{ prgreg, 4, "PREG" },
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{ chrreg, 8, "CREG" },
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{ &chrhi[0], 2 | FCEUSTATE_RLSB, "CRH0" },
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{ &chrhi[1], 2 | FCEUSTATE_RLSB, "CRH1" },
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{ &chrhi[2], 2 | FCEUSTATE_RLSB, "CRH2" },
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{ &chrhi[3], 2 | FCEUSTATE_RLSB, "CRH3" },
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{ &chrhi[4], 2 | FCEUSTATE_RLSB, "CRH4" },
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{ &chrhi[5], 2 | FCEUSTATE_RLSB, "CRH5" },
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{ &chrhi[6], 2 | FCEUSTATE_RLSB, "CRH6" },
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{ &chrhi[7], 2 | FCEUSTATE_RLSB, "CRH7" },
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{ ®cmd, 1, "CMDR" },
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{ &irqcmd, 1, "CMDI" },
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{ &mirr, 1, "MIRR" },
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{ &prgMask, 1, "MAK" },
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{ &big_bank, 1, "BIGB" },
|
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{ &IRQCount, 2 | FCEUSTATE_RLSB, "IRQC" },
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{ &IRQLatch, 1, "IRQL" },
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{ &IRQa, 1, "IRQA" },
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static SFORMAT VRC24_stateRegs[] ={
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{ VRC24_prg, 2, "PREG" },
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{ &VRC24_chr[0], 2 | FCEUSTATE_RLSB, "CRH0" },
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{ &VRC24_chr[1], 2 | FCEUSTATE_RLSB, "CRH1" },
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{ &VRC24_chr[2], 2 | FCEUSTATE_RLSB, "CRH2" },
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{ &VRC24_chr[3], 2 | FCEUSTATE_RLSB, "CRH3" },
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{ &VRC24_chr[4], 2 | FCEUSTATE_RLSB, "CRH4" },
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{ &VRC24_chr[5], 2 | FCEUSTATE_RLSB, "CRH5" },
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{ &VRC24_chr[6], 2 | FCEUSTATE_RLSB, "CRH6" },
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{ &VRC24_chr[7], 2 | FCEUSTATE_RLSB, "CRH7" },
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{ &VRC24_mirroring, 1, "MIRR" },
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{ &VRC24_misc, 1, "MISC" },
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{ 0 }
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};
|
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static void Sync(void) {
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if (regcmd & 2) {
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setprg8(0xC000, prgreg[0] | big_bank);
|
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setprg8(0x8000, (prgreg[2] & prgMask) | big_bank);
|
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} else {
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setprg8(0x8000, prgreg[0] | big_bank);
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setprg8(0xC000, (prgreg[2] & prgMask) | big_bank);
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}
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setprg8(0xA000, prgreg[1] | big_bank);
|
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setprg8(0xE000, (prgreg[3] & prgMask) | big_bank);
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if (UNIFchrrama)
|
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setchr8(0);
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else {
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uint8 i;
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for (i = 0; i < 8; i++)
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setchr1(i << 10, (chrhi[i] | chrreg[i]) >> is22);
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}
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switch (mirr & 0x3) {
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case 0: setmirror(MI_V); break;
|
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case 1: setmirror(MI_H); break;
|
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case 2: setmirror(MI_0); break;
|
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case 3: setmirror(MI_1); break;
|
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}
|
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static SFORMAT VRC2_stateRegs[] ={
|
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{ &VRC2_pins, 1, "PINS" },
|
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};
|
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|
||||
static SFORMAT VRC4_stateRegs[] ={
|
||||
{ &VRC4_latch, 1, "LATC" },
|
||||
{ &VRC4_mode, 1, "MODE" },
|
||||
{ &VRC4_count, 1, "COUN" },
|
||||
{ &VRC4_cycles, 2 | FCEUSTATE_RLSB, "CYCL" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
void VRC24_syncPRG(int AND, int OR) {
|
||||
setprg8r(0x10, 0x6000, 0);
|
||||
setprg8(0x8000, VRC24_GetPRGBank(0) &AND | OR);
|
||||
setprg8(0xA000, VRC24_GetPRGBank(1) &AND | OR);
|
||||
setprg8(0xC000, VRC24_GetPRGBank(2) &AND | OR);
|
||||
setprg8(0xE000, VRC24_GetPRGBank(3) &AND | OR);
|
||||
}
|
||||
|
||||
static DECLFW(VRC24Write) {
|
||||
A &= 0xF003;
|
||||
if ((A >= 0xB000) && (A <= 0xE003)) {
|
||||
if (UNIFchrrama)
|
||||
big_bank = (V & 8) << 2; /* my personally many-in-one feature ;) just for support pirate cart 2-in-1 */
|
||||
else {
|
||||
uint16 i = ((A >> 1) & 1) | ((A - 0xB000) >> 11);
|
||||
uint16 nibble = ((A & 1) << 2);
|
||||
chrreg[i] = (chrreg[i] & (0xF0 >> nibble)) | ((V & 0xF) << nibble);
|
||||
if (nibble)
|
||||
chrhi[i] = (V & 0x10) << 4; /* another one many in one feature from pirate carts */
|
||||
void VRC24_syncCHR(int AND, int OR) {
|
||||
setchr1(0x0000, VRC24_GetCHRBank(0) &AND | OR);
|
||||
setchr1(0x0400, VRC24_GetCHRBank(1) &AND | OR);
|
||||
setchr1(0x0800, VRC24_GetCHRBank(2) &AND | OR);
|
||||
setchr1(0x0C00, VRC24_GetCHRBank(3) &AND | OR);
|
||||
setchr1(0x1000, VRC24_GetCHRBank(4) &AND | OR);
|
||||
setchr1(0x1400, VRC24_GetCHRBank(5) &AND | OR);
|
||||
setchr1(0x1800, VRC24_GetCHRBank(6) &AND | OR);
|
||||
setchr1(0x1C00, VRC24_GetCHRBank(7) &AND | OR);
|
||||
}
|
||||
|
||||
int VRC24_getPRGBank(int bank) {
|
||||
if (~bank &1 && VRC24_misc &2) bank ^=2;
|
||||
return bank &2? (0xFE | bank &1): VRC24_prg[bank &1];
|
||||
}
|
||||
|
||||
int VRC24_getCHRBank(int bank) {
|
||||
return VRC24_chr[bank &7];
|
||||
}
|
||||
|
||||
void VRC24_syncMirror() {
|
||||
setmirror(VRC24_isVRC4 && VRC24_mirroring &2? (VRC24_mirroring &1? MI_1: MI_0): (VRC24_mirroring &1? MI_H: MI_V));
|
||||
}
|
||||
|
||||
DECLFR(VRC24_wramRead) {
|
||||
if (VRC24_WRAMRead)
|
||||
VRC24_WRAMRead(A);
|
||||
else
|
||||
if (WRAMSize)
|
||||
return CartBR(((A -0x6000) &(WRAMSize -1)) +0x6000);
|
||||
else
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
DECLFW(VRC24_wramWrite) {
|
||||
if (WRAMSize)
|
||||
CartBW(((A -0x6000) &(WRAMSize -1)) +0x6000, V);
|
||||
else
|
||||
if (!VRC24_isVRC4)
|
||||
VRC2_pins =V;
|
||||
|
||||
if (VRC24_WRAMWrite)
|
||||
VRC24_WRAMWrite(A, V);
|
||||
}
|
||||
|
||||
DECLFW(VRC24_writeReg) {
|
||||
unsigned int index, addr;
|
||||
addr =A &0xF000 | (A &VRC24_A0? 1: 0) | (A &VRC24_A1? 2: 0); /* address as the chip sees it */
|
||||
switch (addr &0xF000) {
|
||||
case 0x8000: case 0xA000:
|
||||
VRC24_prg[addr >>13 &1] =V;
|
||||
VRC24_Sync();
|
||||
break;
|
||||
case 0x9000:
|
||||
if (!VRC24_isVRC4 || (addr &3) ==0) {
|
||||
VRC24_mirroring =V;
|
||||
VRC24_Sync();
|
||||
} else
|
||||
if (VRC24_isVRC4 && (addr &3) ==2) {
|
||||
VRC24_misc =V;
|
||||
VRC24_Sync();
|
||||
}
|
||||
if (VRC24_isVRC4 && (addr &3) ==3 && VRC24_ExternalSelect) {
|
||||
VRC24_ExternalSelect(A, V); /* Provide original address */
|
||||
}
|
||||
Sync();
|
||||
} else {
|
||||
switch (A & 0xF003) {
|
||||
case 0x8000:
|
||||
case 0x8001:
|
||||
case 0x8002:
|
||||
case 0x8003:
|
||||
if (!isPirate) {
|
||||
prgreg[0] = V & prgMask;
|
||||
Sync();
|
||||
}
|
||||
break;
|
||||
case 0xA000:
|
||||
case 0xA001:
|
||||
case 0xA002:
|
||||
case 0xA003:
|
||||
if (!isPirate)
|
||||
{
|
||||
prgreg[1] = V & prgMask;
|
||||
}
|
||||
else {
|
||||
prgreg[0] = (V & prgMask) << 1;
|
||||
prgreg[1] = ((V & prgMask) << 1) | 1;
|
||||
}
|
||||
Sync();
|
||||
break;
|
||||
case 0x9000:
|
||||
case 0x9001: if (V != 0xFF) mirr = V; Sync(); break;
|
||||
case 0x9002:
|
||||
case 0x9003: regcmd = V; Sync(); break;
|
||||
case 0xF000: X6502_IRQEnd(FCEU_IQEXT); IRQLatch &= 0xF0; IRQLatch |= V & 0xF; break;
|
||||
case 0xF001: X6502_IRQEnd(FCEU_IQEXT); IRQLatch &= 0x0F; IRQLatch |= V << 4; break;
|
||||
case 0xF002: X6502_IRQEnd(FCEU_IQEXT); acount = 0; IRQCount = IRQLatch; IRQa = V & 2; irqcmd = V & 1; break;
|
||||
case 0xF003: X6502_IRQEnd(FCEU_IQEXT); IRQa = irqcmd; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static DECLFW(M21Write) {
|
||||
A = (A & 0xF000) | ((A >> 1) & 0x3) | ((A >> 6) & 0x3); /* Ganbare Goemon Gaiden 2 - Tenka no Zaihou (J) [!] is Mapper 21*/
|
||||
VRC24Write(A, V);
|
||||
}
|
||||
|
||||
static DECLFW(M22Write) {
|
||||
#if 0
|
||||
/* Removed this hack, which was a bug in actual game cart.
|
||||
* http://forums.nesdev.com/viewtopic.php?f=3&t=6584
|
||||
*/
|
||||
if ((A >= 0xC004) && (A <= 0xC007)) { /* Ganbare Goemon Gaiden does strange things!!! at the end credits
|
||||
weirdo = 1; * quick dirty hack, seems there is no other games with such PCB, so
|
||||
* we never know if it will not work for something else lol
|
||||
*/
|
||||
}
|
||||
#endif
|
||||
A |= ((A >> 2) & 0x3); /* It's just swapped lines from 21 mapper
|
||||
*/
|
||||
VRC24Write((A & 0xF000) | ((A >> 1) & 1) | ((A << 1) & 2), V);
|
||||
}
|
||||
|
||||
static DECLFW(M23Write) {
|
||||
A |= ((A >> 2) & 0x3) | ((A >> 4) & 0x3); /* actually there is many-in-one mapper source, some pirate or
|
||||
* licensed games use various address bits for registers
|
||||
*/
|
||||
VRC24Write(A, V);
|
||||
}
|
||||
|
||||
static void VRC24PowerCommon(void (*WRITEFUNC)(uint32 A, uint8 V)) {
|
||||
Sync();
|
||||
if (WRAMSIZE) {
|
||||
setprg8r(0x10, 0x6000, 0); /* Only two Goemon games are have battery backed RAM, three more shooters
|
||||
* (Parodius Da!, Gradius 2 and Crisis Force uses 2k or SRAM at 6000-67FF only
|
||||
*/
|
||||
SetReadHandler(0x6000, 0x7FFF, CartBR);
|
||||
SetWriteHandler(0x6000, 0x7FFF, CartBW);
|
||||
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
|
||||
}
|
||||
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
||||
SetWriteHandler(0x8000, 0xFFFF, WRITEFUNC);
|
||||
}
|
||||
|
||||
static void M21Power(void) {
|
||||
VRC24PowerCommon(M21Write);
|
||||
}
|
||||
|
||||
static void M22Power(void) {
|
||||
VRC24PowerCommon(M22Write);
|
||||
}
|
||||
|
||||
static void M23Power(void) {
|
||||
big_bank = 0x20;
|
||||
if ((prgreg[2] == 0x30) && (prgreg[3] == 0x31))
|
||||
big_bank = 0x00;
|
||||
VRC24PowerCommon(M23Write);
|
||||
}
|
||||
|
||||
static void M25Power(void) {
|
||||
big_bank = 0x20;
|
||||
VRC24PowerCommon(M22Write);
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) VRC24IRQHook(int a) {
|
||||
#define LCYCS 341
|
||||
if (IRQa) {
|
||||
acount += a * 3;
|
||||
if (acount >= LCYCS) {
|
||||
while (acount >= LCYCS) {
|
||||
acount -= LCYCS;
|
||||
IRQCount++;
|
||||
if (IRQCount & 0x100) {
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
IRQCount = IRQLatch;
|
||||
break;
|
||||
case 0xF000:
|
||||
if (VRC24_isVRC4) switch (addr &3) {
|
||||
case 0: VRC4_latch =VRC4_latch &0xF0 | V &0x0F; break;
|
||||
case 1: VRC4_latch =VRC4_latch &0x0F | V <<4; break;
|
||||
case 2: VRC4_mode =V;
|
||||
if (VRC4_mode &0x02) {
|
||||
VRC4_count =VRC4_latch;
|
||||
VRC4_cycles =341;
|
||||
}
|
||||
X6502_IRQEnd(FCEU_IQEXT);
|
||||
break;
|
||||
case 3: if (VRC24_useRepeatBit) VRC4_mode =VRC4_mode &~0x02 | VRC4_mode <<1 &0x02;
|
||||
X6502_IRQEnd(FCEU_IQEXT);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
index =(addr -0xB000) >>11 | addr >>1 &1;
|
||||
if (addr &1)
|
||||
VRC24_chr[index] =VRC24_chr[index] & 0x0F | V <<4;
|
||||
else
|
||||
VRC24_chr[index] =VRC24_chr[index] &~0x0F | V &0x0F;
|
||||
VRC24_Sync();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) VRC4_cpuCycle(int a) {
|
||||
while (a--) {
|
||||
if (VRC4_mode &0x02 && (VRC4_mode &0x04 || (VRC4_cycles -=3) <=0)) {
|
||||
if (~VRC4_mode &0x04) VRC4_cycles +=341;
|
||||
if (!++VRC4_count) {
|
||||
VRC4_count =VRC4_latch;
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void StateRestore(int version) {
|
||||
Sync();
|
||||
void VRC24_power(void) {
|
||||
SetReadHandler(0x6000, 0x7FFF, VRC24_wramRead);
|
||||
SetWriteHandler(0x6000, 0x7FFF, VRC24_wramWrite);
|
||||
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
||||
SetWriteHandler(0x8000, 0xFFFF, VRC24_writeReg);
|
||||
VRC24_Sync();
|
||||
}
|
||||
|
||||
static void VRC24Close(void) {
|
||||
if (WRAM)
|
||||
void VRC24_close(void) {
|
||||
if (WRAM) {
|
||||
FCEU_gfree(WRAM);
|
||||
WRAM = NULL;
|
||||
WRAM =NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void VRC24_Init(CartInfo *info, uint32 hasWRAM) {
|
||||
info->Close = VRC24Close;
|
||||
MapIRQHook = VRC24IRQHook;
|
||||
GameStateRestore = StateRestore;
|
||||
|
||||
prgMask = 0x1F;
|
||||
prgreg[2] = ~1;
|
||||
prgreg[3] = ~0;
|
||||
|
||||
WRAMSIZE = 0;
|
||||
|
||||
/* 400K PRG + 128K CHR Contra rom hacks */
|
||||
if (info->PRGRomSize == 400 * 1024 && info->CHRRomSize == 128 * 1024) {
|
||||
prgreg[2] = 0x30;
|
||||
prgreg[3] = 0x31;
|
||||
prgMask = 0x3F;
|
||||
void VRC24_init(CartInfo *info, void (*_sync)(), uint8 _A0, uint8 _A1, uint8 _isVRC4, uint8 _useRepeatBit, uint8 defaultWRAMSizeKiB) {
|
||||
VRC24_Sync =_sync;
|
||||
VRC24_A0 =_A0;
|
||||
VRC24_A1 =_A1;
|
||||
VRC24_isVRC4 =_isVRC4;
|
||||
VRC24_useRepeatBit =_useRepeatBit;
|
||||
VRC24_GetPRGBank =VRC24_getPRGBank;
|
||||
VRC24_GetCHRBank =VRC24_getCHRBank;
|
||||
VRC24_WRAMRead =NULL;
|
||||
VRC24_WRAMWrite =NULL;
|
||||
VRC24_ExternalSelect =NULL;
|
||||
info->Power =VRC24_power;
|
||||
info->Close =VRC24_close;
|
||||
AddExState(VRC24_stateRegs, ~0, 0, 0);
|
||||
if (VRC24_isVRC4) {
|
||||
MapIRQHook =VRC4_cpuCycle;
|
||||
AddExState(VRC4_stateRegs, ~0, 0, 0);
|
||||
} else {
|
||||
AddExState(VRC2_stateRegs, ~0, 0, 0);
|
||||
}
|
||||
|
||||
if (hasWRAM) {
|
||||
WRAMSIZE = 8192;
|
||||
WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
|
||||
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
|
||||
AddExState(WRAM, WRAMSIZE, 0, "WRAM");
|
||||
|
||||
|
||||
WRAMSize =info->iNES2? (info->PRGRamSize +info->PRGRamSaveSize): (defaultWRAMSizeKiB *1024);
|
||||
if (WRAMSize) {
|
||||
WRAM =(uint8*)FCEU_gmalloc(WRAMSize);
|
||||
SetupCartPRGMapping(0x10, WRAM, WRAMSize, 1);
|
||||
AddExState(WRAM, WRAMSize, 0, "WRAM");
|
||||
if (info->battery) {
|
||||
info->SaveGame[0] = WRAM;
|
||||
info->SaveGameLen[0] = WRAMSIZE;
|
||||
info->SaveGame[0] =WRAM;
|
||||
info->SaveGameLen[0] =WRAMSize;
|
||||
}
|
||||
}
|
||||
|
||||
AddExState(&StateRegs, ~0, 0, 0);
|
||||
}
|
||||
|
||||
void Mapper21_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M21Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void Mapper22_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 1;
|
||||
info->Power = M22Power;
|
||||
VRC24_Init(info, 0);
|
||||
}
|
||||
|
||||
void Mapper23_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M23Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void Mapper25_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M25Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void UNLT230_Init(CartInfo *info) {
|
||||
isPirate = 1;
|
||||
is22 = 0;
|
||||
info->Power = M23Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
/* -------------------- UNL-TH2131-1 -------------------- */
|
||||
/* https://wiki.nesdev.com/w/index.php/NES_2.0_Mapper_308
|
||||
* NES 2.0 Mapper 308 is used for a bootleg version of the Sunsoft game Batman
|
||||
* similar to Mapper 23 Submapper 3) with custom IRQ functionality.
|
||||
* UNIF board name is UNL-TH2131-1.
|
||||
*/
|
||||
|
||||
static DECLFW(TH2131Write) {
|
||||
switch (A & 0xF003) {
|
||||
case 0xF000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; IRQCount = 0; break;
|
||||
case 0xF001: IRQa = 1; break;
|
||||
case 0xF003: IRQLatch = (V & 0xF0) >> 4; break;
|
||||
}
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) TH2131IRQHook(int a) {
|
||||
int count;
|
||||
|
||||
if (!IRQa)
|
||||
return;
|
||||
|
||||
for (count = 0; count < a; count++) {
|
||||
IRQCount++;
|
||||
if ((IRQCount & 0x0FFF) == 2048)
|
||||
IRQLatch--;
|
||||
if (!IRQLatch && (IRQCount & 0x0FFF) < 2048)
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
}
|
||||
}
|
||||
|
||||
static void TH2131Power(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xF000, 0xFFFF, TH2131Write);
|
||||
}
|
||||
|
||||
void UNLTH21311_Init(CartInfo *info) {
|
||||
info->Power = TH2131Power;
|
||||
VRC24_Init(info, 1);
|
||||
MapIRQHook = TH2131IRQHook;
|
||||
}
|
||||
|
||||
/* -------------------- UNL-KS7021A -------------------- */
|
||||
/* http://wiki.nesdev.com/w/index.php/NES_2.0_Mapper_525
|
||||
* NES 2.0 Mapper 525 is used for a bootleg version of versions of Contra and 月風魔伝 (Getsu Fūma Den).
|
||||
* Its similar to Mapper 23 Submapper 3) with non-nibblized CHR-ROM bank registers.
|
||||
*/
|
||||
|
||||
static DECLFW(KS7021AWrite) {
|
||||
switch (A & 0xB000) {
|
||||
case 0xB000: chrreg[A & 0x07] = V; Sync(); break;
|
||||
}
|
||||
}
|
||||
|
||||
static void KS7021APower(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xB000, 0xBFFF, KS7021AWrite);
|
||||
}
|
||||
|
||||
void UNLKS7021A_Init(CartInfo *info) {
|
||||
info->Power = KS7021APower;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
/* -------------------- BTL-900218 -------------------- */
|
||||
/* http://wiki.nesdev.com/w/index.php/UNIF/900218
|
||||
* NES 2.0 Mapper 524 describes the PCB used for the pirate port Lord of King or Axe of Fight.
|
||||
* UNIF board name is BTL-900218.
|
||||
*/
|
||||
|
||||
static DECLFW(BTL900218Write) {
|
||||
switch (A & 0xF00C) {
|
||||
case 0xF008: IRQa = 1; break;
|
||||
case 0xF00C: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; IRQCount = 0; break;
|
||||
}
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) BTL900218IRQHook(int a) {
|
||||
if (!IRQa)
|
||||
return;
|
||||
|
||||
IRQCount += a;
|
||||
if (IRQCount & 1024)
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
}
|
||||
|
||||
static void BTL900218Power(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xF000, 0xFFFF, BTL900218Write);
|
||||
}
|
||||
|
||||
void BTL900218_Init(CartInfo *info) {
|
||||
info->Power = BTL900218Power;
|
||||
VRC24_Init(info, 1);
|
||||
MapIRQHook = BTL900218IRQHook;
|
||||
}
|
||||
|
||||
35
src/boards/vrc2and4.h
Normal file
35
src/boards/vrc2and4.h
Normal file
@@ -0,0 +1,35 @@
|
||||
#ifndef _VRC2AND4_H
|
||||
#define _VRC2AND4_H
|
||||
|
||||
extern uint8 VRC24_A0, VRC24_A1;
|
||||
extern uint8 VRC24_isVRC4;
|
||||
extern uint8 VRC24_useRepeatBit;
|
||||
extern uint8 VRC24_prg[2];
|
||||
extern uint16 VRC24_chr[8];
|
||||
extern uint8 VRC24_mirroring;
|
||||
extern uint8 VRC24_misc;
|
||||
extern uint8 VRC2_pins;
|
||||
extern uint8 VRC4_latch;
|
||||
extern uint8 VRC4_mode;
|
||||
extern uint8 VRC4_count;
|
||||
extern signed short int VRC4_cycles;
|
||||
|
||||
extern int (*VRC24_GetPRGBank)(int);
|
||||
extern int (*VRC24_GetCHRBank)(int);
|
||||
extern void (*VRC24_Sync)();
|
||||
DECLFW((*VRC24_ExternalSelect));
|
||||
DECLFR((*VRC24_WRAMRead));
|
||||
DECLFW((*VRC24_WRAMWrite));
|
||||
|
||||
void VRC24_syncPRG (int AND, int OR);
|
||||
void VRC24_syncCHR (int AND, int OR);
|
||||
int VRC24_getPRGBank (int bank);
|
||||
int VRC24_getCHRBank (int bank);
|
||||
void VRC24_syncMirror ();
|
||||
DECLFW(VRC24_writeReg);
|
||||
|
||||
void VRC24_power(void);
|
||||
void VRC24_close(void);
|
||||
void VRC24_init(CartInfo *info, void (*_sync)(), uint8 _A0, uint8 _A1, uint8 _isVRC4, uint8 _useRepeatBit, uint8 defaultWRAMSizeKiB);
|
||||
|
||||
#endif
|
||||
389
src/boards/vrc2and4.old
Normal file
389
src/boards/vrc2and4.old
Normal file
@@ -0,0 +1,389 @@
|
||||
/* FCE Ultra - NES/Famicom Emulator
|
||||
*
|
||||
* Copyright notice for this file:
|
||||
* Copyright (C) 2007 CaH4e3
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
* VRC-2/VRC-4 Konami
|
||||
* VRC-4 Pirate
|
||||
*
|
||||
*/
|
||||
|
||||
#include "mapinc.h"
|
||||
|
||||
static uint8 isPirate, is22;
|
||||
static uint16 IRQCount;
|
||||
static uint8 IRQLatch, IRQa;
|
||||
static uint8 prgreg[4], chrreg[8];
|
||||
static uint16 chrhi[8];
|
||||
static uint8 regcmd, irqcmd, mirr, big_bank;
|
||||
static uint16 acount = 0;
|
||||
|
||||
static uint8 *WRAM = NULL;
|
||||
static uint32 WRAMSIZE;
|
||||
|
||||
static uint8 prgMask = 0x1F;
|
||||
|
||||
static SFORMAT StateRegs[] =
|
||||
{
|
||||
{ prgreg, 4, "PREG" },
|
||||
{ chrreg, 8, "CREG" },
|
||||
{ &chrhi[0], 2 | FCEUSTATE_RLSB, "CRH0" },
|
||||
{ &chrhi[1], 2 | FCEUSTATE_RLSB, "CRH1" },
|
||||
{ &chrhi[2], 2 | FCEUSTATE_RLSB, "CRH2" },
|
||||
{ &chrhi[3], 2 | FCEUSTATE_RLSB, "CRH3" },
|
||||
{ &chrhi[4], 2 | FCEUSTATE_RLSB, "CRH4" },
|
||||
{ &chrhi[5], 2 | FCEUSTATE_RLSB, "CRH5" },
|
||||
{ &chrhi[6], 2 | FCEUSTATE_RLSB, "CRH6" },
|
||||
{ &chrhi[7], 2 | FCEUSTATE_RLSB, "CRH7" },
|
||||
{ ®cmd, 1, "CMDR" },
|
||||
{ &irqcmd, 1, "CMDI" },
|
||||
{ &mirr, 1, "MIRR" },
|
||||
{ &prgMask, 1, "MAK" },
|
||||
{ &big_bank, 1, "BIGB" },
|
||||
{ &IRQCount, 2 | FCEUSTATE_RLSB, "IRQC" },
|
||||
{ &IRQLatch, 1, "IRQL" },
|
||||
{ &IRQa, 1, "IRQA" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static void Sync(void) {
|
||||
if (regcmd & 2) {
|
||||
setprg8(0xC000, prgreg[0] | big_bank);
|
||||
setprg8(0x8000, (prgreg[2] & prgMask) | big_bank);
|
||||
} else {
|
||||
setprg8(0x8000, prgreg[0] | big_bank);
|
||||
setprg8(0xC000, (prgreg[2] & prgMask) | big_bank);
|
||||
}
|
||||
setprg8(0xA000, prgreg[1] | big_bank);
|
||||
setprg8(0xE000, (prgreg[3] & prgMask) | big_bank);
|
||||
if (UNIFchrrama)
|
||||
setchr8(0);
|
||||
else {
|
||||
uint8 i;
|
||||
for (i = 0; i < 8; i++)
|
||||
setchr1(i << 10, (chrhi[i] | chrreg[i]) >> is22);
|
||||
}
|
||||
switch (mirr & 0x3) {
|
||||
case 0: setmirror(MI_V); break;
|
||||
case 1: setmirror(MI_H); break;
|
||||
case 2: setmirror(MI_0); break;
|
||||
case 3: setmirror(MI_1); break;
|
||||
}
|
||||
}
|
||||
|
||||
static DECLFW(VRC24Write) {
|
||||
A &= 0xF003;
|
||||
if ((A >= 0xB000) && (A <= 0xE003)) {
|
||||
if (UNIFchrrama)
|
||||
big_bank = (V & 8) << 2; /* my personally many-in-one feature ;) just for support pirate cart 2-in-1 */
|
||||
else {
|
||||
uint16 i = ((A >> 1) & 1) | ((A - 0xB000) >> 11);
|
||||
uint16 nibble = ((A & 1) << 2);
|
||||
chrreg[i] = (chrreg[i] & (0xF0 >> nibble)) | ((V & 0xF) << nibble);
|
||||
if (nibble)
|
||||
chrhi[i] = (V & 0x10) << 4; /* another one many in one feature from pirate carts */
|
||||
}
|
||||
Sync();
|
||||
} else {
|
||||
switch (A & 0xF003) {
|
||||
case 0x8000:
|
||||
case 0x8001:
|
||||
case 0x8002:
|
||||
case 0x8003:
|
||||
if (!isPirate) {
|
||||
prgreg[0] = V & prgMask;
|
||||
Sync();
|
||||
}
|
||||
break;
|
||||
case 0xA000:
|
||||
case 0xA001:
|
||||
case 0xA002:
|
||||
case 0xA003:
|
||||
if (!isPirate)
|
||||
{
|
||||
prgreg[1] = V & prgMask;
|
||||
}
|
||||
else {
|
||||
prgreg[0] = (V & prgMask) << 1;
|
||||
prgreg[1] = ((V & prgMask) << 1) | 1;
|
||||
}
|
||||
Sync();
|
||||
break;
|
||||
case 0x9000:
|
||||
case 0x9001: if (V != 0xFF) mirr = V; Sync(); break;
|
||||
case 0x9002:
|
||||
case 0x9003: regcmd = V; Sync(); break;
|
||||
case 0xF000: X6502_IRQEnd(FCEU_IQEXT); IRQLatch &= 0xF0; IRQLatch |= V & 0xF; break;
|
||||
case 0xF001: X6502_IRQEnd(FCEU_IQEXT); IRQLatch &= 0x0F; IRQLatch |= V << 4; break;
|
||||
case 0xF002: X6502_IRQEnd(FCEU_IQEXT); acount = 0; IRQCount = IRQLatch; IRQa = V & 2; irqcmd = V & 1; break;
|
||||
case 0xF003: X6502_IRQEnd(FCEU_IQEXT); IRQa = irqcmd; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static DECLFW(M21Write) {
|
||||
A = (A & 0xF000) | ((A >> 1) & 0x3) | ((A >> 6) & 0x3); /* Ganbare Goemon Gaiden 2 - Tenka no Zaihou (J) [!] is Mapper 21*/
|
||||
VRC24Write(A, V);
|
||||
}
|
||||
|
||||
static DECLFW(M22Write) {
|
||||
#if 0
|
||||
/* Removed this hack, which was a bug in actual game cart.
|
||||
* http://forums.nesdev.com/viewtopic.php?f=3&t=6584
|
||||
*/
|
||||
if ((A >= 0xC004) && (A <= 0xC007)) { /* Ganbare Goemon Gaiden does strange things!!! at the end credits
|
||||
weirdo = 1; * quick dirty hack, seems there is no other games with such PCB, so
|
||||
* we never know if it will not work for something else lol
|
||||
*/
|
||||
}
|
||||
#endif
|
||||
A |= ((A >> 2) & 0x3); /* It's just swapped lines from 21 mapper
|
||||
*/
|
||||
VRC24Write((A & 0xF000) | ((A >> 1) & 1) | ((A << 1) & 2), V);
|
||||
}
|
||||
|
||||
static DECLFW(M23Write) {
|
||||
A |= ((A >> 2) & 0x3) | ((A >> 4) & 0x3); /* actually there is many-in-one mapper source, some pirate or
|
||||
* licensed games use various address bits for registers
|
||||
*/
|
||||
VRC24Write(A, V);
|
||||
}
|
||||
|
||||
static void VRC24PowerCommon(void (*WRITEFUNC)(uint32 A, uint8 V)) {
|
||||
Sync();
|
||||
if (WRAMSIZE) {
|
||||
setprg8r(0x10, 0x6000, 0); /* Only two Goemon games are have battery backed RAM, three more shooters
|
||||
* (Parodius Da!, Gradius 2 and Crisis Force uses 2k or SRAM at 6000-67FF only
|
||||
*/
|
||||
SetReadHandler(0x6000, 0x7FFF, CartBR);
|
||||
SetWriteHandler(0x6000, 0x7FFF, CartBW);
|
||||
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
|
||||
}
|
||||
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
||||
SetWriteHandler(0x8000, 0xFFFF, WRITEFUNC);
|
||||
}
|
||||
|
||||
static void M21Power(void) {
|
||||
VRC24PowerCommon(M21Write);
|
||||
}
|
||||
|
||||
static void M22Power(void) {
|
||||
VRC24PowerCommon(M22Write);
|
||||
}
|
||||
|
||||
static void M23Power(void) {
|
||||
big_bank = 0x20;
|
||||
if ((prgreg[2] == 0x30) && (prgreg[3] == 0x31))
|
||||
big_bank = 0x00;
|
||||
VRC24PowerCommon(M23Write);
|
||||
}
|
||||
|
||||
static void M25Power(void) {
|
||||
big_bank = 0x20;
|
||||
VRC24PowerCommon(M22Write);
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) VRC24IRQHook(int a) {
|
||||
#define LCYCS 341
|
||||
if (IRQa) {
|
||||
acount += a * 3;
|
||||
if (acount >= LCYCS) {
|
||||
while (acount >= LCYCS) {
|
||||
acount -= LCYCS;
|
||||
IRQCount++;
|
||||
if (IRQCount & 0x100) {
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
IRQCount = IRQLatch;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void StateRestore(int version) {
|
||||
Sync();
|
||||
}
|
||||
|
||||
static void VRC24Close(void) {
|
||||
if (WRAM)
|
||||
FCEU_gfree(WRAM);
|
||||
WRAM = NULL;
|
||||
}
|
||||
|
||||
static void VRC24_Init(CartInfo *info, uint32 hasWRAM) {
|
||||
info->Close = VRC24Close;
|
||||
MapIRQHook = VRC24IRQHook;
|
||||
GameStateRestore = StateRestore;
|
||||
|
||||
prgMask = 0x1F;
|
||||
prgreg[2] = ~1;
|
||||
prgreg[3] = ~0;
|
||||
|
||||
WRAMSIZE = 0;
|
||||
|
||||
/* 400K PRG + 128K CHR Contra rom hacks */
|
||||
if (info->PRGRomSize == 400 * 1024 && info->CHRRomSize == 128 * 1024) {
|
||||
prgreg[2] = 0x30;
|
||||
prgreg[3] = 0x31;
|
||||
prgMask = 0x3F;
|
||||
}
|
||||
|
||||
if (hasWRAM) {
|
||||
WRAMSIZE = 8192;
|
||||
WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
|
||||
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
|
||||
AddExState(WRAM, WRAMSIZE, 0, "WRAM");
|
||||
|
||||
if (info->battery) {
|
||||
info->SaveGame[0] = WRAM;
|
||||
info->SaveGameLen[0] = WRAMSIZE;
|
||||
}
|
||||
}
|
||||
|
||||
AddExState(&StateRegs, ~0, 0, 0);
|
||||
}
|
||||
|
||||
void Mapper21_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M21Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void Mapper22_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 1;
|
||||
info->Power = M22Power;
|
||||
VRC24_Init(info, 0);
|
||||
}
|
||||
|
||||
void Mapper23_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M23Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void Mapper25_Init(CartInfo *info) {
|
||||
isPirate = 0;
|
||||
is22 = 0;
|
||||
info->Power = M25Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
void UNLT230_Init(CartInfo *info) {
|
||||
isPirate = 1;
|
||||
is22 = 0;
|
||||
info->Power = M23Power;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
/* -------------------- UNL-TH2131-1 -------------------- */
|
||||
/* https://wiki.nesdev.com/w/index.php/NES_2.0_Mapper_308
|
||||
* NES 2.0 Mapper 308 is used for a bootleg version of the Sunsoft game Batman
|
||||
* similar to Mapper 23 Submapper 3) with custom IRQ functionality.
|
||||
* UNIF board name is UNL-TH2131-1.
|
||||
*/
|
||||
|
||||
static DECLFW(TH2131Write) {
|
||||
switch (A & 0xF003) {
|
||||
case 0xF000: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; IRQCount = 0; break;
|
||||
case 0xF001: IRQa = 1; break;
|
||||
case 0xF003: IRQLatch = (V & 0xF0) >> 4; break;
|
||||
}
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) TH2131IRQHook(int a) {
|
||||
int count;
|
||||
|
||||
if (!IRQa)
|
||||
return;
|
||||
|
||||
for (count = 0; count < a; count++) {
|
||||
IRQCount++;
|
||||
if ((IRQCount & 0x0FFF) == 2048)
|
||||
IRQLatch--;
|
||||
if (!IRQLatch && (IRQCount & 0x0FFF) < 2048)
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
}
|
||||
}
|
||||
|
||||
static void TH2131Power(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xF000, 0xFFFF, TH2131Write);
|
||||
}
|
||||
|
||||
void UNLTH21311_Init(CartInfo *info) {
|
||||
info->Power = TH2131Power;
|
||||
VRC24_Init(info, 1);
|
||||
MapIRQHook = TH2131IRQHook;
|
||||
}
|
||||
|
||||
/* -------------------- UNL-KS7021A -------------------- */
|
||||
/* http://wiki.nesdev.com/w/index.php/NES_2.0_Mapper_525
|
||||
* NES 2.0 Mapper 525 is used for a bootleg version of versions of Contra and 月風魔伝 (Getsu Fūma Den).
|
||||
* Its similar to Mapper 23 Submapper 3) with non-nibblized CHR-ROM bank registers.
|
||||
*/
|
||||
|
||||
static DECLFW(KS7021AWrite) {
|
||||
switch (A & 0xB000) {
|
||||
case 0xB000: chrreg[A & 0x07] = V; Sync(); break;
|
||||
}
|
||||
}
|
||||
|
||||
static void KS7021APower(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xB000, 0xBFFF, KS7021AWrite);
|
||||
}
|
||||
|
||||
void UNLKS7021A_Init(CartInfo *info) {
|
||||
info->Power = KS7021APower;
|
||||
VRC24_Init(info, 1);
|
||||
}
|
||||
|
||||
/* -------------------- BTL-900218 -------------------- */
|
||||
/* http://wiki.nesdev.com/w/index.php/UNIF/900218
|
||||
* NES 2.0 Mapper 524 describes the PCB used for the pirate port Lord of King or Axe of Fight.
|
||||
* UNIF board name is BTL-900218.
|
||||
*/
|
||||
|
||||
static DECLFW(BTL900218Write) {
|
||||
switch (A & 0xF00C) {
|
||||
case 0xF008: IRQa = 1; break;
|
||||
case 0xF00C: X6502_IRQEnd(FCEU_IQEXT); IRQa = 0; IRQCount = 0; break;
|
||||
}
|
||||
}
|
||||
|
||||
void FP_FASTAPASS(1) BTL900218IRQHook(int a) {
|
||||
if (!IRQa)
|
||||
return;
|
||||
|
||||
IRQCount += a;
|
||||
if (IRQCount & 1024)
|
||||
X6502_IRQBegin(FCEU_IQEXT);
|
||||
}
|
||||
|
||||
static void BTL900218Power(void) {
|
||||
VRC24PowerCommon(VRC24Write);
|
||||
SetWriteHandler(0xF000, 0xFFFF, BTL900218Write);
|
||||
}
|
||||
|
||||
void BTL900218_Init(CartInfo *info) {
|
||||
info->Power = BTL900218Power;
|
||||
VRC24_Init(info, 1);
|
||||
MapIRQHook = BTL900218IRQHook;
|
||||
}
|
||||
Reference in New Issue
Block a user