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Cleanup

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NewRisingSun
2025-04-05 23:18:06 +02:00
committed by LibretroAdmin
parent c7a131c0e0
commit b349f7f3e2
3 changed files with 0 additions and 239 deletions
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146
src/boards/hardware/MMC3.c
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/* FCE Ultra - NES/Famicom Emulator
*
* Copyright notice for this file:
* Copyright (C) 2024 NewRisingSun
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "mapinc.h"
uint8 MMC3_type;
uint8 MMC3_index;
uint8 MMC3_reg[16];
uint8 MMC3_regMask;
uint8 MMC3_mirroring;
uint8 MMC3_wramEnable;
uint8 MMC3_reloadValue;
uint8 MMC3_reloadRequest;
uint8 MMC3_irqEnable;
uint8 MMC3_counter;
static SFORMAT MMC3_stateRegs[] ={
{ MMC3_reg, 8, "REGS" },
{ &MMC3_index, 1, "CMD" },
{ &MMC3_mirroring, 1, "A000" },
{ &MMC3_wramEnable, 1, "A001" },
{ &MMC3_reloadRequest, 1, "IRQR" },
{ &MMC3_counter, 1, "IRQC" },
{ &MMC3_reloadValue, 1, "IRQL" },
{ &MMC3_irqEnable, 1, "IRQA" },
{ 0 }
};
void (*MMC3_Sync)();
uint16 (*MMC3_GetPRGBank)(uint8 bank);
uint16 (*MMC3_GetCHRBank)(uint8 bank);
uint8 FP_FASTAPASS(1) (*MMC3_ReadWRAM) (uint32 A);
void FP_FASTAPASS(2) (*MMC3_WriteWRAM)(uint32 A, uint8 V);
void MMC3_syncWRAM () {
setprg8r(0x10, 0x6000, 0);
SetReadHandler (0x6000, 0x7FFF, MMC3_wramEnable &0x80? MMC3_ReadWRAM: NULL);
SetWriteHandler(0x6000, 0x7FFF, MMC3_wramEnable &0x80 && ~MMC3_wramEnable &0x40? MMC3_WriteWRAM: NULL);
}
uint16 MMC3_getPRGBank (uint8 bank) {
if (MMC3_index &0x40 && ~bank &1) bank ^=2;
return bank &2? 0xFE | bank &1: MMC3_reg[6 | bank &1];
}
uint16 MMC3_getCHRBank (uint8 bank) {
if (MMC3_index &0x80) bank ^=4;
return bank &4? reg[bank -2]: reg[bank >>1] &~1 | bank &1;
}
void MMC3_syncPRG (int AND, int OR) {
int bank;
for (bank =0; bank <4; bank++) setprg8(0x8000 | bank <<13, MMC3_GetPRGBank(bank) &AND |OR);
}
void MMC3_syncCHR (int AND, int OR) {
int bank;
for (bank =0; bank <4; bank++) setchr1(bank <<10, MMC3_GetCHRBank(bank) &AND |OR);
}
void MMC3_syncMirror () {
setmirror(MMC3_mirroring &1? MI_H: MI_V);
}
void MMC3_clockCounter () {
uint8 prevCounter =MMC3_counter;
MMC3_counter =MMC3_reloadRequest || !MMC3_counter? MMC3_reloadValue: --MMC3_counter;
if ((prevCounter || MMC3_type ==MMC3_TYPE_SHARP || MMC3_reloadRequest) && !MMC3_counter && MMC3_enableIRQ) X6502_IRQBegin(FCEU_IQEXT);
MMC3_reloadRequest =0;
}
DECLFW(MMC3_write) {
switch(A &0xE001) {
case 0x8000: MMC3_index =V; break;
case 0x8001: MMC3_reg[MMC3_index &MMC3_regMask] =V; break;
case 0xA000: MMC3_mirroring =V; break;
case 0xA001: MMC3_wramEnable =V; break;
case 0xC000: MMC3_reloadValue =V; break;
case 0xC001: MMC3_reloadRequest =1; MMC3_counter =0; break;
case 0xE000: X6502_IRQEnd(FCEU_IQEXT); /* Fall-through */
case 0xE001: MMC3_irqEnable =A &1; break;
}
if (A <0xC000) MMC3_Sync();
}
void MMC3_power (CartInfo *info) {
SetReadHandler (0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0xFFFF, MMC3_write);
MMC3_reg[0] =0; MMC3_reg[1] =2; MMC3_reg[2] =4; MMC3_reg[3] =5; MMC3_reg[4] =6; MMC3_reg[5] =7; MMC3_reg[6] =0; MMC3_reg[7] =1;
MMC3_index =MMC3_mirroring =MMC3_wramEnable =MMC3_reloadValue =MMC3_reloadRequest =MMC3_irqEnable =MMC3_counter =0;
MMC3_Sync();
}
void MMC3_restore (int version) {
MMC3_Sync();
}
void MMC3_init (CartInfo *info, void (*sync)()) {
MMC3_init_enhanced(info, sync, MMC3_TYPE_SHARP, 8);
}
void MMC3_init_enhanced (CartInfo *info, void (*sync)(), uint8 type, uint8 regs) {
MMC3_type =type;
MMC3_setNumberOfRegs(regs);
MMC3_Sync =sync;
MMC3_setBankCallback(MMC3_getPRGBank, MMC3_getCHRBank);
MMC3_setWRAMCallback(CartBR, CartBW);
info->Power =MMC3_power;
info->Reset =MMC3_Sync;
GameStateRestore = MMC3_restore;
GameHBIRQHook =MMC3_clockCounter;
AddExState(MMC3_StateRegs, ~0, 0, 0);
}
void MMC3_setNumberOfRegs (uint8 num) {
MMC3_regMask =num -1;
MMC3_stateRegs[0].s =num;
}
void MMC3_setBankCallback (uint16 (*prg)(uint8), uint16 (*chr)(uint8)) {
MMC3_GetPRGBank =prg;
MMC3_GetCHRBank =chr;
}
void MMC3_setWRAMCallback (FP_FASTAPASS(1)(*read) (uint32), FP_FASTAPASS(2)(*write)(uint32,uint8)) {
MMC3_readWRAM =read;
MMC3_writeWRAM =write;
}

75
src/boards/hardware/MMC3.h
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@@ -1,75 +0,0 @@
/* FCE Ultra - NES/Famicom Emulator
*
* Copyright notice for this file:
* Copyright (C) 2024 NewRisingSun
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _MMC3A_H
#define _MMC3A_H
#include "mapinc.h"
#define MMC3_TYPE_NEC 0
#define MMC3_TYPE_SHARP 1
extern uint8 MMC3_type;
extern uint8 MMC3_index;
extern uint8 MMC3_reg[16];
extern uint8 MMC3_regMask;
extern uint8 MMC3_mirroring;
extern uint8 MMC3_wramEnable;
extern uint8 MMC3_reloadValue;
extern uint8 MMC3_reloadRequest;
extern uint8 MMC3_irqEnable;
extern uint8 MMC3_counter;
static SFORMAT MMC3_stateRegs[] ={
{ MMC3_reg, 8, "REGS" },
{ &MMC3_index, 1, "CMD" },
{ &MMC3_mirroring, 1, "A000" },
{ &MMC3_wramEnable, 1, "A001" },
{ &MMC3_reloadRequest, 1, "IRQR" },
{ &MMC3_counter, 1, "IRQC" },
{ &MMC3_reloadValue, 1, "IRQL" },
{ &MMC3_irqEnable, 1, "IRQA" },
{ 0 }
};
extern void (*MMC3_Sync)();
extern uint16 (*MMC3_GetPRGBank)(uint8);
extern uint16 (*MMC3_GetCHRBank)(uint8);
extern uint8 FP_FASTAPASS(1) (*MMC3_ReadWRAM) (uint32);
extern void FP_FASTAPASS(2) (*MMC3_WriteWRAM)(uint32, uint8);
void MMC3_syncWRAM ();
uint16 MMC3_getPRGBank (uint8);
uint16 MMC3_getCHRBank (uint8);
void MMC3_syncPRG (int, int);
void MMC3_syncCHR (int, int);
void MMC3_syncMirror ();
void MMC3_clockCounter ();
DECLFW(MMC3_write);
void MMC3_power (CartInfo *);
void MMC3_restore (int);
void MMC3_init (CartInfo *, void (*)());
void MMC3_init_enhanced (CartInfo *, void (*)(), uint8, uint8);
void MMC3_setNumberOfRegs (uint8);
void MMC3_setBankCallback (uint16 (*)(uint8), uint16 (*)(uint8));
void MMC3_setWRAMCallback (FP_FASTAPASS(1)(*) (uint32), FP_FASTAPASS(2)(*)(uint32,uint8));
#endif

18
src/boards/hardware/MMC6.c
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#include "mapinc.h"
DECLFR(MMC6_read0) {
return 0;
}
void MMC6_syncWRAM () {
uint16 A;
setprg4r(0x10, 0x7000, OR <<1);
for (A =0x7000; A <=0x7FFF; A |=0x400) {
/* "If neither bank is enabled for reading, the $7000-$7FFF area is open bus. If only one bank is enabled for reading, the other reads back as zero." */
SetReadHandler(A |0x000, A |0x1FF, ~index &0x20 || ~MMC3_wramEnable &0x20 && ~MMC3_wramEnable &0x80? NULL: ~MMC3_wramEnable &0x20 && MMC3_wramEnable &0x80? MMC6_read0: CartBR);
SetReadHandler(A |0x200, A |0x3FF, ~index &0x20 || ~MMC3_wramEnable &0x20 && ~MMC3_wramEnable &0x80? NULL: ~MMC3_wramEnable &0x80 && MMC3_wramEnable &0x20? MMC6_read0: CartBR);
/* "The write-enable bits only have effect if that bank is enabled for reading, otherwise the bank is not writable." */
SetWriteHandler(A |0x000, A |0x1FF, index &0x20 && MMC3_wramEnable &0x20 && MMC3_wramEnable &0x10? CartWR: NULL);
SetWriteHandler(A |0x200, A |0x3FF, index &0x20 && MMC3_wramEnable &0x80 && MMC3_wramEnable &0x40? CartWR: NULL);
}
}