Merge pull request #506 from NRS-NewRisingSun/mappers2
Mappers 351, 394, 435. 432 correction.
This commit is contained in:
Autechre
295
src/boards/351.c
Normal file
295
src/boards/351.c
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@@ -0,0 +1,295 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2022 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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static uint8 reg[4], dip;
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static uint8 MMC1_reg[4], MMC1_shift, MMC1_count, MMC1_filter;
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static uint8 MMC3_reg[8], MMC3_index, MMC3_mirroring, MMC3_wram, MMC3_reload, MMC3_count, MMC3_irq;
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static uint8 VRC4_prg[2];
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static uint8 VRC4_mirroring;
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static uint8 VRC4_misc;
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static uint16 VRC4_chr[8];
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static uint8 VRCIRQ_latch;
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static uint8 VRCIRQ_mode;
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static uint8 VRCIRQ_count;
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static signed short int VRCIRQ_cycles;
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static SFORMAT stateRegs[] = {
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{ reg, 4, "REGS" },
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{ &dip, 1, "DIPS" },
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{ MMC1_reg, 4, "MMC1" },
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{ &MMC1_shift, 1, "M1SH" },
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{ &MMC1_count, 1, "M1CN" },
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{ &MMC1_filter, 1, "M1FI" },
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{ MMC3_reg, 1, "MMC3" },
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{ &MMC3_index, 1, "M3IX" },
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{ &MMC3_mirroring, 1, "M3MI" },
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{ &MMC3_wram, 1, "M3WR" },
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{ &MMC3_reload, 1, "M3RL" },
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{ &MMC3_count, 1, "M3CN" },
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{ &MMC3_irq, 1, "M3IQ" },
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{ VRC4_prg, 2, "V4PR" },
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{ &VRC4_mirroring, 1, "V4MI" },
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{ &VRC4_misc, 1, "V4MS" },
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{ VRC4_chr, 16, "V4CH" },
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{ &VRCIRQ_latch, 1, "VILA" },
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{ &VRCIRQ_mode, 1, "VIMO" },
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{ &VRCIRQ_count, 1, "VICO" },
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{ &VRCIRQ_cycles, 2, "VICY" },
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{ 0 }
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};
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static void sync () {
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int prgAND =reg[2] &0x04? 0x0F: 0x1F;
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int prgOR =reg[1] >>1;
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if (reg[2] &0x80) { /* NROM mode */
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if (reg[2] &0x04) { /* NROM-128 */
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setprg16(0x8000, prgOR >>1);
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setprg16(0xC000, prgOR >>1);
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} else /* NROM-256 */
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setprg32(0x8000, prgOR >>2);
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} else
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if (~reg[0] &0x02) { /* MMC3 mode */
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setprg8(0x8000 ^(MMC3_index <<8 &0x4000), MMC3_reg[6] &prgAND | prgOR &~prgAND);
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setprg8(0xA000, MMC3_reg[7] &prgAND | prgOR &~prgAND);
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setprg8(0xC000 ^(MMC3_index <<8 &0x4000), 0xFE &prgAND | prgOR &~prgAND);
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setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
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} else
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if (reg[0] &0x01) { /* VRC4 mode */
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setprg8(0x8000 ^(VRC4_misc <<13 &0x4000), VRC4_prg[0] &prgAND | prgOR &~prgAND);
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setprg8(0xA000, VRC4_prg[1] &prgAND | prgOR &~prgAND);
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setprg8(0xC000 ^(VRC4_misc <<13 &0x4000), 0xFE &prgAND | prgOR &~prgAND);
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setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
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} else { /* MMC1 mode */
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prgAND >>=1;
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prgOR >>=1;
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if (MMC1_reg[0] &0x8) { /* 16 KiB mode */
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if (MMC1_reg[0] &0x04) { /* OR logic */
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setprg16(0x8000, MMC1_reg[3] &prgAND | prgOR &~prgAND);
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setprg16(0xC000, 0xFF &prgAND | prgOR &~prgAND);
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} else { /* AND logic */
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setprg16(0x8000, 0x00 &prgAND | prgOR &~prgAND);
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setprg16(0xC000, MMC1_reg[3] &prgAND | prgOR &~prgAND);
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}
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} else
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setprg32(0x8000, (MMC1_reg[3] &prgAND | prgOR &~prgAND) >>1);
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}
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int chrAND =reg[2] &0x10? 0x1F: reg[2] &0x20? 0x7F: 0xFF;
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int chrOR =reg[0] <<1;
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if (reg[2] &0x40) /* CNROM mode */
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setchr8(chrOR >>3);
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else
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if (~reg[0] &0x02) { /* MMC3 mode */
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setchr1(0x0000 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] &0xFE)&chrAND | chrOR &~chrAND);
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setchr1(0x0400 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] |0x01)&chrAND | chrOR &~chrAND);
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setchr1(0x0800 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] &0xFE)&chrAND | chrOR &~chrAND);
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setchr1(0x0C00 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] |0x01)&chrAND | chrOR &~chrAND);
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setchr1(0x1000 ^(MMC3_index <<5 &0x1000), MMC3_reg[2] &chrAND | chrOR &~chrAND);
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setchr1(0x1400 ^(MMC3_index <<5 &0x1000), MMC3_reg[3] &chrAND | chrOR &~chrAND);
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setchr1(0x1800 ^(MMC3_index <<5 &0x1000), MMC3_reg[4] &chrAND | chrOR &~chrAND);
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setchr1(0x1C00 ^(MMC3_index <<5 &0x1000), MMC3_reg[5] &chrAND | chrOR &~chrAND);
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} else
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if (reg[0] &0x01) { /* VRC4 mode */
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setchr1(0x0000, VRC4_chr[0] &chrAND | chrOR &~chrAND);
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setchr1(0x0400, VRC4_chr[1] &chrAND | chrOR &~chrAND);
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setchr1(0x0800, VRC4_chr[2] &chrAND | chrOR &~chrAND);
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setchr1(0x0C00, VRC4_chr[3] &chrAND | chrOR &~chrAND);
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setchr1(0x1000, VRC4_chr[4] &chrAND | chrOR &~chrAND);
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setchr1(0x1400, VRC4_chr[5] &chrAND | chrOR &~chrAND);
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setchr1(0x1800, VRC4_chr[6] &chrAND | chrOR &~chrAND);
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setchr1(0x1C00, VRC4_chr[7] &chrAND | chrOR &~chrAND);
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} else { /* MMC1 mode */
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chrAND >>=2;
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chrOR >>=2;
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if (MMC1_reg[0] &0x10) { /* 4 KiB mode */
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setchr4(0x0000, MMC1_reg[1] &chrAND | chrOR &~chrAND);
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setchr4(0x1000, MMC1_reg[2] &chrAND | chrOR &~chrAND);
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} else /* 8 KiB mode */
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setchr8((MMC1_reg[1] &chrAND |chrOR &~chrAND) >>1);
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}
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if (~reg[0] &0x02) /* MMC3 mode */
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setmirror(MMC3_mirroring &1 ^1);
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else
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if ( reg[0] &0x01) /* VRC4 mode */
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setmirror(VRC4_mirroring &3 ^(VRC4_mirroring &2? 0: 1));
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else /* MMC1 mode */
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setmirror(MMC1_reg[0] &3 ^3);
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}
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static DECLFW(writeMMC3) {
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switch(A &0xE001) {
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case 0x8000: MMC3_index =V; sync(); break;
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case 0x8001: MMC3_reg[MMC3_index &7] =V; sync(); break;
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case 0xA000: MMC3_mirroring =V; sync(); break;
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case 0xA001: MMC3_wram =V; sync(); break;
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case 0xC000: MMC3_reload =V; break;
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case 0xC001: MMC3_count =0; break;
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case 0xE000: MMC3_irq =0; X6502_IRQEnd(FCEU_IQEXT); break;
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case 0xE001: MMC3_irq =1; break;
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}
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}
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static DECLFW(writeMMC1) {
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if (V &0x80) {
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MMC1_shift =MMC1_count =0;
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MMC1_reg[0] |=0x0C;
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sync();
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} else
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if (!MMC1_filter) {
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MMC1_shift |=(V &1) <<MMC1_count++;
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if (MMC1_count ==5) {
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MMC1_reg[A >>13 &3] =MMC1_shift;
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MMC1_count =0;
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MMC1_shift =0;
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sync();
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}
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}
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MMC1_filter =2;
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}
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static DECLFW(writeVRC4) {
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uint8 index;
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A =A &0xF000 | (A &0x800? ((A &8? 1: 0) | (A &4? 2: 0)): ((A &4? 1: 0) | (A &8? 2: 0)));
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switch (A &0xF000) {
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case 0x8000: case 0xA000:
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VRC4_prg[A >>13 &1] =V;
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sync();
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break;
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case 0x9000:
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if (~A &2)
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VRC4_mirroring =V;
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else
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if (~A &1)
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VRC4_misc =V;
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sync();
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break;
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case 0xF000:
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switch (A &3) {
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case 0: VRCIRQ_latch =VRCIRQ_latch &0xF0 | V &0x0F; break;
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case 1: VRCIRQ_latch =VRCIRQ_latch &0x0F | V <<4; break;
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case 2: VRCIRQ_mode =V;
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if (VRCIRQ_mode &0x02) {
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VRCIRQ_count =VRCIRQ_latch;
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VRCIRQ_cycles =341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3: VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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break;
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default:
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index =(A -0xB000) >>11 | A >>1 &1;
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if (A &1)
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VRC4_chr[index] =VRC4_chr[index] & 0x0F | V <<4;
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else
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VRC4_chr[index] =VRC4_chr[index] &~0x0F | V &0x0F;
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sync();
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break;
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}
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}
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static void FP_FASTAPASS(1) cpuCycle(int a) {
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if ((reg[0] &3) ==3) while (a--) { /* VRC4 mode */
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if (VRCIRQ_mode &0x02 && (VRCIRQ_mode &0x04 || (VRCIRQ_cycles -=3) <=0)) {
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if (~VRCIRQ_mode &0x04) VRCIRQ_cycles +=341;
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if (!++VRCIRQ_count) {
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VRCIRQ_count =VRCIRQ_latch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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if (MMC1_filter) MMC1_filter--;
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}
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static void horizontalBlanking(void) {
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if (~reg[0] &2) { /* MMC3 mode */
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MMC3_count =!MMC3_count? MMC3_reload: --MMC3_count;
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if (!MMC3_count && MMC3_irq) X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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static void applyMode() {
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switch (reg[0] &3) {
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case 0:
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case 1: SetWriteHandler(0x8000, 0xFFFF, writeMMC3); break;
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case 2: SetWriteHandler(0x8000, 0xFFFF, writeMMC1); break;
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case 3: SetWriteHandler(0x8000, 0xFFFF, writeVRC4); break;
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}
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}
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static void Mapper351_restore (int version) {
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applyMode();
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sync();
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}
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static DECLFR(readDIP) {
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return dip;
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}
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static DECLFW(writeReg) {
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uint8 previousMode =reg[0] &3;
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reg[A &3] =V;
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if ((reg[0] &3) !=previousMode) applyMode();
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sync();
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}
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static void Mapper351_power(void) {
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int i;
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for (i =0; i <4; i++) reg[i] =0;
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for (i =0; i <4; i++) MMC1_reg[i] =0;
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for (i =0; i <8; i++) MMC3_reg[i] =0;
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for (i =0; i <2; i++) VRC4_prg[i] =0;
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for (i =0; i <8; i++) VRC4_chr[i] =0;
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MMC1_shift =MMC1_count =MMC1_filter =0;
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MMC1_reg[0] =0x0C;
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MMC3_index =MMC3_mirroring =MMC3_wram =MMC3_reload =MMC3_count =MMC3_irq =0;
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VRC4_mirroring =VRC4_misc =VRCIRQ_latch =VRCIRQ_mode =VRCIRQ_count =VRCIRQ_cycles =0;
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dip =0;
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetReadHandler(0x5000, 0x5FFF, readDIP);
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SetWriteHandler(0x5000, 0x5FFF, writeReg);
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applyMode();
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sync();
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}
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static void Mapper351_reset (void) {
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int i;
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for (i =0; i <4; i++) reg[i] =0;
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dip++;
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applyMode();
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sync();
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}
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void Mapper351_Init (CartInfo *info) {
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info->Reset = Mapper351_reset;
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info->Power = Mapper351_power;
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MapIRQHook = cpuCycle;
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GameHBIRQHook = horizontalBlanking;
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GameStateRestore = Mapper351_restore;
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AddExState(stateRegs, ~0, 0, 0);
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}
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@@ -44,7 +44,7 @@ static DECLFR(M432Read) {
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static DECLFW(M432Write) {
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EXPREGS[A & 1] = V;
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if (~A &1 && ~V &1) EXPREGS[1] =0; /* Writing 0 to register 0 clears register 1 */
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if (~A &1 && ~V &1) EXPREGS[1] &=~0x20; /* Writing 0 to register 0 clears register 1's DIP bit */
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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@@ -730,3 +730,31 @@ static void M409Sync(void) {
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void Mapper409_Init(CartInfo *info) {
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Latch_Init(info, M409Sync, NULL, 0x0000, 0xC000, 0xCFFF, 0);
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}
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/*------------------ Map 435 ---------------------------*/
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static void M435Sync(void) {
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int p =latche >>2 &0x1F | latche >>3 &0x20 | latche >>4 &0x40;
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if (latche &0x200) {
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if (latche &0x001) {
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setprg16(0x8000, p);
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setprg16(0xC000, p);
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} else {
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setprg32(0x8000, p >> 1);
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}
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} else {
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setprg16(0x8000, p);
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setprg16(0xC000, p | 7);
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}
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if (latche &0x800)
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SetupCartCHRMapping(0, CHRptr[0], 0x2000, 0);
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else
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SetupCartCHRMapping(0, CHRptr[0], 0x2000, 1);
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setmirror(latche &0x002? MI_H: MI_V);
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setchr8(0);
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}
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void Mapper435_Init(CartInfo *info) {
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Latch_Init(info, M435Sync, NULL, 0x0000, 0x8000, 0xFFFF, 1);
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}
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@@ -21,6 +21,7 @@
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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void (*sync)(void);
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static uint8 allowExtendedMirroring;
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@@ -45,6 +46,7 @@ static uint8 adder;
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static uint8 test;
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static uint8 dipSwitch;
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static uint8 cpuWriteHandlersSet;
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static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
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static SFORMAT JYASIC_stateRegs[] = {
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@@ -238,7 +240,7 @@ static void ppuScanline(void)
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}
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}
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void FP_FASTAPASS(1) cpuCycle(int a)
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static void FP_FASTAPASS(1) cpuCycle(int a)
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{
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if ((irqControl &0x03) ==0x00)
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while (a--)
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@@ -373,6 +375,16 @@ static DECLFW(writeMode)
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sync();
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}
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static void JYASIC_restoreWriteHandlers(void)
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{
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int i;
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if (cpuWriteHandlersSet)
|
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{
|
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for (i =0; i <0x10000; i++) SetWriteHandler(i, i, cpuWriteHandlers[i]);
|
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cpuWriteHandlersSet =0;
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}
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}
|
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|
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static void JYASIC_power(void)
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{
|
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unsigned int i;
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@@ -386,8 +398,10 @@ static void JYASIC_power(void)
|
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SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
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SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
|
||||
|
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JYASIC_restoreWriteHandlers();
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||||
for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
|
||||
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
|
||||
cpuWriteHandlersSet =1;
|
||||
|
||||
SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
|
||||
SetReadHandler(0x6000, 0xFFFF, CartBR);
|
||||
@@ -423,6 +437,7 @@ static void JYASIC_restore (int version)
|
||||
|
||||
void JYASIC_init (CartInfo *info)
|
||||
{
|
||||
cpuWriteHandlersSet =0;
|
||||
info->Reset = JYASIC_reset;
|
||||
info->Power = JYASIC_power;
|
||||
info->Close = JYASIC_close;
|
||||
@@ -669,3 +684,114 @@ void Mapper421_Init(CartInfo *info)
|
||||
sync =sync421;
|
||||
JYASIC_init(info);
|
||||
}
|
||||
|
||||
/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */
|
||||
static uint8 HSK007Reg[4];
|
||||
void sync394 (void) /* Called when J.Y. ASIC is active */
|
||||
{
|
||||
int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
|
||||
int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
|
||||
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
|
||||
int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
|
||||
syncPRG(0x1F, prgOR);
|
||||
syncCHR(0xFF, chrOR);
|
||||
syncNT (0xFF, chrOR);
|
||||
}
|
||||
static void Mapper394_PWrap(uint32 A, uint8 V)
|
||||
{
|
||||
int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
|
||||
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
|
||||
if (HSK007Reg[1] &0x08)
|
||||
setprg8(A, V &prgAND | prgOR &~prgAND);
|
||||
else
|
||||
if (A ==0x8000)
|
||||
setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2);
|
||||
|
||||
}
|
||||
static void Mapper394_CWrap(uint32 A, uint8 V)
|
||||
{
|
||||
int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
|
||||
int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
|
||||
setchr1(A, V &chrAND | chrOR &~chrAND);
|
||||
}
|
||||
static DECLFW(Mapper394_Write)
|
||||
{
|
||||
uint8 oldMode =HSK007Reg[1];
|
||||
A &=3;
|
||||
HSK007Reg[A] =V;
|
||||
if (A ==1)
|
||||
{
|
||||
if (~oldMode &0x10 && V &0x10) JYASIC_power();
|
||||
if ( oldMode &0x10 && ~V &0x10)
|
||||
{
|
||||
JYASIC_restoreWriteHandlers();
|
||||
GenMMC3Power();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (HSK007Reg[1] &0x10)
|
||||
sync();
|
||||
else
|
||||
{
|
||||
FixMMC3PRG(MMC3_cmd);
|
||||
FixMMC3CHR(MMC3_cmd);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
static void Mapper394_restore (int version)
|
||||
{
|
||||
int i;
|
||||
JYASIC_restoreWriteHandlers();
|
||||
if (HSK007Reg[1] &0x10)
|
||||
{
|
||||
SetWriteHandler(0x5000, 0x5FFF, writeALU);
|
||||
SetWriteHandler(0x6000, 0x7fff, CartBW);
|
||||
SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
|
||||
SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
|
||||
SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
|
||||
SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
|
||||
SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
|
||||
SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
|
||||
|
||||
for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
|
||||
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
|
||||
cpuWriteHandlersSet =1;
|
||||
|
||||
SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
|
||||
SetReadHandler(0x6000, 0xFFFF, CartBR);
|
||||
sync();
|
||||
}
|
||||
else
|
||||
{
|
||||
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
|
||||
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
|
||||
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
||||
FixMMC3PRG(MMC3_cmd);
|
||||
FixMMC3CHR(MMC3_cmd);
|
||||
}
|
||||
}
|
||||
static void Mapper394_power(void)
|
||||
{
|
||||
HSK007Reg[0] =0x00;
|
||||
HSK007Reg[1] =0x0F;
|
||||
HSK007Reg[2] =0x00;
|
||||
HSK007Reg[3] =0x10;
|
||||
GenMMC3Power();
|
||||
SetWriteHandler(0x5000, 0x5FFF, Mapper394_Write);
|
||||
}
|
||||
|
||||
void Mapper394_Init(CartInfo *info)
|
||||
{
|
||||
allowExtendedMirroring =1;
|
||||
sync =sync394;
|
||||
JYASIC_init(info);
|
||||
GenMMC3_Init(info, 128, 128, 0, 0);
|
||||
pwrap =Mapper394_PWrap;
|
||||
cwrap =Mapper394_CWrap;
|
||||
info->Reset = Mapper394_power;
|
||||
info->Power = Mapper394_power;
|
||||
AddExState(HSK007Reg, 4, 0, "HSK ");
|
||||
GameStateRestore = Mapper394_restore;
|
||||
}
|
||||
|
||||
@@ -754,6 +754,7 @@ INES_BOARD_BEGIN()
|
||||
INES_BOARD( "830118C", 348, BMC830118C_Init )
|
||||
INES_BOARD( "G-146", 349, BMCG146_Init )
|
||||
INES_BOARD( "891227", 350, BMC891227_Init )
|
||||
INES_BOARD( "Techline XB", 351, Mapper351_Init )
|
||||
INES_BOARD( "Super Mario Family", 353, Mapper353_Init )
|
||||
INES_BOARD( "3D-BLOCK", 355, UNL3DBlock_Init )
|
||||
INES_BOARD( "7-in-1 Rockman (JY-208)", 356, Mapper356_Init )
|
||||
@@ -784,10 +785,11 @@ INES_BOARD_BEGIN()
|
||||
INES_BOARD( "Realtec 8031", 390, Mapper390_Init )
|
||||
INES_BOARD( "BS-110", 391, Mapper391_Init )
|
||||
INES_BOARD( "820720C", 393, Mapper393_Init )
|
||||
INES_BOARD( "HSK007", 394, Mapper394_Init )
|
||||
INES_BOARD( "Realtec 8210", 395, Mapper395_Init )
|
||||
INES_BOARD( "YY850437C", 396, Mapper396_Init )
|
||||
INES_BOARD( "YY850437C", 396, Mapper396_Init )
|
||||
INES_BOARD( "YY850439C", 397, Mapper397_Init )
|
||||
INES_BOARD( "BMC Super 19-in-1 (VIP19)", 401, Mapper401_Init )
|
||||
INES_BOARD( "BMC Super 19-in-1 (VIP19)",401, Mapper401_Init )
|
||||
INES_BOARD( "831019C J-2282", 402, J2282_Init )
|
||||
INES_BOARD( "89433", 403, Mapper403_Init )
|
||||
INES_BOARD( "JY012005", 404, Mapper404_Init )
|
||||
@@ -806,6 +808,7 @@ INES_BOARD_BEGIN()
|
||||
INES_BOARD( "Realtec 8090", 432, Mapper432_Init )
|
||||
INES_BOARD( "NC-20MB", 433, Mapper433_Init )
|
||||
INES_BOARD( "S-009", 434, Mapper434_Init )
|
||||
INES_BOARD( "F-1002", 435, Mapper435_Init )
|
||||
INES_BOARD( "820401/T-217", 436, Mapper436_Init )
|
||||
INES_BOARD( "NTDEC TH2348", 437, Mapper437_Init )
|
||||
INES_BOARD( "K-3071", 438, Mapper438_Init )
|
||||
|
||||
@@ -267,6 +267,7 @@ void Mapper319_Init(CartInfo *);
|
||||
void Mapper326_Init(CartInfo *);
|
||||
void Mapper330_Init(CartInfo *);
|
||||
void Mapper334_Init(CartInfo *);
|
||||
void Mapper351_Init(CartInfo *);
|
||||
void Mapper353_Init(CartInfo *);
|
||||
void Mapper356_Init(CartInfo *);
|
||||
void Mapper357_Init(CartInfo *);
|
||||
@@ -294,6 +295,7 @@ void Mapper389_Init(CartInfo *);
|
||||
void Mapper390_Init(CartInfo *);
|
||||
void Mapper391_Init(CartInfo *);
|
||||
void Mapper393_Init(CartInfo *);
|
||||
void Mapper394_Init(CartInfo *);
|
||||
void Mapper395_Init(CartInfo *);
|
||||
void Mapper396_Init(CartInfo *);
|
||||
void Mapper397_Init(CartInfo *);
|
||||
@@ -315,6 +317,7 @@ void Mapper431_Init(CartInfo *);
|
||||
void Mapper432_Init(CartInfo *);
|
||||
void Mapper433_Init(CartInfo *);
|
||||
void Mapper434_Init(CartInfo *);
|
||||
void Mapper435_Init(CartInfo *);
|
||||
void Mapper436_Init(CartInfo *);
|
||||
void Mapper437_Init(CartInfo *);
|
||||
void Mapper438_Init(CartInfo *);
|
||||
|
||||
Reference in New Issue
Block a user