diff --git a/src/boards/351.c b/src/boards/351.c
new file mode 100644
index 0000000..79322e4
--- /dev/null
+++ b/src/boards/351.c
@@ -0,0 +1,295 @@
+/* FCE Ultra - NES/Famicom Emulator
+ *
+ * Copyright notice for this file:
+ *  Copyright (C) 2022 NewRisingSun
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include "mapinc.h"
+
+static uint8 reg[4], dip;
+static uint8 MMC1_reg[4], MMC1_shift, MMC1_count, MMC1_filter;
+static uint8 MMC3_reg[8], MMC3_index, MMC3_mirroring, MMC3_wram, MMC3_reload, MMC3_count, MMC3_irq;
+static uint8 VRC4_prg[2];
+static uint8 VRC4_mirroring;
+static uint8 VRC4_misc;
+static uint16 VRC4_chr[8];
+static uint8 VRCIRQ_latch;
+static uint8 VRCIRQ_mode;
+static uint8 VRCIRQ_count;
+static signed short int VRCIRQ_cycles;
+
+static SFORMAT stateRegs[] = {
+	{ reg,             4, "REGS" },
+	{ &dip,            1, "DIPS" },
+	{ MMC1_reg,        4, "MMC1" },
+	{ &MMC1_shift,     1, "M1SH" },
+	{ &MMC1_count,     1, "M1CN" },
+	{ &MMC1_filter,    1, "M1FI" },
+	{ MMC3_reg,        1, "MMC3" },
+	{ &MMC3_index,     1, "M3IX" },
+	{ &MMC3_mirroring, 1, "M3MI" },
+	{ &MMC3_wram,      1, "M3WR" },
+	{ &MMC3_reload,    1, "M3RL" },
+	{ &MMC3_count,     1, "M3CN" },
+	{ &MMC3_irq,       1, "M3IQ" },
+	{ VRC4_prg,        2, "V4PR" },
+	{ &VRC4_mirroring, 1, "V4MI" },
+	{ &VRC4_misc,      1, "V4MS" },
+	{ VRC4_chr,       16, "V4CH" },
+	{ &VRCIRQ_latch,   1, "VILA" },
+	{ &VRCIRQ_mode,    1, "VIMO" },
+	{ &VRCIRQ_count,   1, "VICO" },
+	{ &VRCIRQ_cycles,  2, "VICY" },
+	{ 0 }
+};
+
+
+static void sync () {
+	int prgAND =reg[2] &0x04? 0x0F: 0x1F;
+	int prgOR  =reg[1] >>1;
+	if (reg[2] &0x80) { /* NROM mode */
+		if (reg[2] &0x04) { /* NROM-128 */
+			setprg16(0x8000, prgOR >>1);
+			setprg16(0xC000, prgOR >>1);
+		} else      /* NROM-256 */
+			setprg32(0x8000, prgOR >>2);
+	} else
+	if (~reg[0] &0x02) { /* MMC3 mode */
+		setprg8(0x8000 ^(MMC3_index <<8 &0x4000), MMC3_reg[6] &prgAND | prgOR &~prgAND);
+		setprg8(0xA000,                           MMC3_reg[7] &prgAND | prgOR &~prgAND);
+		setprg8(0xC000 ^(MMC3_index <<8 &0x4000),        0xFE &prgAND | prgOR &~prgAND);
+		setprg8(0xE000,                                  0xFF &prgAND | prgOR &~prgAND);
+	} else
+	if (reg[0] &0x01) { /* VRC4 mode */
+		setprg8(0x8000 ^(VRC4_misc <<13 &0x4000), VRC4_prg[0] &prgAND | prgOR &~prgAND);
+		setprg8(0xA000,                           VRC4_prg[1] &prgAND | prgOR &~prgAND);
+		setprg8(0xC000 ^(VRC4_misc <<13 &0x4000),        0xFE &prgAND | prgOR &~prgAND);
+		setprg8(0xE000,                                  0xFF &prgAND | prgOR &~prgAND);
+	} else { /* MMC1 mode */
+		prgAND >>=1;
+		prgOR  >>=1;
+		if (MMC1_reg[0] &0x8) { /* 16 KiB mode */
+			if (MMC1_reg[0] &0x04) { /* OR logic */
+				setprg16(0x8000, MMC1_reg[3] &prgAND | prgOR &~prgAND);
+				setprg16(0xC000,        0xFF &prgAND | prgOR &~prgAND);
+			} else {                 /* AND logic */
+				setprg16(0x8000,        0x00 &prgAND | prgOR &~prgAND);
+				setprg16(0xC000, MMC1_reg[3] &prgAND | prgOR &~prgAND);
+			}
+		} else
+			setprg32(0x8000, (MMC1_reg[3] &prgAND | prgOR &~prgAND) >>1);
+	}
+	
+	int chrAND =reg[2] &0x10? 0x1F: reg[2] &0x20? 0x7F: 0xFF;
+	int chrOR  =reg[0] <<1;
+	if (reg[2] &0x40)  /* CNROM mode */
+		setchr8(chrOR >>3);
+	else
+	if (~reg[0] &0x02) { /* MMC3 mode */
+		setchr1(0x0000 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] &0xFE)&chrAND | chrOR &~chrAND);
+		setchr1(0x0400 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] |0x01)&chrAND | chrOR &~chrAND);
+		setchr1(0x0800 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] &0xFE)&chrAND | chrOR &~chrAND);
+		setchr1(0x0C00 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] |0x01)&chrAND | chrOR &~chrAND);
+		setchr1(0x1000 ^(MMC3_index <<5 &0x1000), MMC3_reg[2]       &chrAND | chrOR &~chrAND);
+		setchr1(0x1400 ^(MMC3_index <<5 &0x1000), MMC3_reg[3]       &chrAND | chrOR &~chrAND);
+		setchr1(0x1800 ^(MMC3_index <<5 &0x1000), MMC3_reg[4]       &chrAND | chrOR &~chrAND);
+		setchr1(0x1C00 ^(MMC3_index <<5 &0x1000), MMC3_reg[5]       &chrAND | chrOR &~chrAND);
+	} else
+	if (reg[0] &0x01) { /* VRC4 mode */
+		setchr1(0x0000, VRC4_chr[0] &chrAND | chrOR &~chrAND);
+		setchr1(0x0400, VRC4_chr[1] &chrAND | chrOR &~chrAND);
+		setchr1(0x0800, VRC4_chr[2] &chrAND | chrOR &~chrAND);
+		setchr1(0x0C00, VRC4_chr[3] &chrAND | chrOR &~chrAND);
+		setchr1(0x1000, VRC4_chr[4] &chrAND | chrOR &~chrAND);
+		setchr1(0x1400, VRC4_chr[5] &chrAND | chrOR &~chrAND);
+		setchr1(0x1800, VRC4_chr[6] &chrAND | chrOR &~chrAND);
+		setchr1(0x1C00, VRC4_chr[7] &chrAND | chrOR &~chrAND);
+	} else { /* MMC1 mode */
+		chrAND >>=2;
+		chrOR  >>=2;
+		if (MMC1_reg[0] &0x10) { /* 4 KiB mode */
+			setchr4(0x0000, MMC1_reg[1] &chrAND | chrOR &~chrAND);
+			setchr4(0x1000, MMC1_reg[2] &chrAND | chrOR &~chrAND);
+		} else                   /* 8 KiB mode */
+			setchr8((MMC1_reg[1] &chrAND |chrOR &~chrAND) >>1);		
+	}
+	
+	if (~reg[0] &0x02)  /* MMC3 mode */
+		setmirror(MMC3_mirroring &1 ^1);
+	else
+	if ( reg[0] &0x01) /* VRC4 mode */
+		setmirror(VRC4_mirroring &3 ^(VRC4_mirroring &2? 0: 1));
+	else               /* MMC1 mode */
+		setmirror(MMC1_reg[0] &3 ^3);
+}
+
+static DECLFW(writeMMC3) {
+	switch(A &0xE001) {
+	case 0x8000: MMC3_index =V;              sync();    break;
+	case 0x8001: MMC3_reg[MMC3_index &7] =V; sync();    break;
+	case 0xA000: MMC3_mirroring =V;          sync();    break;
+	case 0xA001: MMC3_wram =V;               sync();    break;
+	case 0xC000: MMC3_reload =V;                        break;
+	case 0xC001: MMC3_count =0;                         break;
+	case 0xE000: MMC3_irq =0; X6502_IRQEnd(FCEU_IQEXT); break;
+	case 0xE001: MMC3_irq =1;                           break;
+	}
+}
+
+static DECLFW(writeMMC1) {
+	if (V &0x80) {
+		MMC1_shift =MMC1_count =0;
+		MMC1_reg[0] |=0x0C;
+		sync();
+	} else
+	if (!MMC1_filter) {
+		MMC1_shift |=(V &1) <<MMC1_count++;
+		if (MMC1_count ==5) {
+			MMC1_reg[A >>13 &3] =MMC1_shift;
+			MMC1_count =0;
+			MMC1_shift =0;
+			sync();
+		}
+	}
+	MMC1_filter =2;
+}
+
+static DECLFW(writeVRC4) {
+	uint8 index;
+	A =A &0xF000 | (A &0x800? ((A &8? 1: 0) | (A &4? 2: 0)): ((A &4? 1: 0) | (A &8? 2: 0)));
+	switch (A &0xF000) {
+	case 0x8000: case 0xA000:
+		VRC4_prg[A >>13 &1] =V;
+		sync();
+		break;
+	case 0x9000:
+		if (~A &2)
+			VRC4_mirroring =V;
+		else
+		if (~A &1)
+			VRC4_misc =V;
+		sync();
+		break;
+	case 0xF000:
+		switch (A &3) {
+		case 0: VRCIRQ_latch =VRCIRQ_latch &0xF0 | V &0x0F; break;
+		case 1: VRCIRQ_latch =VRCIRQ_latch &0x0F | V <<4;   break;
+		case 2: VRCIRQ_mode =V;
+		        if (VRCIRQ_mode &0x02) {
+				VRCIRQ_count =VRCIRQ_latch;
+				VRCIRQ_cycles =341;
+			}
+			X6502_IRQEnd(FCEU_IQEXT);
+			break;
+		case 3: VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
+			X6502_IRQEnd(FCEU_IQEXT);
+			break;
+		}
+		break;
+	default:
+		index =(A -0xB000) >>11 | A >>1 &1;
+		if (A &1)
+			VRC4_chr[index] =VRC4_chr[index] & 0x0F | V <<4;
+		else
+			VRC4_chr[index] =VRC4_chr[index] &~0x0F | V &0x0F;
+		sync();
+		break;
+	}
+}
+
+static void FP_FASTAPASS(1) cpuCycle(int a) {
+	if ((reg[0] &3) ==3) while (a--) { /* VRC4 mode */
+		if (VRCIRQ_mode &0x02 && (VRCIRQ_mode &0x04 || (VRCIRQ_cycles -=3) <=0)) {
+			if (~VRCIRQ_mode &0x04) VRCIRQ_cycles +=341;
+			if (!++VRCIRQ_count) {
+				VRCIRQ_count =VRCIRQ_latch;
+				X6502_IRQBegin(FCEU_IQEXT);
+			}
+		}
+	}
+	if (MMC1_filter) MMC1_filter--;
+}
+	
+static void horizontalBlanking(void) {
+	if (~reg[0] &2) { /* MMC3 mode */
+		MMC3_count =!MMC3_count? MMC3_reload: --MMC3_count;
+		if (!MMC3_count && MMC3_irq) X6502_IRQBegin(FCEU_IQEXT);
+	}
+}
+
+static void applyMode() {
+	switch (reg[0] &3) {
+	case 0:
+	case 1: SetWriteHandler(0x8000, 0xFFFF, writeMMC3); break;
+	case 2: SetWriteHandler(0x8000, 0xFFFF, writeMMC1); break;	
+	case 3: SetWriteHandler(0x8000, 0xFFFF, writeVRC4); break;
+	}
+}
+
+static void Mapper351_restore (int version) {
+	applyMode();
+	sync();
+}
+
+static DECLFR(readDIP) {
+	return dip;
+}
+
+static DECLFW(writeReg) {
+	uint8 previousMode =reg[0] &3;
+	reg[A &3] =V;
+	if ((reg[0] &3) !=previousMode) applyMode();
+	sync();
+}
+
+static void Mapper351_power(void) {
+	int i;
+	for (i =0; i <4; i++) reg[i] =0;
+	for (i =0; i <4; i++) MMC1_reg[i] =0;
+	for (i =0; i <8; i++) MMC3_reg[i] =0;
+	for (i =0; i <2; i++) VRC4_prg[i] =0;
+	for (i =0; i <8; i++) VRC4_chr[i] =0;
+	MMC1_shift =MMC1_count =MMC1_filter =0;
+	MMC1_reg[0] =0x0C;
+	MMC3_index =MMC3_mirroring =MMC3_wram =MMC3_reload =MMC3_count =MMC3_irq =0;	
+	VRC4_mirroring =VRC4_misc =VRCIRQ_latch =VRCIRQ_mode =VRCIRQ_count =VRCIRQ_cycles =0;
+	dip =0;
+	
+	SetReadHandler(0x6000, 0xFFFF, CartBR);
+	SetReadHandler(0x5000, 0x5FFF, readDIP);
+	SetWriteHandler(0x5000, 0x5FFF, writeReg);
+	applyMode();
+	sync();
+}
+
+static void Mapper351_reset (void) {
+	int i;
+	for (i =0; i <4; i++) reg[i] =0;
+	dip++;
+	applyMode();
+	sync();
+}
+
+void Mapper351_Init (CartInfo *info) {
+	info->Reset = Mapper351_reset;
+	info->Power = Mapper351_power;
+	MapIRQHook = cpuCycle;
+	GameHBIRQHook = horizontalBlanking;
+	GameStateRestore = Mapper351_restore;
+	AddExState(stateRegs, ~0, 0, 0);
+}
+
diff --git a/src/boards/432.c b/src/boards/432.c
index 5c6db48..dbdffa0 100644
--- a/src/boards/432.c
+++ b/src/boards/432.c
@@ -44,7 +44,7 @@ static DECLFR(M432Read) {
 
 static DECLFW(M432Write) {
 	EXPREGS[A & 1] = V;
-	if (~A &1 && ~V &1) EXPREGS[1] =0; /* Writing 0 to register 0 clears register 1 */
+	if (~A &1 && ~V &1) EXPREGS[1] &=~0x20; /* Writing 0 to register 0 clears register 1's DIP bit */
 	FixMMC3PRG(MMC3_cmd);
 	FixMMC3CHR(MMC3_cmd);
 }
diff --git a/src/boards/addrlatch.c b/src/boards/addrlatch.c
index 01c1360..e9bf8b4 100644
--- a/src/boards/addrlatch.c
+++ b/src/boards/addrlatch.c
@@ -730,3 +730,31 @@ static void M409Sync(void) {
 void Mapper409_Init(CartInfo *info) {
 	Latch_Init(info, M409Sync, NULL, 0x0000, 0xC000, 0xCFFF, 0);
 }
+
+/*------------------ Map 435 ---------------------------*/
+static void M435Sync(void) {
+	int p =latche >>2 &0x1F | latche >>3 &0x20 | latche >>4 &0x40;
+	if (latche &0x200) {
+		if (latche &0x001) {
+			setprg16(0x8000, p);
+			setprg16(0xC000, p);
+		} else {
+			setprg32(0x8000, p >> 1);
+		}
+	} else {
+		setprg16(0x8000, p);
+		setprg16(0xC000, p | 7);
+	}
+
+	if (latche &0x800)
+		SetupCartCHRMapping(0, CHRptr[0], 0x2000, 0);
+	else
+		SetupCartCHRMapping(0, CHRptr[0], 0x2000, 1);
+
+	setmirror(latche &0x002? MI_H: MI_V);
+	setchr8(0);
+}
+
+void Mapper435_Init(CartInfo *info) {
+	Latch_Init(info, M435Sync, NULL, 0x0000, 0x8000, 0xFFFF, 1);
+}
diff --git a/src/boards/jyasic.c b/src/boards/jyasic.c
index 0d1cdf1..7ffb0a1 100644
--- a/src/boards/jyasic.c
+++ b/src/boards/jyasic.c
@@ -21,6 +21,7 @@
  */
 
 #include "mapinc.h"
+#include "mmc3.h"
 
 void 	(*sync)(void);
 static uint8	allowExtendedMirroring;
@@ -45,6 +46,7 @@ static uint8	adder;
 static uint8	test;
 static uint8    dipSwitch;
 
+static uint8 cpuWriteHandlersSet;
 static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
 
 static SFORMAT JYASIC_stateRegs[] = {
@@ -238,7 +240,7 @@ static void ppuScanline(void)
    }
 }
 
-void FP_FASTAPASS(1) cpuCycle(int a)
+static void FP_FASTAPASS(1) cpuCycle(int a)
 {
    if ((irqControl &0x03) ==0x00)
       while (a--)
@@ -373,6 +375,16 @@ static DECLFW(writeMode)
 	sync();
 }
 
+static void JYASIC_restoreWriteHandlers(void)
+{
+   int i;
+   if (cpuWriteHandlersSet) 
+   {
+	   for (i =0; i <0x10000; i++) SetWriteHandler(i, i, cpuWriteHandlers[i]);
+	   cpuWriteHandlersSet =0;
+   }
+}
+
 static void JYASIC_power(void)
 {
    unsigned int i;
@@ -386,8 +398,10 @@ static void JYASIC_power(void)
    SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
    SetWriteHandler(0xD000, 0xD7FF, writeMode);    /* D800-DFFF ignored */
 
+   JYASIC_restoreWriteHandlers();
    for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
    SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
+   cpuWriteHandlersSet =1;
 
    SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
    SetReadHandler(0x6000, 0xFFFF, CartBR);
@@ -423,6 +437,7 @@ static void JYASIC_restore (int version)
 
 void JYASIC_init (CartInfo *info)
 {
+   cpuWriteHandlersSet =0;
    info->Reset = JYASIC_reset;
    info->Power = JYASIC_power;
    info->Close = JYASIC_close;
@@ -669,3 +684,114 @@ void Mapper421_Init(CartInfo *info)
 	sync =sync421;
 	JYASIC_init(info);
 }
+
+/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */
+static uint8 HSK007Reg[4];
+void sync394 (void) /* Called when J.Y. ASIC is active */
+{
+	int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
+	int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
+	int prgOR  =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
+	int chrOR  =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
+	syncPRG(0x1F, prgOR);
+	syncCHR(0xFF, chrOR);
+	syncNT (0xFF, chrOR);	
+}
+static void Mapper394_PWrap(uint32 A, uint8 V)
+{
+	int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
+	int prgOR  =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
+	if (HSK007Reg[1] &0x08)
+		setprg8(A, V &prgAND | prgOR &~prgAND);
+	else
+	if (A ==0x8000)
+		setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2);
+	
+}
+static void Mapper394_CWrap(uint32 A, uint8 V)
+{
+	int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
+	int chrOR  =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
+	setchr1(A, V &chrAND | chrOR &~chrAND);
+}
+static DECLFW(Mapper394_Write)
+{
+	uint8 oldMode =HSK007Reg[1];
+	A &=3;
+	HSK007Reg[A] =V;
+	if (A ==1)
+	{		
+		if (~oldMode &0x10 &&  V &0x10) JYASIC_power();
+		if ( oldMode &0x10 && ~V &0x10)
+		{
+			JYASIC_restoreWriteHandlers();
+			GenMMC3Power();
+		}
+	}
+	else
+	{
+		if (HSK007Reg[1] &0x10)
+			sync();
+		else
+		{
+			FixMMC3PRG(MMC3_cmd);
+			FixMMC3CHR(MMC3_cmd);
+		}
+			
+	}
+}
+static void Mapper394_restore (int version)
+{
+	int i;
+	JYASIC_restoreWriteHandlers();
+	if (HSK007Reg[1] &0x10)
+	{		
+		SetWriteHandler(0x5000, 0x5FFF, writeALU);
+		SetWriteHandler(0x6000, 0x7fff, CartBW);
+		SetWriteHandler(0x8000, 0x87FF, writePRG);     /* 8800-8FFF ignored */
+		SetWriteHandler(0x9000, 0x97FF, writeCHRLow);  /* 9800-9FFF ignored */
+		SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
+		SetWriteHandler(0xB000, 0xB7FF, writeNT);      /* B800-BFFF ignored */
+		SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
+		SetWriteHandler(0xD000, 0xD7FF, writeMode);    /* D800-DFFF ignored */
+		
+		for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
+		SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
+		cpuWriteHandlersSet =1;
+		
+		SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
+		SetReadHandler(0x6000, 0xFFFF, CartBR);
+		sync();
+	}
+	else
+	{
+		SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
+		SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
+		SetReadHandler(0x8000, 0xFFFF, CartBR);
+		FixMMC3PRG(MMC3_cmd);
+		FixMMC3CHR(MMC3_cmd);
+	}
+}
+static void Mapper394_power(void)
+{
+	HSK007Reg[0] =0x00;
+	HSK007Reg[1] =0x0F;
+	HSK007Reg[2] =0x00;
+	HSK007Reg[3] =0x10;
+	GenMMC3Power();
+	SetWriteHandler(0x5000, 0x5FFF, Mapper394_Write);
+}
+
+void Mapper394_Init(CartInfo *info)
+{
+	allowExtendedMirroring =1;
+	sync =sync394;
+	JYASIC_init(info);
+	GenMMC3_Init(info, 128, 128, 0, 0);
+	pwrap =Mapper394_PWrap;
+	cwrap =Mapper394_CWrap;
+	info->Reset = Mapper394_power;
+	info->Power = Mapper394_power;
+	AddExState(HSK007Reg, 4, 0, "HSK ");
+	GameStateRestore = Mapper394_restore;
+}
diff --git a/src/ines.c b/src/ines.c
index 97ddef7..4e9baa5 100644
--- a/src/ines.c
+++ b/src/ines.c
@@ -754,6 +754,7 @@ INES_BOARD_BEGIN()
 	INES_BOARD( "830118C",                  348, BMC830118C_Init        )
 	INES_BOARD( "G-146",                    349, BMCG146_Init           )
 	INES_BOARD( "891227",                   350, BMC891227_Init         )
+	INES_BOARD( "Techline XB",              351, Mapper351_Init         )
 	INES_BOARD( "Super Mario Family",       353, Mapper353_Init         )
 	INES_BOARD( "3D-BLOCK",                 355, UNL3DBlock_Init        )
 	INES_BOARD( "7-in-1 Rockman (JY-208)",  356, Mapper356_Init         )
@@ -784,10 +785,11 @@ INES_BOARD_BEGIN()
 	INES_BOARD( "Realtec 8031",             390, Mapper390_Init         )
 	INES_BOARD( "BS-110",                   391, Mapper391_Init         )
 	INES_BOARD( "820720C",                  393, Mapper393_Init         )
+	INES_BOARD( "HSK007",                   394, Mapper394_Init         )
 	INES_BOARD( "Realtec 8210",             395, Mapper395_Init         )
-    INES_BOARD( "YY850437C",                396, Mapper396_Init         )
+	INES_BOARD( "YY850437C",                396, Mapper396_Init         )
 	INES_BOARD( "YY850439C",                397, Mapper397_Init         )
-	INES_BOARD( "BMC Super 19-in-1 (VIP19)", 401, Mapper401_Init         )
+	INES_BOARD( "BMC Super 19-in-1 (VIP19)",401, Mapper401_Init         )
 	INES_BOARD( "831019C J-2282",           402, J2282_Init             )
 	INES_BOARD( "89433",                    403, Mapper403_Init         )
 	INES_BOARD( "JY012005",                 404, Mapper404_Init         )
@@ -806,6 +808,7 @@ INES_BOARD_BEGIN()
 	INES_BOARD( "Realtec 8090",             432, Mapper432_Init         )
 	INES_BOARD( "NC-20MB",                  433, Mapper433_Init         )
 	INES_BOARD( "S-009",                    434, Mapper434_Init         )
+	INES_BOARD( "F-1002",                   435, Mapper435_Init         )
 	INES_BOARD( "820401/T-217",             436, Mapper436_Init         )
 	INES_BOARD( "NTDEC TH2348",             437, Mapper437_Init         )
 	INES_BOARD( "K-3071",                   438, Mapper438_Init         )
diff --git a/src/ines.h b/src/ines.h
index 7a568dd..bdb41a6 100644
--- a/src/ines.h
+++ b/src/ines.h
@@ -267,6 +267,7 @@ void Mapper319_Init(CartInfo *);
 void Mapper326_Init(CartInfo *);
 void Mapper330_Init(CartInfo *);
 void Mapper334_Init(CartInfo *);
+void Mapper351_Init(CartInfo *);
 void Mapper353_Init(CartInfo *);
 void Mapper356_Init(CartInfo *);
 void Mapper357_Init(CartInfo *);
@@ -294,6 +295,7 @@ void Mapper389_Init(CartInfo *);
 void Mapper390_Init(CartInfo *);
 void Mapper391_Init(CartInfo *);
 void Mapper393_Init(CartInfo *);
+void Mapper394_Init(CartInfo *);
 void Mapper395_Init(CartInfo *);
 void Mapper396_Init(CartInfo *);
 void Mapper397_Init(CartInfo *);
@@ -315,6 +317,7 @@ void Mapper431_Init(CartInfo *);
 void Mapper432_Init(CartInfo *);
 void Mapper433_Init(CartInfo *);
 void Mapper434_Init(CartInfo *);
+void Mapper435_Init(CartInfo *);
 void Mapper436_Init(CartInfo *);
 void Mapper437_Init(CartInfo *);
 void Mapper438_Init(CartInfo *);