73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
#define VRC6_chr regByte
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#define VRC6_prg16 regByte[8]
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#define VRC6_prg8 regByte[9]
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#define VRC6_misc regByte[10]
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static void VRC6_sync() {
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int AND =prgAND >>1;
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int OR =prgOR >>1;
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setprg16(0x8000, VRC6_prg16 & AND | OR & ~AND);
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setprg8(0xC000, VRC6_prg8 &prgAND | prgOR &~prgAND);
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setprg8(0xE000, prgAND | prgOR &~prgAND);
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setchr1(0x0000, VRC6_chr[0]);
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setchr1(0x0400, VRC6_chr[1]);
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setchr1(0x0800, VRC6_chr[2]);
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setchr1(0x0C00, VRC6_chr[3]);
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setchr1(0x1000, VRC6_chr[4]);
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setchr1(0x1400, VRC6_chr[5]);
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setchr1(0x1800, VRC6_chr[6]);
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setchr1(0x1C00, VRC6_chr[7]);
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setmirror((VRC6_misc &0xC ^(VRC6_misc &0x8? 0: 0x4)) >>2);
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}
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static DECLFW(VRC6_writeReg) {
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uint8 index;
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switch (A &0xF003) {
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case 0x8000: case 0x8001: case 0x8002: case 0x8003:
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VRC6_prg16 =V;
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sync();
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break;
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case 0xB003:
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VRC6_misc =V;
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sync();
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break;
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case 0xC000: case 0xC001: case 0xC002: case 0xC003:
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VRC6_prg8 =V;
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sync();
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break;
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case 0xD000: case 0xD001: case 0xD002: case 0xD003: case 0xE000: case 0xE001: case 0xE002: case 0xE003:
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index =(A -0xD000) >>10 | A &3;
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VRC6_chr[index] =V;
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sync();
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break;
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case 0xF000:
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VRCIRQ_latch =V;
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break;
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case 0xF001:
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VRCIRQ_mode =V;
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if (VRCIRQ_mode &0x02) {
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VRCIRQ_count =VRCIRQ_latch;
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VRCIRQ_cycles =341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xF002:
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VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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}
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void VRC6_reset(uint8 clearRegs) {
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sync =VRC6_sync;
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prgAND =mapperFlags &2? 0x0F: 0x1F;
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MapIRQHook =VRCIRQ_cpuCycle;
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SetWriteHandler(0x8000, 0xFFFF, VRC6_writeReg);
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sync();
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}
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#undef VRC6_chr
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#undef VRC6_prg16
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#undef VRC6_prg8
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#undef VRC6_misc
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