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Add mapper 468

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This commit is contained in:
NewRisingSun
2022-12-30 23:56:50 +01:00
parent 5ca702053e
commit 07284ca4af
17 changed files with 1074 additions and 0 deletions
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225
src/boards/468.c Normal file
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/* FCE Ultra - NES/Famicom Emulator
*
* Copyright notice for this file:
* Copyright (C) 2022 NewRisingSun
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* BlazePro CPLD-based multicarts
Unsolved issue: how is CHR RAM write-protection triggered?
*/
#include "mapinc.h"
#include "state.h"
static uint8 submapper;
static uint8 eeprom[16], clock, state, command, output; /* Some strange serial EEPROM */
static uint8 *WRAM;
static uint32 WRAMSIZE;
static int prevSFEXINDEX;
extern int SFEXINDEX;
extern SFORMAT SFMDATA[64];
static uint8 mapper; /* 5700 MSB >>4 OR'd with submapper <<4 */
static uint8 mapperFlags; /* 5700 LSB */
static uint8 misc; /* 5601 */
static uint8 misc2; /* 5702 */
static void (*sync)();
static uint16 prgOR;
static uint8 prgAND;
static uint8 regByte[16];
static int16 regWord[9];
#include "468_mmc1.h"
#include "468_mmc24.h"
#include "468_mmc3.h"
#include "468_vrc1.h"
#include "468_vrc24.h"
#include "468_vrc3.h"
#include "468_vrc6.h"
#include "468_vrc7.h"
#include "468_fme7.h"
#include "468_discrete.h"
#include "468_cnrom.h"
#include "468_if12.h"
#include "468_lf36.h"
#include "468_nanjing.h"
static SFORMAT stateRegs[] = {
{ &mapper, 1, "SUP0" },
{ &mapperFlags, 1, "SUP1" },
{ &misc, 1, "SUP2" },
{ &misc2, 1, "SUP3" },
{ &prgOR, 2, "SUP4" },
{ &prgAND, 1, "SUP5" },
{ eeprom, 16,"EEPR" },
{ &clock, 1, "EEP0" },
{ &state, 1, "EEP1" },
{ &command, 1, "EEP2" },
{ &output, 1, "EEP3" },
{ regByte, 16,"REGB" },
{ regWord, 16,"REGW" },
{ 0 }
};
void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */
if (select)
state =0;
else
if (!clock && newClock) {
if (state <8) {
command =command <<1 | newData*1;
if (++state ==8 && (command &0xF0) !=0x50 && (command &0xF0) !=0xA0) state =0;
} else {
int mask =1 <<(15 -state);
int address =command &0x0F;
if ((command &0xF0) ==0xA0)
eeprom[address] =eeprom[address] &~mask | newData*mask;
else
if ((command &0xF0) ==0x50)
output =!!(eeprom[address] &mask);
if (++state ==16) state =0;
}
}
clock =newClock;
}
static DECLFR(readReg);
static DECLFW(writeReg);
static void setMapper(uint8 clearRegs) {
int i;
if (clearRegs) {
for (i =0; i <16; i++) regByte[i] =0;
for (i =0; i < 8; i++) regWord[i] =0;
X6502_IRQEnd(FCEU_IQEXT);
}
SetReadHandler(0x5000, 0x5FFF, readReg);
SetReadHandler(0x6000, 0xFFFF, CartBR);
SetWriteHandler(0x5000, 0x5FFF, writeReg);
SetWriteHandler(0x6000, 0xFFFF, CartBW);
MapIRQHook = NULL;
PPU_hook = NULL;
GameHBIRQHook = NULL;
setprg8r(0x10, 0x6000, 0);
switch(mapper) { /* 5700 MSB >>4 OR'd with submapper <<4 */
case 0x00: case 0x01: case 0x32: MMC1_reset(clearRegs); break;
case 0x0A: MMC2_reset(clearRegs); break;
case 0x10: case 0x11: case 0x12: MMC3_reset(clearRegs); break;
case 0x08: MMC4_reset(clearRegs); break;
case 0x40: VRC1_reset(clearRegs); break;
case 0x20: case 0x21: case 0x22: case 0x23: VRC24_reset(clearRegs); break;
case 0x44: VRC3_reset(clearRegs); break;
case 0x30: case 0x31: VRC6_reset(clearRegs); break;
case 0x41: VRC7_reset(clearRegs); break;
case 0x07: LF36_reset(clearRegs); break;
case 0x50: FME7_reset(clearRegs); break;
case 0x0E: case 0x1E: NANJING_reset(clearRegs); break;
case 0x09: case 0x0B: case 0x17: case 0x37: UNROM_IF12_reset(clearRegs); break;
case 0x04: case 0x06: case 0x14: case 0x16: ANROM_BNROM_reset(clearRegs); break;
case 0x05: case 0x15: CNROM_BF9097_reset(clearRegs); break;
case 0x0C: case 0x0D: case 0x1C: case 0x1D: GNROM_reset(clearRegs); break;
default: break;
}
sync();
}
static DECLFR(readReg) {
switch(A) {
case 0x5301: case 0x5601:
return output? 0x80: 0x00;
default:
return 0xFF;
}
}
static DECLFW(writeReg) {
switch(A) {
case 0x5301:
if (submapper ==0) setPins(!!(V &0x04), !!(V &0x02), !!(V &0x01));
break;
case 0x5601:
if (~misc &0x80) {
misc =V;
if (submapper !=1) prgOR =prgOR &~0x2000 | V <<9 &0x2000;
sync();
}
if (submapper ==1) setPins(!!(V &0x10), !!(V &0x02), !!(V &0x01));
break;
case 0x5700:
mapper =V >>4 | submapper <<4;
mapperFlags =V &0xF;
prgOR =prgOR &~0x0010 | V <<4 &0x0010;
setMapper(1);
break;
case 0x5701:
prgOR =prgOR &~0x1FE0 | V <<5 &0x1FE0;
sync();
break;
case 0x5702:
if (submapper ==1) {
misc2 =V;
sync();
}
break;
}
}
static void reset(void) {
mapper =submapper <<4;
mapperFlags =0x0F;
misc =0;
prgOR =0x7FF0;
clock =command =output =1;
command =state =0;
setMapper(1);
}
static void power(void) {
int i;
for (i =0; i <16; i++) eeprom[i] =0;
reset();
}
static void close(void) {
if (WRAM)
FCEU_gfree(WRAM);
WRAM = NULL;
}
static void stateRestore(int version) {
setMapper(0);
}
void Mapper468_Init(CartInfo *info) {
submapper =info->submapper;
info->Reset =reset;
info->Power =power;
info->Close =close;
GameStateRestore =stateRestore;
WRAMSIZE =8192;
WRAM =(uint8*) FCEU_gmalloc(WRAMSIZE);
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
AddExState(WRAM, WRAMSIZE, 0, "WRAM");
AddExState(stateRegs, ~0, 0, 0);
prevSFEXINDEX =SFEXINDEX;
}

45
src/boards/468_cnrom.h Normal file
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#define CNROM_reg regByte
static void CNROM_sync () {
int OR =prgOR >>1;
if (mapperFlags &2) {
setprg16(0x8000, CNROM_reg[2] <<1 &0xE | mapperFlags &1 | OR &~0xF);
setprg16(0xC000, CNROM_reg[2] <<1 &0xE | mapperFlags &1 | OR &~0xF);
setchr8(CNROM_reg[0] &0x03);
} else {
OR >>=1;
setprg32(0x8000, CNROM_reg[2] &0x7 | OR &~0x7);
setchr8(CNROM_reg[0] &0x0F);
}
if (mapperFlags &8)
setmirror(mapperFlags &0x04? MI_H: MI_V);
else
setmirror(CNROM_reg[1] &0x10? MI_1: MI_0);
}
static DECLFW(CNROM_writeReg) {
switch(A &0xE000) {
case 0x8000: case 0xA000:
CNROM_reg[0] =V;
break;
case 0xE000:
CNROM_reg[2] =V;
break;
}
sync();
}
static DECLFW(BF9097_writeMirroring) {
CNROM_reg[1] =V;
sync();
}
void CNROM_BF9097_reset(uint8 clearRegs) { /* This strange mapper is used for both (C)NROM games and FireHawk. What an absurd combination!*/
sync =CNROM_sync;
SetWriteHandler(0x8000, 0xFFFF, CNROM_writeReg);
if (~mapperFlags &8)
SetWriteHandler(0x9000, 0x9FFF, BF9097_writeMirroring);
sync();
}
#undef CNROM_reg

74
src/boards/468_discrete.h Normal file
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#define latch regByte[0]
static void ANROM_sync () {
int AND =prgAND >>2;
int OR =prgOR >>2;
setprg32(0x8000, latch &AND | OR &~AND);
setchr8(0);
setmirror(latch &0x10? MI_1: MI_0);
}
static void BNROM_sync () {
int AND =prgAND >>2;
int OR =prgOR >>2;
setprg32(0x8000, latch &AND | OR &~AND);
setchr8(0);
setmirror(mapperFlags &4? MI_H: MI_V);
}
static void GNROM_sync () {
int AND =prgAND >>2;
int OR =prgOR >>2 | (mapperFlags &4? 2: 0);
setprg32(0x8000, latch >>4 &AND | OR &~AND);
setchr8(latch &0x0F);
setmirror(mapper &1? MI_H: MI_V);
}
static void UNROM_sync () {
int AND =prgAND >>1;
int OR =prgOR >>1;
setprg16(0x8000, latch &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
setchr8(0);
setmirror(mapperFlags &4? MI_H: MI_V);
}
static DECLFW(DISCRETE_writeLatch) {
if (mapper ==0x09 && mapperFlags ==0xE && A ==0xA000 && V ==0x00)
V =0x06; // UNROM: Strange hack, needed to get #282 "Portopia Serial Murder Case" on 852-in-1 running
latch =V;
sync();
}
static DECLFW(GNROM_writeLatch) {
if (~prgOR &0x2000 || mapper ==0x1C || mapper==0x1D)
V =V >>4 &0xF | V <<4 &0xF0; // Color Dreams: swap nibbles to mimic GNROM
latch =V;
sync();
}
void ANROM_BNROM_reset(uint8 clearRegs) {
sync =mapperFlags &8? BNROM_sync: ANROM_sync;
prgAND =(mapper ==0x06 || mapper ==0x16)? 0x3F: mapperFlags &2? 0x0F: 0x1F;
SetWriteHandler(0x8000, 0xFFFF, DISCRETE_writeLatch);
latch =0;
sync();
}
void GNROM_reset(uint8 clearRegs) {
sync =GNROM_sync;
prgAND =mapperFlags &8? 0x07: 0x0F;
SetWriteHandler(0x8000, 0xFFFF, GNROM_writeLatch);
latch =0;
sync();
}
void UNROM_reset(uint8 clearRegs) {
sync =UNROM_sync;
prgAND =mapper ==0x0B || mapper ==0x17 &&~mapperFlags &8? 0x3F: mapperFlags &2? 0x0F: 0x1F;
SetWriteHandler(0x8000, 0xFFFF, DISCRETE_writeLatch);
sync();
}
#undef latch

72
src/boards/468_fme7.h Normal file
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#define FME7_reg regByte
#define FME7_index regByte[15]
#define FME7_counter regWord[0]
static void FME7_sync() {
int AND =mapperFlags &8? 0xFF: 0x7F;
switch(FME7_reg[8] &0xC0) {
case 0x00: case 0x80:
setprg8(0x6000, FME7_reg[0x8] &prgAND | prgOR &~prgAND);
break;
case 0x40:
/* Open Bus */
break;
case 0xC0:
setprg8r(0x10, 0x6000, 0);
break;
}
setprg8(0x8000, FME7_reg[0x9] &prgAND | prgOR &~prgAND);
setprg8(0xA000, FME7_reg[0xA] &prgAND | prgOR &~prgAND);
setprg8(0xC000, FME7_reg[0xB] &prgAND | prgOR &~prgAND);
setprg8(0xE000, prgAND | prgOR &~prgAND);
setchr1(0x0000, FME7_reg[0x0] &AND);
setchr1(0x0400, FME7_reg[0x1] &AND);
setchr1(0x0800, FME7_reg[0x2] &AND);
setchr1(0x0C00, FME7_reg[0x3] &AND);
setchr1(0x1000, FME7_reg[0x4] &AND);
setchr1(0x1400, FME7_reg[0x5] &AND);
setchr1(0x1800, FME7_reg[0x6] &AND);
setchr1(0x1C00, FME7_reg[0x7] &AND);
setmirror(FME7_reg[0xC] &3 ^(FME7_reg[0xC] &2? 0: 1));
}
static DECLFW(FME7_writeIndex) {
FME7_index =V &0xF;
}
static DECLFW(FME7_writeReg) {
switch(FME7_index) {
case 0xE:
FME7_counter =FME7_counter &0xFF00 |V;
break;
case 0xF:
FME7_counter =FME7_counter &0x00FF |V <<8;
break;
case 0xD:
X6502_IRQEnd(FCEU_IQEXT);
/* Falling through */
default:
FME7_reg[FME7_index] =V;
sync();
}
}
static void FP_FASTAPASS(1) FME7_cpuCycle(int a) {
while (a--) {
if (FME7_reg[0xD] &0x80 && !--FME7_counter && FME7_reg[0xD] &0x01) X6502_IRQBegin(FCEU_IQEXT);
}
}
void FME7_reset(uint8 clearRegs) {
sync =FME7_sync;
prgAND =mapperFlags &2? 0x0F: 0x1F;
MapIRQHook =FME7_cpuCycle;
SetWriteHandler(0x8000, 0x9FFF, FME7_writeIndex);
SetWriteHandler(0xA000, 0xBFFF, FME7_writeReg);
sync();
}
#undef FME7_reg
#undef FME7_index
#undef FME7_counter

31
src/boards/468_if12.h Normal file
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#define IF12_reg regByte
static void IF12_sync () {
int AND =prgAND >>1;
int OR =prgOR >>1;
setprg16(0x8000, IF12_reg[1] &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
setchr8(IF12_reg[0] >>1 &0xF);
setmirror(IF12_reg[0] &1? MI_H: MI_V);
}
static DECLFW(IF12_writeReg) {
IF12_reg[A >>14 &1] =V;
sync();
}
void IF12_reset(uint8 clearRegs) {
sync =IF12_sync;
prgAND =mapperFlags &2? 0x0F: 0x1F;
SetWriteHandler(0x8000, 0xFFFF, IF12_writeReg);
sync();
}
void UNROM_IF12_reset(uint8 clearRegs) {
if (mapperFlags &8)
UNROM_reset(clearRegs);
else
IF12_reset(clearRegs);
}
#undef IF12_reg

46
src/boards/468_lf36.h Normal file
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#define LF36_prg regByte[0]
#define LF36_irq regByte[1]
#define LF36_counter regWord[0]
static void LF36_sync () {
int OR =prgOR | mapperFlags &0x08;
setprg8(0x8000, 0x04 | OR);
setprg8(0xA000, 0x05 | OR);
setprg8(0xC000, LF36_prg &0x07 | OR);
setprg8(0xE000, 0x07 | OR);
setchr8(0);
setmirror(mapperFlags &4? MI_H: MI_V);
}
static DECLFW(LF36_writeReg) {
switch (A &0xE000) {
case 0x8000: LF36_irq =0; break;
case 0xA000: LF36_irq =1; break;
case 0XE000: LF36_prg =V; sync(); break;
}
}
static void FP_FASTAPASS(1) LF36_cpuCycle(int a) {
while (a--) {
if (LF36_irq) {
if (++LF36_counter &0x1000)
X6502_IRQBegin(FCEU_IQEXT);
else
X6502_IRQEnd(FCEU_IQEXT);
} else {
X6502_IRQEnd(FCEU_IQEXT);
LF36_counter =0;
}
}
}
void LF36_reset(uint8 clearRegs) {
sync =LF36_sync;
MapIRQHook =LF36_cpuCycle;
SetWriteHandler(0x8000, 0xFFFF, LF36_writeReg);
sync();
}
#undef LF36_prg
#undef LF36_irq
#undef LF36_counter

70
src/boards/468_mmc1.h Normal file
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#define MMC1_reg regByte
#define MMC1_shift regByte[4]
#define MMC1_count regByte[5]
#define MMC1_filter regByte[6]
static void MMC1_sync () {
int AND =prgAND >>1;
int OR =prgOR >>1 | (mapper &0x01? (MMC1_reg[1] &0x10): (mapperFlags &0x06));
if (MMC1_reg[0] &0x8) { /* 16 KiB mode */
if (MMC1_reg[0] &0x04) { /* OR logic */
setprg16(0x8000, MMC1_reg[3] &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
} else { /* AND logic */
setprg16(0x8000, 0x00 &AND | OR &~AND);
setprg16(0xC000, MMC1_reg[3] &AND | OR &~AND);
}
} else
setprg32(0x8000, (MMC1_reg[3] &AND | OR &~AND) >>1);
AND =mapper &0x01? 0x0F: 0x1F;
if (MMC1_reg[0] &0x10) { /* 4 KiB mode */
setchr4(0x0000, MMC1_reg[1] &AND);
setchr4(0x1000, MMC1_reg[2] &AND);
} else /* 8 KiB mode */
setchr8(MMC1_reg[1] >>1 &(AND >>1));
switch(MMC1_reg[0] &3) {
case 0: setmirror(MI_0); break;
case 1: setmirror(MI_1); break;
case 2: setmirror(MI_V); break;
case 3: setmirror(MI_H); break;
}
}
static DECLFW(MMC1_writeReg) {
if (V &0x80) {
MMC1_shift =MMC1_count =0;
MMC1_reg[0] |=0x0C;
sync();
} else
if (!MMC1_filter) {
MMC1_shift |=(V &1) <<MMC1_count++;
if (MMC1_count ==5) {
MMC1_reg[A >>13 &3] =MMC1_shift;
MMC1_count =0;
MMC1_shift =0;
sync();
}
}
MMC1_filter =2;
}
static void FP_FASTAPASS(1) MMC1_cpuCycle(int a) {
while (a--) if (MMC1_filter) MMC1_filter--;
}
void MMC1_reset(uint8 clearRegs) {
sync =MMC1_sync;
MapIRQHook =MMC1_cpuCycle;
prgAND =mapperFlags &2? (mapperFlags &8? 0x07: 0x0F): 0x1F;
SetWriteHandler(0x8000, 0xFFFF, MMC1_writeReg);
if (clearRegs) MMC1_reg[0] =0x0C;
sync();
}
#undef MMC1_reg
#undef MMC1_shift
#undef MMC1_count
#undef MMC1_filter

67
src/boards/468_mmc24.h Normal file
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#define MMC24_reg regByte
static void MMC2_sync() {
setprg8(0x8000, MMC24_reg[0] &prgAND | prgOR &~prgAND);
setprg8(0xA000, 0xFD &prgAND | prgOR &~prgAND);
setprg8(0xC000, 0xFE &prgAND | prgOR &~prgAND);
setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
setchr4(0x0000, MMC24_reg[1 +MMC24_reg[6]]);
setchr4(0x1000, MMC24_reg[3 +MMC24_reg[7]]);
setmirror(MMC24_reg[5] &1? MI_H: MI_V);
}
static void MMC4_sync() {
int AND =prgAND >>1;
int OR =prgOR >>1;
setprg16(0x8000, MMC24_reg[0] &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
setchr4(0x0000, MMC24_reg[1 +MMC24_reg[6]]);
setchr4(0x1000, MMC24_reg[3 +MMC24_reg[7]]);
setmirror(MMC24_reg[5] &1? MI_H: MI_V);
}
static DECLFW(MMC24_writeReg) {
MMC24_reg[(A >>12) -0xA] =V;
sync();
}
static void FP_FASTAPASS(1) MMC24_ppuHook(uint32 A) {
uint8 l, h = A >> 8;
if (h >= 0x20 || ((h & 0xF) != 0xF)) return;
l = A & 0xF0;
if (h < 0x10) {
if (l == 0xD0) {
MMC24_reg[6] =0;
sync();
} else if (l == 0xE0) {
MMC24_reg[6] =1;
sync();
}
} else {
if (l == 0xD0) {
MMC24_reg[7] =0;
sync();
} else if (l == 0xE0) {
MMC24_reg[7] =1;
sync();
}
}
}
void MMC2_reset(uint8 clearRegs) {
sync =MMC2_sync;
prgAND =0x0F;
PPU_hook =MMC24_ppuHook;
SetWriteHandler(0xA000, 0xFFFF, MMC24_writeReg);
sync();
}
void MMC4_reset(uint8 clearRegs) {
sync =MMC4_sync;
prgAND =mapperFlags &2? 0x0F: 0x1F;
PPU_hook =MMC24_ppuHook;
SetWriteHandler(0xA000, 0xFFFF, MMC24_writeReg);
sync();
}
#undef MMC24_reg

79
src/boards/468_mmc3.h Normal file
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#define MMC3_reg regByte
#define MMC3_index regByte[8]
#define MMC3_mirroring regByte[9]
#define MMC3_wram regByte[10]
#define MMC3_reload regByte[11]
#define MMC3_count regByte[12]
#define MMC3_irq regByte[13]
#define MMC3_lastReg regByte[14]
static void MMC3_sync () {
int chrAND =mapper &0x01? 0xFF: 0x7F;
int OR =prgOR | (misc2 &1? 12: 0);
setprg8(0x8000 ^(MMC3_index <<8 &0x4000), MMC3_reg[6] &prgAND | prgOR &~prgAND);
setprg8(0xA000, MMC3_reg[7] &prgAND | prgOR &~prgAND);
setprg8(0xC000 ^(MMC3_index <<8 &0x4000), 0xFE &prgAND | prgOR &~prgAND);
setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
setchr1(0x0000 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] &0xFE)&chrAND);
setchr1(0x0400 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] |0x01)&chrAND);
setchr1(0x0800 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] &0xFE)&chrAND);
setchr1(0x0C00 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] |0x01)&chrAND);
setchr1(0x1000 ^(MMC3_index <<5 &0x1000), MMC3_reg[2] &chrAND);
setchr1(0x1400 ^(MMC3_index <<5 &0x1000), MMC3_reg[3] &chrAND);
setchr1(0x1800 ^(MMC3_index <<5 &0x1000), MMC3_reg[4] &chrAND);
setchr1(0x1C00 ^(MMC3_index <<5 &0x1000), MMC3_reg[5] &chrAND);
if (mapper &2) switch(MMC3_mirroring &3) {
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MMC3_reg[MMC3_lastReg] &0x80? MI_1: MI_0); break;
case 3: setmirror(MI_1); break;
} else
setmirror(MMC3_mirroring &1 ^1);
}
static DECLFW(MMC3_writeReg) {
switch(A &0xE001) {
case 0x8000: MMC3_index =V; sync(); break;
case 0x8001: MMC3_reg[MMC3_index &7] =V; sync(); break;
case 0xA000: MMC3_mirroring =V; sync(); break;
case 0xA001: MMC3_wram =V; sync(); break;
case 0xC000: MMC3_reload =V; break;
case 0xC001: MMC3_count =0; break;
case 0xE000: MMC3_irq =0; X6502_IRQEnd(FCEU_IQEXT); break;
case 0xE001: MMC3_irq =1; break;
}
}
static void MMC3_horizontalBlanking(void) {
MMC3_count =!MMC3_count? MMC3_reload: --MMC3_count;
if (!MMC3_count && MMC3_irq) X6502_IRQBegin(FCEU_IQEXT);
}
static void FP_FASTAPASS(1) MMC3_ppuHook(uint32 A) {
A &=0x1FFF;
if (MMC3_index &0x80) A ^=0x1000;
if (A <0x1000)
MMC3_lastReg =A >>11;
else
MMC3_lastReg =(A >>10) -2;
if ((MMC3_mirroring &3) ==2) setmirror(MMC3_reg[MMC3_lastReg] &0x80? MI_1: MI_0);
}
void MMC3_reset(uint8 clearRegs) {
sync =MMC3_sync;
GameHBIRQHook =MMC3_horizontalBlanking;
if (mapper &2) PPU_hook =MMC3_ppuHook;
prgAND =mapperFlags &8? (mapperFlags &4? (mapperFlags &2? (misc2 &2? 0x07: 0x0F): 0x1F): 0x3F): 0x7F;
SetWriteHandler(0x8000, 0xFFFF, MMC3_writeReg);
sync();
}
#undef MMC3_reg
#undef MMC3_index
#undef MMC3_mirroring
#undef MMC3_wram
#undef MMC3_reload
#undef MMC3_count
#undef MMC3_irq
#undef MMC3_lastReg

29
src/boards/468_nanjing.h Normal file
View File

@@ -0,0 +1,29 @@
#define NANJING_reg regByte
static void NANJING_sync () {
setprg32(0x8000, NANJING_reg[2] <<4 &0x30 | NANJING_reg[0] &0x0F | (NANJING_reg[3] &4? 0x00: 0x03) | prgOR >>2);
setchr8(0);
setmirror(mapperFlags &4? MI_H: MI_V);
}
static DECLFW(NANJING_writeReg) {
NANJING_reg[A >>8 &3] =V;
sync();
}
static void NANJING_horizontalBlanking(void) {
if (NANJING_reg[0] &0x80 && scanline <239) { /* Actual hardware cannot look at the current scanline number, but instead latches PA09 on PA13 rises. This does not seem possible with the current PPU emulation however. */
setchr4(0x0000, scanline >=127? 1: 0);
setchr4(0x1000, scanline >=127? 1: 0);
} else
setchr8(0);
}
void NANJING_reset(uint8 clearRegs) {
sync =NANJING_sync;
GameHBIRQHook = NANJING_horizontalBlanking;
SetWriteHandler(0x5000, 0x53FF, NANJING_writeReg);
sync();
}
#undef NANJING_reg

25
src/boards/468_vrc1.h Normal file
View File

@@ -0,0 +1,25 @@
#define VRC1_reg regByte
static void VRC1_sync () {
setprg8(0x8000, VRC1_reg[0] &prgAND | prgOR &~prgAND);
setprg8(0xA000, VRC1_reg[2] &prgAND | prgOR &~prgAND);
setprg8(0xC000, VRC1_reg[4] &prgAND | prgOR &~prgAND);
setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
setchr4(0x0000, VRC1_reg[6] &0x0F | VRC1_reg[1] <<3 &0x10);
setchr4(0x1000, VRC1_reg[7] &0x0F | VRC1_reg[1] <<2 &0x10);
setmirror(VRC1_reg[1] &1? MI_H: MI_V);
}
static DECLFW(VRC1_writeReg) {
VRC1_reg[A >>12 &7] =V;
sync();
}
void VRC1_reset(uint8 clearRegs) {
sync =VRC1_sync;
prgAND =mapperFlags &8? (mapperFlags &4? (mapperFlags &2? 0x0F: 0x1F): 0x3F): 0x7F;
SetWriteHandler(0x8000, 0xFFFF, VRC1_writeReg);
sync();
}
#undef VRC1_reg

92
src/boards/468_vrc24.h Normal file
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@@ -0,0 +1,92 @@
#define VRC24_prg regByte
#define VRC24_mirroring regByte[2]
#define VRC24_misc regByte[3]
#define VRC24_chr regWord
#define VRCIRQ_latch regByte[13]
#define VRCIRQ_mode regByte[14]
#define VRCIRQ_count regByte[15]
#define VRCIRQ_cycles regWord[8]
static void VRC24_sync() {
setprg8(0x8000 ^(VRC24_misc <<13 &0x4000), VRC24_prg[0] &prgAND | prgOR &~prgAND);
setprg8(0xA000, VRC24_prg[1] &prgAND | prgOR &~prgAND);
setprg8(0xC000 ^(VRC24_misc <<13 &0x4000), 0xFE &prgAND | prgOR &~prgAND);
setprg8(0xE000, 0xFF &prgAND | prgOR &~prgAND);
setchr1(0x0000, VRC24_chr[0]);
setchr1(0x0400, VRC24_chr[1]);
setchr1(0x0800, VRC24_chr[2]);
setchr1(0x0C00, VRC24_chr[3]);
setchr1(0x1000, VRC24_chr[4]);
setchr1(0x1400, VRC24_chr[5]);
setchr1(0x1800, VRC24_chr[6]);
setchr1(0x1C00, VRC24_chr[7]);
setmirror(VRC24_mirroring &3 ^(VRC24_mirroring &2? 0: 1));
}
static DECLFW(VRC24_writeReg) {
uint8 index;
A =A &0xF000 | (mapper &2? ((A &0xA? 1: 0) | (A &0x5? 2: 0)): ((A &0x5? 1: 0) | (A &0xA? 2: 0)));
switch (A &0xF000) {
case 0x8000: case 0xA000:
VRC24_prg[A >>13 &1] =V;
sync();
break;
case 0x9000:
if (~A &2)
VRC24_mirroring =V & (mapper &1? 3: 1);
else
if (~A &1 && mapper &1)
VRC24_misc =V;
sync();
break;
case 0xF000:
if (mapper &1) switch (A &3) {
case 0: VRCIRQ_latch =VRCIRQ_latch &0xF0 | V &0x0F; break;
case 1: VRCIRQ_latch =VRCIRQ_latch &0x0F | V <<4; break;
case 2: VRCIRQ_mode =V;
if (VRCIRQ_mode &0x02) {
VRCIRQ_count =VRCIRQ_latch;
VRCIRQ_cycles =341;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 3: VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
X6502_IRQEnd(FCEU_IQEXT);
break;
}
break;
default:
index =(A -0xB000) >>11 | A >>1 &1;
if (A &1)
VRC24_chr[index] =VRC24_chr[index] & 0x0F | V <<4;
else
VRC24_chr[index] =VRC24_chr[index] &~0x0F | V &0x0F;
sync();
break;
}
}
static void FP_FASTAPASS(1) VRCIRQ_cpuCycle(int a) {
while (a--) {
if (VRCIRQ_mode &0x02 && (VRCIRQ_mode &0x04 || (VRCIRQ_cycles -=3) <=0)) {
if (~VRCIRQ_mode &0x04) VRCIRQ_cycles +=341;
if (!++VRCIRQ_count) {
VRCIRQ_count =VRCIRQ_latch;
X6502_IRQBegin(FCEU_IQEXT);
}
}
}
}
void VRC24_reset(uint8 clearRegs) {
sync =VRC24_sync;
prgAND =mapperFlags &2? 0x0F: 0x1F;
if (mapper &1) MapIRQHook =VRCIRQ_cpuCycle;
SetWriteHandler(0x8000, 0xFFFF, VRC24_writeReg);
sync();
}
#undef VRC24_prg
#undef VRC24_mirroring
#undef VRC24_misc
#undef VRC24_chr

63
src/boards/468_vrc3.h Normal file
View File

@@ -0,0 +1,63 @@
#define VRC3_prg regByte[0]
#define VRC3_latch regWord[0]
#define VRC3_mode regByte[1]
#define VRC3_count regWord[1]
static void VRC3_sync() {
int AND =prgAND >>1;
int OR =prgOR >>1;
setprg16(0x8000, VRC3_prg &AND | OR &~AND);
setprg16(0xC000, AND | OR &~AND);
setchr8(0);
setmirror(mapperFlags &4? MI_H: MI_V);
}
static DECLFW(VRC3_writeReg) {
int shift;
switch(A &0xF000) {
case 0x8000: case 0x9000: case 0xA000: case 0xB000:
V &=0xF;
shift =A >>10 &0xC;
VRC3_latch =VRC3_latch &~(0xF <<shift) | V <<shift;
break;
case 0xC000:
VRC3_mode =V;
if (VRC3_mode &0x02) VRC3_count =VRC3_latch;
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xD000:
VRC3_mode =VRC3_mode &~0x02 | VRC3_mode <<1 &0x02;
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xF000:
VRC3_prg =V;
sync();
break;
}
}
static void FP_FASTAPASS(1) VRC3_cpuCycle(int a) {
while (a--) {
int mask =VRC3_mode &0x04? 0xFF: 0xFFFF;
if (VRC3_mode &0x02) {
if ((VRC3_count &mask) ==mask) {
VRC3_count =VRC3_latch;
X6502_IRQBegin(FCEU_IQEXT);
} else
++VRC3_count;
}
}
}
void VRC3_reset(uint8 clearRegs) {
sync =VRC3_sync;
prgAND =0x0F;
MapIRQHook =VRC3_cpuCycle;
SetWriteHandler(0x8000, 0xFFFF, VRC3_writeReg);
sync();
}
#undef VRC3_prg
#undef VRC3_latch
#undef VRC3_mode
#undef VRC3_count

72
src/boards/468_vrc6.h Normal file
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@@ -0,0 +1,72 @@
#define VRC6_chr regByte
#define VRC6_prg16 regByte[8]
#define VRC6_prg8 regByte[9]
#define VRC6_misc regByte[10]
static void VRC6_sync() {
int AND =prgAND >>1;
int OR =prgOR >>1;
setprg16(0x8000, VRC6_prg16 & AND | OR & ~AND);
setprg8(0xC000, VRC6_prg8 &prgAND | prgOR &~prgAND);
setprg8(0xE000, prgAND | prgOR &~prgAND);
setchr1(0x0000, VRC6_chr[0]);
setchr1(0x0400, VRC6_chr[1]);
setchr1(0x0800, VRC6_chr[2]);
setchr1(0x0C00, VRC6_chr[3]);
setchr1(0x1000, VRC6_chr[4]);
setchr1(0x1400, VRC6_chr[5]);
setchr1(0x1800, VRC6_chr[6]);
setchr1(0x1C00, VRC6_chr[7]);
setmirror((VRC6_misc &0xC ^(VRC6_misc &0x8? 0: 0x4)) >>2);
}
static DECLFW(VRC6_writeReg) {
uint8 index;
switch (A &0xF003) {
case 0x8000: case 0x8001: case 0x8002: case 0x8003:
VRC6_prg16 =V;
sync();
break;
case 0xB003:
VRC6_misc =V;
sync();
break;
case 0xC000: case 0xC001: case 0xC002: case 0xC003:
VRC6_prg8 =V;
sync();
break;
case 0xD000: case 0xD001: case 0xD002: case 0xD003: case 0xE000: case 0xE001: case 0xE002: case 0xE003:
index =(A -0xD000) >>10 | A &3;
VRC6_chr[index] =V;
sync();
break;
case 0xF000:
VRCIRQ_latch =V;
break;
case 0xF001:
VRCIRQ_mode =V;
if (VRCIRQ_mode &0x02) {
VRCIRQ_count =VRCIRQ_latch;
VRCIRQ_cycles =341;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xF002:
VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
X6502_IRQEnd(FCEU_IQEXT);
break;
}
}
void VRC6_reset(uint8 clearRegs) {
sync =VRC6_sync;
prgAND =mapperFlags &2? 0x0F: 0x1F;
MapIRQHook =VRCIRQ_cpuCycle;
SetWriteHandler(0x8000, 0xFFFF, VRC6_writeReg);
sync();
}
#undef VRC6_chr
#undef VRC6_prg16
#undef VRC6_prg8
#undef VRC6_misc

82
src/boards/468_vrc7.h Normal file
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@@ -0,0 +1,82 @@
#define VRC7_chr regByte
#define VRC7_prg0 regByte[8]
#define VRC7_prg1 regByte[9]
#define VRC7_prg2 regByte[10]
#define VRC7_misc regByte[11]
static void VRC7_sync() {
setprg8(0x8000, VRC7_prg0 &prgAND | prgOR &~prgAND);
setprg8(0xA000, VRC7_prg1 &prgAND | prgOR &~prgAND);
setprg8(0xC000, VRC7_prg2 &prgAND | prgOR &~prgAND);
setprg8(0xE000, prgAND | prgOR &~prgAND);
setchr1(0x0000, VRC7_chr[0]);
setchr1(0x0400, VRC7_chr[1]);
setchr1(0x0800, VRC7_chr[2]);
setchr1(0x0C00, VRC7_chr[3]);
setchr1(0x1000, VRC7_chr[4]);
setchr1(0x1400, VRC7_chr[5]);
setchr1(0x1800, VRC7_chr[6]);
setchr1(0x1C00, VRC7_chr[7]);
setmirror(VRC7_misc &3 ^(VRC7_misc &2? 0: 1));
}
static DECLFW(VRC7_writeReg) {
uint8 index;
A =A &0xF000 | (A &0x18? 1: 0) | (A &0x20? 2: 0);
switch (A &0xF003) {
case 0x8000:
VRC7_prg0 =V;
sync();
break;
case 0x8001:
VRC7_prg1 =V;
sync();
break;
case 0x9000:
VRC7_prg2 =V;
sync();
break;
case 0x9001: case 0x9002:
/* sound */
break;
case 0xA000: case 0xA001: case 0xB000: case 0xB001: case 0xC000: case 0xC001: case 0xD000: case 0xD001:
index =(A -0xA000) >>11 | A &1;
VRC7_chr[index] =V;
sync();
break;
case 0xE000:
VRC7_misc =V;
sync();
break;
case 0xE001:
VRCIRQ_latch =V;
break;
case 0xF000:
VRCIRQ_mode =V;
if (VRCIRQ_mode &0x02) {
VRCIRQ_count =VRCIRQ_latch;
VRCIRQ_cycles =341;
}
X6502_IRQEnd(FCEU_IQEXT);
break;
case 0xF001:
VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
X6502_IRQEnd(FCEU_IQEXT);
break;
}
}
void VRC7_reset(uint8 clearRegs) {
sync =VRC7_sync;
prgAND =mapperFlags &8? (mapperFlags &4? (mapperFlags &2? 0x0F: 0x1F): 0x3F): 0x7F;
MapIRQHook =VRCIRQ_cpuCycle;
SetWriteHandler(0x8000, 0xFFFF, VRC7_writeReg);
sync();
}
#undef VRC7_chr
#undef VRC7_prg0
#undef VRC7_prg1
#undef VRC7_prg2
#undef VRC7_misc

1
src/ines.c
View File

@@ -831,6 +831,7 @@ INES_BOARD_BEGIN()
INES_BOARD( "ET-120", 465, Mapper465_Init )
INES_BOARD( "Keybyte Computer", 466, Mapper466_Init )
INES_BOARD( "47-2", 467, Mapper467_Init )
INES_BOARD( "BlazePro CPLD", 468, Mapper468_Init )
INES_BOARD( "SA-9602B", 513, SA9602B_Init )
INES_BOARD( "Brilliant Com Cocoma Pack", 516, Mapper516_Init )
INES_BOARD( "DANCE2000", 518, UNLD2000_Init )

1
src/ines.h
View File

@@ -339,6 +339,7 @@ void Mapper464_Init(CartInfo *);
void Mapper465_Init(CartInfo *);
void Mapper466_Init(CartInfo *);
void Mapper467_Init(CartInfo *);
void Mapper468_Init(CartInfo *);
void Mapper516_Init(CartInfo *);
void Mapper523_Init(CartInfo *);
void Mapper533_Init(CartInfo *);