64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
#define VRC3_prg regByte[0]
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#define VRC3_latch regWord[0]
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#define VRC3_mode regByte[1]
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#define VRC3_count regWord[1]
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static void VRC3_sync() {
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int AND =prgAND >>1;
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int OR =prgOR >>1;
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setprg16(0x8000, VRC3_prg &AND | OR &~AND);
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setprg16(0xC000, AND | OR &~AND);
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setchr8(0);
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setmirror(mapperFlags &4? MI_H: MI_V);
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}
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static DECLFW(VRC3_writeReg) {
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int shift;
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switch(A &0xF000) {
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case 0x8000: case 0x9000: case 0xA000: case 0xB000:
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V &=0xF;
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shift =A >>10 &0xC;
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VRC3_latch =VRC3_latch &~(0xF <<shift) | V <<shift;
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break;
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case 0xC000:
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VRC3_mode =V;
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if (VRC3_mode &0x02) VRC3_count =VRC3_latch;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xD000:
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VRC3_mode =VRC3_mode &~0x02 | VRC3_mode <<1 &0x02;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xF000:
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VRC3_prg =V;
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sync();
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break;
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}
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}
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static void FP_FASTAPASS(1) VRC3_cpuCycle(int a) {
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while (a--) {
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int mask =VRC3_mode &0x04? 0xFF: 0xFFFF;
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if (VRC3_mode &0x02) {
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if ((VRC3_count &mask) ==mask) {
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VRC3_count =VRC3_latch;
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X6502_IRQBegin(FCEU_IQEXT);
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} else
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++VRC3_count;
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}
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}
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}
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void VRC3_reset(uint8 clearRegs) {
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sync =VRC3_sync;
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prgAND =0x0F;
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MapIRQHook =VRC3_cpuCycle;
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SetWriteHandler(0x8000, 0xFFFF, VRC3_writeReg);
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sync();
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}
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#undef VRC3_prg
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#undef VRC3_latch
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#undef VRC3_mode
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#undef VRC3_count
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