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m369: Update and reworked

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This commit is contained in:
negativeExponent
2020-03-07 09:37:58 +08:00
parent 6af7c82742
commit edea0a8899
1 changed files with 115 additions and 71 deletions
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186
src/boards/369.c
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@@ -23,131 +23,175 @@
#include "mapinc.h" #include "mapinc.h"
#include "mmc3.h" #include "mmc3.h"
static uint8 M40IRQa; static uint8 mode;
static uint16 M40IRQCount; static uint8 mmc3_count, mmc3_latch, mmc3_enabled, mmc3_reload;
static uint8 smb2_reg;
static uint8 smb2j_enabled;
static uint16 smb2j_count;
static void M369PW(uint32 A, uint8 V) { static uint32 WRAMSIZE;
switch (EXPREGS[0]) { static uint8 *WRAM;
static SFORMAT StateRegs[] = {
{ &mode, 1, "MODE" },
{ &mmc3_reload, 1, "IRQR" },
{ &mmc3_count, 1, "IRQC" },
{ &mmc3_latch, 1, "IRQL" },
{ &mmc3_enabled, 1, "IRQA" },
{ &smb2_reg, 1, "MBRG" },
{ &smb2j_enabled, 1, "MIRQ" },
{ &smb2j_count, 2 | FCEUSTATE_RLSB, "MIQC" },
{ 0 }
};
static void SyncPRG(uint32 A, uint8 V) {
switch (mode) {
case 0x00: case 0x00:
setprg32(0x8000, 0); case 0x01: /* NROM */
setprg32(0x8000, mode & 0x01);
break; break;
case 0x01: case 0x13: /* Mapper 40 */
setprg32(0x8000, 1); setprg8r(0, 0x6000, 0x0E);
break;
case 0x13:
setprg8(0x6000, 0x0E);
setprg8(0x8000, 0x0C); setprg8(0x8000, 0x0C);
setprg8(0xa000, 0x0D); setprg8(0xa000, 0x0D);
setprg8(0xc000, EXPREGS[1] | 0x08); setprg8(0xc000, smb2_reg | 0x08);
setprg8(0xe000, 0x0F); setprg8(0xe000, 0x0F);
break; break;
case 0x37: case 0x37: /* MMC3 128 PRG */
setprg8r(0x10, 0x6000, 0); setprg8r(0x10, 0x6000, 0);
setprg8(A, (V & 0x0F) | 0x10); setprg8(A, (V & 0x0F) | 0x10);
break; break;
case 0xFF: case 0xFF: /* MMC3 256 PRG */
setprg8r(0x10, 0x6000, 0); setprg8r(0x10, 0x6000, 0);
setprg8(A, (V & 0x1F) | 0x20); setprg8(A, (V & 0x1F) | 0x20);
break; break;
} }
} }
static void M369CW(uint32 A, uint8 V) { static void SyncCHR(uint32 A, uint8 V) {
switch (EXPREGS[0]) { switch (mode) {
case 0x00: case 0x00:
setchr8(0); case 0x01: /* NROM */
case 0x13: /* Mapper 40 */
setchr8(mode & 0x03);
break; break;
case 0x01: case 0x37: /* MMC3 128 CHR */
setchr8(1);
break;
case 0x13:
setprg8(0xE000, 0xF);
setchr8(3);
break;
case 0x37:
setchr1(A, (V & 0x7F) | 0x80); setchr1(A, (V & 0x7F) | 0x80);
break; break;
case 0xFF: case 0xFF: /* MMC3 256 CHR */
setchr1(A, V | 0x100); setchr1(A, (V & 0xFF) | 0x100);
break; break;
} }
} }
static DECLFW(M369WriteCMD) { static DECLFW(M369WriteLo) {
EXPREGS[0] = V; if ((A & 0xC100) == 0x4100) {
FixMMC3PRG(MMC3_cmd); mode = V;
FixMMC3CHR(MMC3_cmd); FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
}
} }
static DECLFW(M369Write) { static DECLFW(M369Write) {
if (EXPREGS[0] == 0x13) { if (mode == 0x13) {
switch (A & 0xE000) { switch (A & 0xE000) {
case 0x8000: case 0x8000:
M40IRQa = 0; smb2j_enabled = 0;
M40IRQCount = 0; smb2j_count = 0;
X6502_IRQEnd(FCEU_IQEXT); X6502_IRQEnd(FCEU_IQEXT);
break; break;
case 0xA000: case 0xA000:
M40IRQa = 1; smb2j_enabled = 1;
break; break;
case 0xE000: case 0xE000:
EXPREGS[1] = V & 7; smb2_reg = V & 7;
FixMMC3PRG(MMC3_cmd); FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd); FixMMC3CHR(MMC3_cmd);
break; break;
} }
} else { } else {
if (A < 0xC000) { switch (A & 0xE001) {
case 0x8000:
case 0x8001:
case 0xA000:
case 0xA001:
MMC3_CMDWrite(A, V); MMC3_CMDWrite(A, V);
FixMMC3PRG(MMC3_cmd); FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd); FixMMC3CHR(MMC3_cmd);
} else break;
MMC3_IRQWrite(A, V); case 0xC000:
mmc3_latch = V;
break;
case 0xC001:
mmc3_reload = 1;
break;
case 0xE000:
X6502_IRQEnd(FCEU_IQEXT);
mmc3_enabled = 0;
break;
case 0xE001:
mmc3_enabled = 1;
break;
}
} }
} }
static void M369Power(void) { static void FP_FASTAPASS(1) SMB2JIRQHook(int a) {
EXPREGS[0] = 0x00; if (mode != 0x13)
EXPREGS[1] = 0x00; return;
M40IRQa = 0x00;
M40IRQCount = 0x00; if (smb2j_enabled) {
GenMMC3Power(); if (smb2j_count < 4096)
SetWriteHandler(0x4120, 0x4120, M369WriteCMD); smb2j_count += a;
SetWriteHandler(0x8000, 0xFFFF, M369Write); else {
smb2j_enabled = 0;
X6502_IRQBegin(FCEU_IQEXT);
}
}
}
static void MMC3IRQHook(void) {
int32 count = mmc3_count;
if (mode == 0x13)
return;
if (!count || mmc3_reload) {
mmc3_count = mmc3_latch;
mmc3_reload = 0;
} else
mmc3_count--;
if (count && !mmc3_count && mmc3_enabled)
X6502_IRQBegin(FCEU_IQEXT);
} }
static void M369Reset(void) { static void M369Reset(void) {
EXPREGS[0] = 0x00; mode = 0;
EXPREGS[1] = 0x00; smb2_reg = 0;
M40IRQa = 0x00; smb2j_enabled = 0;
M40IRQCount = 0x00; smb2j_count = 0;
mmc3_count = mmc3_latch = mmc3_enabled = 0;
MMC3RegReset(); MMC3RegReset();
} }
static void FP_FASTAPASS(1) M40IRQHook(int a) { static void M369Power(void) {
if (EXPREGS[0] == 0x13) mode = 0;
{ smb2_reg = 0;
if (M40IRQa) smb2j_enabled = 0;
{ smb2j_count = 0;
if (M40IRQCount < 4096) mmc3_count = mmc3_latch = mmc3_enabled = 0;
M40IRQCount += a; GenMMC3Power();
else SetWriteHandler(0x4100, 0x4FFF, M369WriteLo);
{ SetWriteHandler(0x8000, 0xFFFF, M369Write);
M40IRQa = 0;
X6502_IRQBegin(FCEU_IQEXT);
}
}
}
} }
void Mapper369_Init(CartInfo *info) { void Mapper369_Init(CartInfo *info) {
GenMMC3_Init(info, 512, 384, 8, 0); GenMMC3_Init(info, 512, 384, 8, info->battery);
pwrap = M369PW; pwrap = SyncPRG;
cwrap = M369CW; cwrap = SyncCHR;
MapIRQHook = M40IRQHook;
info->Power = M369Power; info->Power = M369Power;
info->Reset = M369Reset; info->Reset = M369Reset;
AddExState(EXPREGS, 4, 0, "EXPR"); MapIRQHook = SMB2JIRQHook;
AddExState(&M40IRQa, 1, 0, "M2a"); GameHBIRQHook = MMC3IRQHook;
AddExState(&M40IRQCount, 2 | FCEUSTATE_RLSB, 0, "M2CN"); AddExState(&StateRegs, ~0, 0, 0);
} }