Overall cleanup.

src/boards/116.c

@@ -100,7 +100,7 @@ static void applyMode (uint8 clear) {
 	}
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (A &0x100) {
 		uint8 previousReg = reg;
 		reg = V;

src/boards/14.c

@@ -52,7 +52,7 @@ int getCHRBank_VRC2 (uint8 bank) {
 	return VRC24_getCHRBank(bank) | reg <<(~bank &4? 5: ~bank &2? 3: 1) &0x100;
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	uint8 previousReg = reg;
 	reg = V;
 	if ((previousReg ^V) &2)

src/boards/182.c

@@ -25,7 +25,7 @@
 
 static uint8 reg[4];
 
-static void sync() {
+static void sync () {
 	int prgAND = reg[1] &0x20? 0x1F: 0x0F;
 	int chrAND = reg[1] &0x40? 0xFF: 0x7F;
 	int prgOR = (reg[1] &0x02? 0x10: 0x00) | (reg[1] &0x10? 0x020: 0x00);
@@ -43,31 +43,31 @@ static void sync() {
 	MMC3_syncMirror();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (~reg[1] &0x01) {
 		reg[A &3] = V;
 		sync();
 	}
 }
 
-static DECLFW(unscramble) {
+static DECLFW (unscramble) {
 	static const uint16 lutAddress[8] = { 0xA001, 0xA000, 0x8000, 0xC000, 0x8001, 0xC001, 0xE000, 0xE001 }; /* i <5? 4-i: i */
 	static const uint8 lutIndex[8] = { 0, 3, 1, 5, 6, 7, 2, 4 }; /* i <6? (i^3)-1: i */
 	MMC3_writeReg(lutAddress[A >>12 &6 | A &1], (A &0xE001) == 0xA000? lutIndex[V &7]: V);
 }
 
-static void reset() {
+static void reset () {
 	reg[0] = reg[1] = reg[2] = reg[3] = 0;
 	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg[0] = reg[1] = reg[2] = reg[3] = 0;
 	MMC3_power();
 	SetWriteHandler(0x8000, 0xFFFF, unscramble);
 }
 
-void Mapper182_Init(CartInfo *info) {
+void Mapper182_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/183.c

@@ -23,7 +23,7 @@
 
 static uint8  prg;
 
-static SFORMAT Mapper183_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &prg, 1, "PRG6" },
 	{ 0 }
 };
@@ -35,18 +35,18 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(Mapper183_writePRG) {
+static DECLFW (writePRG) {
 	prg =A &0xFF;
 	sync();
 }
 
-void Mapper183_power(void) {
+static void power(void) {
 	prg =0;
 	VRC24_power();
 }
 
 void Mapper183_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, CartBR, Mapper183_writePRG, NULL);
-	AddExState(Mapper183_stateRegs, ~0, 0, 0);
-	info->Power =Mapper183_power;
+	VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, CartBR, writePRG, NULL);
+	AddExState(stateRegs, ~0, 0, 0);
+	info->Power =power;
 }

src/boards/222.c

@@ -27,7 +27,7 @@ static uint8 counter1;
 static uint8 counter2;
 static uint8 prescaler;
 
-static SFORMAT Mapper222_stateRegs[] ={
+static SFORMAT stateRegs[] = {
 	{ &clockMode, 1, "CLKM" },
 	{ &pending, 1, "PEND" },
 	{ &counter1, 1, "CNT1" },
@@ -42,39 +42,39 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(Mapper222_nibblizeCHR) {
+static DECLFW (nibblizeCHR) {
 	if (~A &1) {
 		VRC24_writeReg(A,    V);
 		VRC24_writeReg(A |1, V >>4);
 	}
 }
 
-DECLFW(Mapper222_writeIRQ) {
+static DECLFW (writeIRQ) {
 	switch(A &3) {
-		case 0: clockMode =0;
+		case 0: clockMode = 0;
 			break;
-		case 1: pending =false;
+		case 1: pending = 0;
 		        if (!clockMode) {
-				counter1 =V &0xF;
-				counter2 =V >>4;
+				counter1 = V &0xF;
+				counter2 = V >>4;
 			}
 			break;
-		case 2:	clockMode =1;
+		case 2:	clockMode = 1;
 			break;
 	}
 }
 
-void FP_FASTAPASS(1) Mapper222_cpuCycle(int a) {
+static void FP_FASTAPASS(1) cpuCycle (int a) {
 	while (a--) {
-		uint8 previousPrescaler =prescaler;
+		uint8 previousPrescaler = prescaler;
 		if (pending)
-			prescaler =0;
+			prescaler = 0;
 		else
 			prescaler++;
 		if (clockMode && ~previousPrescaler &0x40 && prescaler &0x40) {
-			if (++counter1 ==0xF && ++counter2 ==0xF) pending =1;
-			counter1 &=0xF;
-			counter2 &=0xF;
+			if (++counter1 == 0xF && ++counter2 == 0xF) pending = 1;
+			counter1 &= 0xF;
+			counter2 &= 0xF;
 		}
 		if (pending)
 			X6502_IRQBegin(FCEU_IQEXT);
@@ -83,16 +83,16 @@ void FP_FASTAPASS(1) Mapper222_cpuCycle(int a) {
 	}
 }
 
-void Mapper222_power(void) {
-	clockMode =pending =counter1 =counter2 =prescaler =0;
+static void power (void) {
+	clockMode = pending = counter1 = counter2 = prescaler = 0;
 	VRC24_power();
-	SetWriteHandler(0xB000, 0xEFFF, Mapper222_nibblizeCHR);
-	SetWriteHandler(0xF000, 0xFFFF, Mapper222_writeIRQ);
+	SetWriteHandler(0xB000, 0xEFFF, nibblizeCHR);
+	SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
 }
 
 void Mapper222_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
-	AddExState(Mapper222_stateRegs, ~0, 0, 0);
-	info->Power =Mapper222_power;
-	MapIRQHook =Mapper222_cpuCycle;
+	AddExState(stateRegs, ~0, 0, 0);
+	info->Power =power;
+	MapIRQHook = cpuCycle;
 }

src/boards/252_253.c

@@ -28,7 +28,7 @@ static uint8 compare;
 extern uint32 RefreshAddr;
 static writefunc writePPU;
 
-static SFORMAT stateRegs[] ={
+static SFORMAT stateRegs[] = {
 	{ &mask, 1, "CHRM" },
 	{ &compare, 1, "CHRC" },
         { 0 }
@@ -38,48 +38,48 @@ static void sync () {
 	int bank;
 	VRC24_syncWRAM(0);
 	VRC24_syncPRG(0x01F, 0x000);
-	for (bank =0; bank <8; bank++) setchr1r((VRC24_getCHRBank(bank) &mask) ==compare? 0x10: 0x00, bank <<10, VRC24_getCHRBank(bank));
+	for (bank = 0; bank < 8; bank++) setchr1r((VRC24_getCHRBank(bank) &mask) == compare? 0x10: 0x00, bank <<10, VRC24_getCHRBank(bank));
 	VRC24_syncMirror();
 }
 
-static DECLFW(Mapper252_253_interceptPPUWrite) {
+static DECLFW (Mapper252_253_interceptPPUWrite) {
 	if (~RefreshAddr &0x2000) {
-		int bank =VRC24_getCHRBank(RefreshAddr >>10 &7);
+		int bank = VRC24_getCHRBank(RefreshAddr >>10 &7);
 		switch(bank) {
-			case 0x88: mask =0xFC; compare =0x4C; sync(); break;
-			case 0xC2: mask =0xFE; compare =0x7C; sync(); break;
-			case 0xC8: mask =0xFE; compare =0x04; sync(); break;
+			case 0x88: mask = 0xFC; compare = 0x4C; sync(); break;
+			case 0xC2: mask = 0xFE; compare = 0x7C; sync(); break;
+			case 0xC8: mask = 0xFE; compare = 0x04; sync(); break;
 		}
 	}
 	writePPU(A, V);
 }
 
-void Mapper252_power (void) {
-	mask =0xFE;
-	compare =0x06;
+static void Mapper252_power (void) {
+	mask = 0xFE;
+	compare = 0x06;
 	VRC24_power();
-	writePPU =GetWriteHandler(0x2007);
+	writePPU = GetWriteHandler(0x2007);
 	SetWriteHandler(0x2007, 0x2007, Mapper252_253_interceptPPUWrite);
 }
 
-void Mapper253_power (void) {
-	mask =0xFE; /* There are two board revisions, the earlier one with a non-switchable mask/compare FE/04 and a later switchable one that starts with FC/28 */
-	compare =0x04;
+static void Mapper253_power (void) {
+	mask = 0xFE; /* There are two board revisions, the earlier one with a non-switchable mask/compare FE/04 and a later switchable one that starts with FC/28 */
+	compare = 0x04;
 	VRC24_power();
-	writePPU =GetWriteHandler(0x2007);
+	writePPU = GetWriteHandler(0x2007);
 	SetWriteHandler(0x2007, 0x2007, Mapper252_253_interceptPPUWrite);
 }
 
 void Mapper252_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x4, 0x8, 1, NULL, NULL, NULL, NULL, NULL);
 	CartRAM_init(info, 8, 2);
-	info->Power =Mapper252_power;
+	info->Power = Mapper252_power;
 	AddExState(stateRegs, ~0, 0, 0);
 }
 
 void Mapper253_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x4, 0x8, 1, NULL, NULL, NULL, NULL, NULL);
 	CartRAM_init(info, 8, 2);
-	info->Power =Mapper253_power;
+	info->Power = Mapper253_power;
 	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/266.c

@@ -23,7 +23,7 @@
 
 static uint8  prg;
 
-static SFORMAT UNLCITYFIGHT_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &prg, 1, "PRG8" },
 	{ 0 }
 };
@@ -34,7 +34,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(UNLCITYFIGHT_externalSelect) {
+static DECLFW (externalSelect) {
 	if (A &0x800)
 		(GetWriteHandler(0x4011))(0x4011, V <<3 &0x78);
 	else {
@@ -43,18 +43,18 @@ DECLFW(UNLCITYFIGHT_externalSelect) {
 	}
 }
 
-DECLFW(UNLCITYFIGHT_unscrambleAddress) {
+static DECLFW (unscrambleAddress) {
 	VRC24_writeReg(A &~0x6000 | A <<1 &0x4000 | A >>1 &0x2000, V);
 }
 
-void UNLCITYFIGHT_power(void) {
+static void power (void) {
 	prg =0;
 	VRC24_power();
-	SetWriteHandler(0x8000, 0xFFFF, UNLCITYFIGHT_unscrambleAddress);
+	SetWriteHandler(0x8000, 0xFFFF, unscrambleAddress);
 }
 
 void UNLCITYFIGHT_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, UNLCITYFIGHT_externalSelect);
-	AddExState(UNLCITYFIGHT_stateRegs, ~0, 0, 0);
-	info->Power =UNLCITYFIGHT_power;
+	VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, externalSelect);
+	AddExState(stateRegs, ~0, 0, 0);
+	info->Power =power;
 }

src/boards/273.c

@@ -40,7 +40,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-static DECLFW(writeIRQ) {
+static DECLFW (writeIRQ) {
 	switch(A &8) {
 		case 0:
 			irqCounter = V;
@@ -69,7 +69,7 @@ static void FP_FASTAPASS(1) cpuCycle (int a) {
 	}
 }
 
-static void power(void) {
+static void power (void) {
 	irqEnabled = irqCounter = irqPrescaler = irqMask = 0;
 	VRC24_power();
 	SetWriteHandler(0xF000, 0xFFFF, writeIRQ);

src/boards/280.c

@@ -21,9 +21,9 @@
 #include "mapinc.h"
 
 static uint16 latchAddr;
-static uint8  latchData;
-static uint8  mode;
-static uint8  submapper;
+static uint8 latchData;
+static uint8 mode;
+static uint8 submapper;
 
 static SFORMAT StateRegs[] = {
    { &latchAddr, 2 | FCEUSTATE_RLSB, "LATC" },

src/boards/285.c

@@ -59,13 +59,13 @@ static DECLFR (readPad) {
 	return pad >= 8? 0: pad &7;
 }
 
-static void power() {
+static void power () {
 	pad = 0;
 	Latch_power();
 	SetReadHandler(0x5000, 0x5FFF, readPad);
 }
 
-static void reset() {
+static void reset () {
 	pad = ++pad %24;
 	Latch_clear();
 }

src/boards/308.c

@@ -25,7 +25,7 @@ static uint8  irqEnabled;
 static uint16 irqCounterLow;
 static uint8  irqCounterHigh;
 
-static SFORMAT UNLTH21311_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &irqEnabled, 1, "IRQE" },
 	{ &irqCounterLow, 2 | FCEUSTATE_RLSB, "CNTL" },
 	{ &irqCounterHigh, 1, "CNTH" },
@@ -38,7 +38,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(UNLTH21311_writeIRQ) {
+static DECLFW (writeIRQ) {
 	switch(A &3) {
 	case 0:	X6502_IRQEnd(FCEU_IQEXT);
 		irqEnabled =0;
@@ -51,22 +51,22 @@ DECLFW(UNLTH21311_writeIRQ) {
 	}
 }
 
-void FP_FASTAPASS(1) UNLTH21311_cpuCycle(int a) {
+static void FP_FASTAPASS(1) cpuCycle (int a) {
 	while (a--) if (irqEnabled) {
 		if ((++irqCounterLow &4095) ==2048) irqCounterHigh--;
 		if (!irqCounterHigh && (irqCounterLow &4095) <2048) X6502_IRQBegin(FCEU_IQEXT);
 	}
 }
 
-void UNLTH21311_power(void) {
+static void power (void) {
 	irqEnabled =irqCounterLow =irqCounterHigh =0;
 	VRC24_power();
-	SetWriteHandler(0xF000, 0xFFFF, UNLTH21311_writeIRQ);
+	SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
 }
 
 void UNLTH21311_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
-	AddExState(UNLTH21311_stateRegs, ~0, 0, 0);
-	info->Power =UNLTH21311_power;
-	MapIRQHook =UNLTH21311_cpuCycle;
+	AddExState(stateRegs, ~0, 0, 0);
+	info->Power =power;
+	MapIRQHook =cpuCycle;
 }

src/boards/351.c

@@ -40,7 +40,7 @@ static void sync () {
 	int chrAND = reg[2] &0x40? 0x00: reg[2] &0x20? 0x7F: reg[2] &0x10? 0x1F: 0xFF; /* No inner bank in (C)NROM mode, 128K or 256K for others */
 	int prgOR  = reg[1] >>1 &(reg[2] &0x01 && CHRRAM? prgMask_CHRRAM: prgMask_CHRROM) &~prgAND;
 	int chrOR  = reg[0] <<1 &~chrAND;
-	
+
 	if (reg[2] &0x10) { /* NROM mode */
 		if (reg[2] &0x08) { /* NROM-64 */
 			setprg8(0x8000, prgOR);
@@ -61,7 +61,7 @@ static void sync () {
 		VRC24_syncPRG(prgAND, prgOR);
 	else
 		MMC1_syncPRG(prgAND >>1, prgOR >>1);
-		
+
 	if (reg[2] &0x01 && CHRRAM)
 		setchr8r(0x10, 0);
 	else
@@ -75,7 +75,7 @@ static void sync () {
 		VRC24_syncCHR(chrAND, chrOR);
 	else
 		MMC1_syncCHR(chrAND >>2, chrOR >>2);
-	
+
 	if (~reg[0] &0x02)
 		MMC3_syncMirror();
 	else
@@ -85,7 +85,7 @@ static void sync () {
 		MMC1_syncMirror();
 }
 
-DECLFW(VRC24_trapWriteReg) { /* When A11 is set, VRC4's A0 and A1 are swapped */
+DECLFW (VRC24_trapWriteReg) { /* When A11 is set, VRC4's A0 and A1 are swapped */
 	if (A &0x800) A = A &~0xF | A >>1 &0x5 | A <<1 &0xA;
 	VRC24_writeReg(A, V);
 }
@@ -107,25 +107,25 @@ static void applyMode (uint8 clear) {
 		MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, NULL, NULL, NULL, NULL);
 }
 
-static void Mapper351_restore (int version) {
+static void restore (int version) {
 	applyMode(0);
 	sync();
 }
 
-static DECLFR(readDIP) {
+static DECLFR (readDIP) {
 	return dip;
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg[A &3] = V;
 	applyMode(A == 2);
 }
 
-static DECLFW(writeFDSMirroring) {
+static DECLFW (writeFDSMirroring) {
 	MMC3_writeReg(0xA000, V >>3 &1);
 }
 
-static void Mapper351_power(void) {
+static void power (void) {
 	reg[0] = reg[1] = reg[2] = reg[3] = 0;
 	dip = 0;
 	SetReadHandler(0x5000, 0x5FFF, readDIP);
@@ -135,13 +135,13 @@ static void Mapper351_power(void) {
 	applyMode(1);
 }
 
-static void Mapper351_reset (void) {
+static void reset (void) {
 	reg[0] = reg[1] = reg[2] = reg[3] = 0;
 	dip++;
 	applyMode(1);
 }
 
-static void Mapper351_close(void) {
+static void close (void) {
 	if (CHRRAM) FCEU_gfree(CHRRAM);
 	if (PRGCHR) FCEU_gfree(PRGCHR);
 	CHRRAM = NULL;
@@ -153,20 +153,21 @@ void Mapper351_Init (CartInfo *info) {
 	MMC1_addExState();
 	MMC3_addExState();
 	VRC24_addExState();
-	info->Reset = Mapper351_reset;
-	info->Power = Mapper351_power;
-	info->Close = Mapper351_close;
-	GameStateRestore = Mapper351_restore;
-	AddExState(stateRegs, ~0, 0, 0);	
+	info->Reset = reset;
+	info->Power = power;
+	info->Close = close;
+	GameStateRestore = restore;
+	AddExState(stateRegs, ~0, 0, 0);
 
  	/* When CHR-RAM is enabled, CHR-ROM becomes part of PRG-ROM address space. */
 	prgMask_CHRROM = prgMask_CHRRAM = PRGsize[0] /8192 -1;
 	if (CHRRAMSIZE) {
+		uint8* newROM;
 		CHRRAM = (uint8 *)FCEU_gmalloc(CHRRAMSIZE);
 		SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1);
-		AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM");		
-		prgMask_CHRRAM = (PRGsize[0] +CHRsize[0]) /8192 -1;		
-		uint8* newROM = (uint8*)FCEU_gmalloc(PRGsize[0] +CHRsize[0]);
+		AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM");
+		prgMask_CHRRAM = (PRGsize[0] +CHRsize[0]) /8192 -1;
+		newROM = (uint8*)FCEU_gmalloc(PRGsize[0] +CHRsize[0]);
 		memcpy(newROM,              ROM, info->PRGRomSize);
 		memcpy(newROM +PRGsize[0], VROM, info->CHRRomSize);
 		FCEU_gfree(ROM);

src/boards/362.c

@@ -23,7 +23,7 @@
 
 static uint8 game;
 
-static SFORMAT Mapper362_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &game, 1, "GAME" },
 	{ 0 }
 };
@@ -40,21 +40,21 @@ static void sync () {
 	}
 }
 
-void Mapper362_power(void) {
+static void power (void) {
 	game =0;
 	VRC24_power();
 }
 
-void Mapper362_reset(void) {
+static void reset (void) {
 	game ^=1;
-	sync();
+	VRC24_clear();
 }	
 
 void Mapper362_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x01, 0x02, 0, NULL, NULL, NULL, NULL, NULL);
-	info->Power =Mapper362_power;
+	info->Power = power;
 	if (PRGsize[0] >512*1024) {
-		info->Reset =Mapper362_reset;
-		AddExState(Mapper362_stateRegs, ~0, 0, 0);
+		info->Reset = reset;
+		AddExState(stateRegs, ~0, 0, 0);
 	}
 }

src/boards/384.c

@@ -24,7 +24,7 @@
 
 static uint8 reg;
 
-static SFORMAT Mapper384_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &reg, 1, "EXP0" },
 	{ 0 }
 };
@@ -36,7 +36,7 @@ static void sync () {
 	VRC24_syncWRAM(0);
 }
 
-DECLFW(Mapper384_writeReg) {
+static DECLFW (writeReg) {
 	if (A &0x800 && ~reg &0x08) {
 		reg =V;
 		sync();
@@ -44,20 +44,20 @@ DECLFW(Mapper384_writeReg) {
 	CartBW(A, V);
 }
 
-void Mapper384_power(void) {
+static void power (void) {
 	reg =0;
 	VRC24_power();
 }
 
-void Mapper384_reset(void) {
+static void reset (void) {
 	reg =0;
-	sync();
-}	
+	VRC24_clear();
+}
 
 void Mapper384_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, Mapper384_writeReg, NULL);
+	VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, writeReg, NULL);
 	WRAM_init(info, 2);
-	info->Power =Mapper384_power;
-	info->Reset =Mapper384_reset;
-	AddExState(Mapper384_stateRegs, ~0, 0, 0);
+	info->Power =power;
+	info->Reset =reset;
+	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/398.c

@@ -23,7 +23,7 @@
 
 static uint8 reg;
 
-static SFORMAT Mapper398_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &reg, 1, "EXP0" },
 	{ 0 }
 };
@@ -39,25 +39,25 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(Mapper398_writeReg) {
+static DECLFW (writeReg) {
 	reg =A &0xFF;	
 	VRC24_writeReg(A, V);
 }
 
-void Mapper398_power(void) {
-	reg =0xC0;
+static void power (void) {
+	reg = 0xC0;
 	VRC24_power();
-	SetWriteHandler(0x8000, 0xFFFF, Mapper398_writeReg);
+	SetWriteHandler(0x8000, 0xFFFF, writeReg);
 }
 
-void Mapper398_reset(void) {
-	reg =0xC0;
-	sync();
+static void reset (void) {
+	reg = 0xC0;
+	VRC24_clear();
 }	
 
 void Mapper398_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL);
-	info->Power =Mapper398_power;
-	info->Reset =Mapper398_reset;
-	AddExState(Mapper398_stateRegs, ~0, 0, 0);
+	info->Power = power;
+	info->Reset = reset;
+	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/432.c

@@ -27,11 +27,11 @@ static uint8 submapper;
 static uint8 reg[2];
 static uint8 pad;
 
-static DECLFR(readPad) {
+static DECLFR (readPad) {
 	return pad;
 }
 
-static void sync() {
+static void sync () {
 	int prgAND = reg[1] &0x02? 0x0F: 0x1F;
 	int chrAND = reg[1] &0x20 && submapper == 3? 0x1FF: reg[1] &0x04? 0x7F: 0xFF;
 	int prgOR  = reg[1] <<4 &0x10 | reg[1] <<1 &0x60;
@@ -42,7 +42,7 @@ static void sync() {
 	SetReadHandler(0x8000, 0xFFFF, submapper == 1 && reg[1] &0x20 || submapper != 1 && reg[0] &0x01? readPad: CartBR);
 }
 
-static int getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	if (reg[1] &0x40) {
 		int mask = reg[1] &(submapper == 2? 0x20: 0x80)? 3: 1;
 		return MMC3_getPRGBank(bank &1) &~mask | bank &mask;
@@ -50,14 +50,14 @@ static int getPRGBank(uint8 bank) {
 		return MMC3_getPRGBank(bank);
 }
 
-static int getCHRBank(uint8 bank) {
+static int getCHRBank (uint8 bank) {
 	if (reg[1] &0x20 && submapper == 3)
 		return MMC3_getCHRBank(bank &6 | bank >>1 &1) <<1 | bank &1;
 	else
 		return MMC3_getCHRBank(bank);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (submapper == 3 && reg[1] &0x80)
 		;
 	else {
@@ -66,19 +66,19 @@ static DECLFW(writeReg) {
 	}
 }
 
-static void reset() {
+static void reset () {
 	reg[0] = reg[1] = 0;
 	++pad;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg[0] = reg[1] = 0;
 	pad = 0;
 	MMC3_power();
 }
 
-void Mapper432_Init(CartInfo *info) {
+void Mapper432_Init (CartInfo *info) {
 	submapper =info->submapper;
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, getPRGBank, getCHRBank, NULL, writeReg);
 	info->Power = power;

src/boards/445.c

@@ -66,7 +66,7 @@ static void sync () {
 	SetReadHandler(0x8000, 0xFFFF, reg[0] &0xC0 && (reg[0] &0xC0) == dip? NULL: CartBR);
 }
 
-static void applyMode(uint8 clear) {
+static void applyMode (uint8 clear) {
 	if ((reg[2] >>3 &7) >= 5)
 		Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
 	else
@@ -84,7 +84,7 @@ static void Mapper445_restore (int version) {
 	sync();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (~reg[3] &0x20) {
 		reg[A &3] = V;
 		if ((A &3) == 3) applyMode(1);

src/boards/446.c

@@ -165,7 +165,7 @@ static void sync_QJ (int prgAND, int prgOR, int chrAND, int chrOR) {
 	QJ_syncCHR(chrAND, chrOR &~chrAND);
 	QJ_syncMirror();
 }
-static void sync_TC3294(int prgAND, int prgOR, int chrAND, int chrOR) {
+static void sync_TC3294 (int prgAND, int prgOR, int chrAND, int chrOR) {
 	TC3294_syncWRAM(reg[5]);
 	TC3294_syncPRG(prgAND, prgOR &~prgAND);
 	setchr8(0);
@@ -240,19 +240,19 @@ static void sync_supervisor (int prgAND, int prgOR, int chrAND, int chrOR) {
 	setmirror(reg[4] &0x01? MI_V: MI_H);
 }
 
-static DECLFW(writeFlash) {
+static DECLFW (writeFlash) {
 	flashrom_write(A &0x1FFF | (Page[A >>11] +A -PRGptr[0]) &~0x1FFF, V);
 }
 
-static int SUROM_getPRGBank(uint8 bank) {
+static int SUROM_getPRGBank (uint8 bank) {
 	return MMC1_getPRGBank(bank) | MMC1_getCHRBank(0) &0x10;
 }
 
-static int Mapper22_getCHRBank(uint8 bank) {
+static int Mapper22_getCHRBank (uint8 bank) {
 	return VRC24_getCHRBank(bank &7) >>1;
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg[A &7] = V;
 	if ((A &7) == 0)
 		applyMode(1);
@@ -388,17 +388,17 @@ static void applyMode (uint8 clear) {
 	}
 }
 
-static void power() {
+static void power () {
 	reg[0] = reg[1] = reg[2] = reg[3] = reg[4] = reg[5] = reg[6] = reg[7] = 0;
 	applyMode(1);
 	SetReadHandler(0x8000, 0xFFFF, CartBR);
 }
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	applyMode(0);
 }
 
-void Mapper446_Init(CartInfo *info) {
+void Mapper446_Init (CartInfo *info) {
 	submapper =info->submapper;
 	H3001_addExState();
 	Latch_addExState();

src/boards/447.c

@@ -25,7 +25,7 @@
 static uint8 reg;
 static uint8 dip;
 
-static SFORMAT Mapper447_stateRegs[] ={
+static SFORMAT stateRegs[] = {
 	{ &reg, 1, "EXP0" },
 	{ &dip, 1, "DIPS" },
 	{ 0 }
@@ -38,7 +38,7 @@ static void sync () {
 	VRC24_syncWRAM(0);
 }
 
-static int Mapper447_getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	if (reg &4) {
 		if (~reg &2)
 			return VRC24_getPRGBank(bank &1) &~2 | bank &2;
@@ -48,35 +48,35 @@ static int Mapper447_getPRGBank(uint8 bank) {
 		return VRC24_getPRGBank(bank);
 }
 
-DECLFR(Mapper447_readPRG) {
+static DECLFR (readPRG) {
 	return CartBR(reg &8? (A &~3 | dip &3): A);
 }
 
-DECLFW(Mapper447_writeReg) {
+static DECLFW (writeReg) {
 	if (~reg &1) {
-		reg =A &0xFF;
+		reg = A &0xFF;
 		sync();
 	}
 	CartBW(A, V);
 }
 
-void Mapper447_power(void) {
-	reg =0;
-	dip =0;
+static void power (void) {
+	reg = 0;
+	dip = 0;
 	VRC24_power();
-	SetReadHandler(0x8000, 0xFFFF, Mapper447_readPRG);
+	SetReadHandler(0x8000, 0xFFFF, readPRG);
 }
 
-void Mapper447_reset(void) {
-	reg =0;
+static void reset (void) {
+	reg = 0;
 	dip++;
 	sync();
-}	
+}
 
 void Mapper447_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x04, 0x08, 0, Mapper447_getPRGBank, NULL, NULL, Mapper447_writeReg, NULL );
+	VRC4_init(info, sync, 0x04, 0x08, 0, getPRGBank, NULL, NULL, writeReg, NULL );
 	WRAM_init(info, 2);
-	info->Power =Mapper447_power;
-	info->Reset =Mapper447_reset;
-	AddExState(Mapper447_stateRegs, ~0, 0, 0);
+	info->Power = power;
+	info->Reset = reset;
+	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/448.c

@@ -24,7 +24,7 @@
 
 static uint8 reg;
 
-static SFORMAT Mapper448_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &reg, 1, "EXP0" },
 	{ 0 }
 };
@@ -46,31 +46,31 @@ static void sync () {
 	setchr8(0);
 }
 
-DECLFW(Mapper448_writeReg) {
+static DECLFW (writeReg) {
 	reg =A &0xFF;
 	sync();
 	CartBW(A, V);
 }
 
-DECLFW(Mapper448_writePRG) {
+static DECLFW (writePRG) {
 	VRC24_writeReg(reg &8? 0x8000: A, V);
 }
 
-void Mapper448_power(void) {
+static void power (void) {
 	reg =0;
 	VRC24_power();
-	SetWriteHandler(0x8000, 0xFFFF, Mapper448_writePRG);
+	SetWriteHandler(0x8000, 0xFFFF, writePRG);
 }
 
-void Mapper448_reset(void) {
+static void reset (void) {
 	reg =0;
-	sync();
-}	
+	VRC24_clear();
+}
 
 void Mapper448_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, Mapper448_writeReg, NULL);
+	VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, writeReg, NULL);
 	WRAM_init(info, 2);
-	info->Power =Mapper448_power;
-	info->Reset =Mapper448_reset;
-	AddExState(Mapper448_stateRegs, ~0, 0, 0);
+	info->Power =power;
+	info->Reset =reset;
+	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/449.c

@@ -25,15 +25,15 @@ uint8 submapper;
 uint8 pad;
 uint8 padSelect;
 
-static DECLFR(readPad_submapper0) {
+static DECLFR (readPad_submapper0) {
 	return CartBR(A &~0xF | pad &0xF);
 }
 
-static DECLFR(readPad_submapper1) {
+static DECLFR (readPad_submapper1) {
 	return pad;
 }
 
-static DECLFR(readPad_submapper2) {
+static DECLFR (readPad_submapper2) {
 	return CartBR(A &~0x3 | pad &0x3);
 }
 
@@ -57,7 +57,7 @@ static void sync () {
 	SetReadHandler(0x8000, 0xFFFF, submapper == 0 && Latch_address &0x200? readPad_submapper0: submapper == 2 && padSelect &1? readPad_submapper2: CartBR);
 }
 
-static DECLFW(writePad_submapper2) {
+static DECLFW (writePad_submapper2) {
 	padSelect = V;
 	sync();
 }
@@ -75,8 +75,7 @@ static void power () {
 static void reset () {
 	pad++;
 	padSelect = 0;
-	Latch_address = 0;
-	sync();
+	Latch_clear();
 }
 
 void Mapper449_Init (CartInfo *info) {

src/boards/450.c

@@ -27,12 +27,12 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-void Mapper450_reset(void) {
-	VRC2_pins =0;
-	sync();
-}	
+static void reset(void) {
+	VRC2_pins = 0;
+	VRC24_clear();
+}
 
 void Mapper450_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
-	info->Reset =Mapper450_reset;
+	info->Reset = reset;
 }

src/boards/458.c

@@ -1,7 +1,7 @@
 /* FCEUmm - NES/Famicom Emulator
  *
  * Copyright notice for this file:
- *  Copyright (C) 2020
+ *  Copyright (C) 2025 NewRisingSun
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by

src/boards/460.c

@@ -22,11 +22,11 @@
 
 #include "mapinc.h"
 #include "asic_mmc3.h"
+#include "cartram.h"
 
 static uint8 submapper;
 static uint8 reg;
 static uint8 pad;
-static uint8 *CHRRAM = NULL;
 
 static DECLFR (readPad) {
 	return CartBR(A &~3 | pad &3);
@@ -74,23 +74,12 @@ static void power () {
 	MMC3_power();
 }
 
-static void close () {
-	if (CHRRAM) {
-		FCEU_gfree(CHRRAM);
-		CHRRAM = NULL;
-	}
-}
-
 void Mapper460_Init (CartInfo *info) {
 	submapper = info->submapper;
 	MMC3_init(info, sync, MMC3_TYPE_SHARP, getPRGBank, getCHRBank, NULL, writeReg);
+	CHRRAM_init(info, 8);
 	info->Power = power;
 	info->Reset = reset;
-	info->Close = close;
 	AddExState(&reg, 1, 0, "EXPR");
 	AddExState(&reg, 1, 0, "DIPS");
-
-	CHRRAM = (uint8 *)FCEU_gmalloc(8192);
-	SetupCartCHRMapping(0x10, CHRRAM, 8192, 1);
-	AddExState(CHRRAM, 8192, 0, "CRAM");
 }

src/boards/468.c

@@ -67,7 +67,7 @@ static const uint16 lut509[512] = { /* Look-up table, used only by Legendary Gam
  483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 512, 513, 514, 515, 516, 517
 };
 
-void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */
+static void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */
 	if (select)
 		state = 0;
 	else
@@ -145,7 +145,7 @@ static void sync_IF12 (int prgOR) {
 	setmirror(Custom_reg[0] &0x01? MI_H: MI_V);
 }
 
-static DECLFW(IF12_writeReg) {
+static DECLFW (IF12_writeReg) {
 	Custom_reg[A >>14 &1] = V;
 	sync();
 }
@@ -160,7 +160,7 @@ static void sync_LF36 (int prgOR) {
 	setmirror(reg[0] &0x04? MI_H: MI_V);
 }
 
-void FP_FASTAPASS(1) LF36_cpuCycle (int a) {
+static void FP_FASTAPASS(1) LF36_cpuCycle (int a) {
 	while (a--) {
 		if (Custom_reg[1] &1) {
 			if (!++Custom_reg[2]) ++Custom_reg[3];
@@ -201,7 +201,7 @@ static void sync_Misc (int prgOR) {
 		setmirror(Custom_reg[1] &0x10? MI_1: MI_0);
 }
 
-static DECLFW(Misc_writeReg) {
+static DECLFW (Misc_writeReg) {
 	switch(A >>12 &7) {
 		case 0: case 2: case 3:
 			Custom_reg[0] = V;
@@ -232,7 +232,7 @@ static void Nanjing_scanline (void) {
 		setchr8(0);
 }
 
-static DECLFW(Nanjing_writeReg) {
+static DECLFW (Nanjing_writeReg) {
 	Custom_reg[A >>8 &3] = V;
 	sync();
 }
@@ -259,7 +259,7 @@ static void sync_SUROM (int prgOR) {
 	MMC1_syncMirror();
 }
 
-static int SUROM_getPRGBank(uint8 bank) {
+static int SUROM_getPRGBank (uint8 bank) {
 	return MMC1_getPRGBank(bank) | MMC1_getCHRBank(0) &0x10;
 }
 
@@ -348,7 +348,7 @@ static void sync_VRC7 (int prgOR) {
 }
 
 /* Supervisor */
-static DECLFR(readReg) {
+static DECLFR (readReg) {
 	switch(A) {
 		case 0x5301: case 0x5601:
 			return output? 0x80: 0x00;
@@ -357,7 +357,7 @@ static DECLFR(readReg) {
 	}
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	switch(A) {
 		case 0x5301:
 			if (submapper == 0) setPins(!!(V &0x04), !!(V &0x02), !!(V &0x01));
@@ -500,7 +500,7 @@ static void applyMode (uint8 clear) {
 	}
 }
 
-static void power() {
+static void power () {
 	reg[0] = 0x0F;
 	reg[1] = 0xFF;
 	reg[2] = submapper == 1? 0x10: 0x00;
@@ -511,11 +511,11 @@ static void power() {
 }
 
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	applyMode(0);
 }
 
-void Mapper468_Init(CartInfo *info) {
+void Mapper468_Init (CartInfo *info) {
 	submapper = info->submapper;
 	FME7_addExState();
 	Latch_addExState();

src/boards/483.c

@@ -66,9 +66,10 @@ static void power () {
 	applyMode(1);
 }
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	applyMode(0);
 }
+
 void Mapper483_Init (CartInfo *info) {
 	AddExState(&game, 1, 0, "GAME");
 	Latch_addExState();

src/boards/490.c

@@ -26,11 +26,11 @@
 static uint8 reg;
 static uint8 pad;
 
-static DECLFR(readPad) {
+static DECLFR (readPad) {
 	return CartBR(A &~0xF | pad &0xF);
 }
 
-static void sync() {
+static void sync () {
 	if (reg &0x20)
 		setprg32(0x8000, reg >>1);
 	else {
@@ -42,24 +42,24 @@ static void sync() {
 	SetReadHandler(0x8000, 0xFFFF, reg &0x80? readPad: CartBR);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
-	reg = 0;
-	++pad;
-	sync();
-}
-
-static void power() {
+static void power () {
 	reg = 0;
 	pad = 0;
 	MMC3_power();
 }
 
-void Mapper490_Init(CartInfo *info) {
+static void reset () {
+	reg = 0;
+	++pad;
+	MMC3_clear();
+}
+
+void Mapper490_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/494.c

@@ -23,7 +23,7 @@
 
 static uint8 pad;
 
-static DECLFR(readOB) {
+static DECLFR (readOB) {
 	return X.DB;
 }
 
@@ -43,12 +43,12 @@ static void sync () {
 	SetReadHandler(0x8000, 0xFFFF, ~Latch_address &0x100 && Latch_address &0x001 &pad? readOB: CartBR);
 }
 
-static void power() {
+static void power () {
 	pad = 0;
 	Latch_power();
 }
 
-static void reset() {
+static void reset () {
 	pad++;
 	Latch_clear();
 }

src/boards/495.c

@@ -31,7 +31,7 @@ static SFORMAT stateRegs[] = {
 	{ 0 }
 };
 
-static void sync() {
+static void sync () {
 	setprg8(0x8000, prg[0]);
 	setprg8(0xA000, prg[1]);
 	setprg8(0xC000, prg[2]);
@@ -53,7 +53,7 @@ static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A) {
 	}
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (A <0xE000)
 		prg[A >>13 &3] = V;
 	else

src/boards/503.c

@@ -26,11 +26,11 @@
 static uint8 reg;
 static uint8 pad;
 
-static DECLFR(readPad) {
+static DECLFR (readPad) {
 	return CartBR(A &~3 | pad &3);
 }
 
-static void sync() {
+static void sync () {
 	if (reg &0x10)
 		setprg32(0x8000, reg >>1);
 	else {
@@ -42,24 +42,24 @@ static void sync() {
 	SetReadHandler(0x8000, 0xFFFF, reg &0x20? readPad: CartBR);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
 	++pad;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	pad = 0;
 	MMC3_power();
 }
 
-void Mapper503_Init(CartInfo *info) {
+void Mapper503_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/504.c

@@ -25,7 +25,7 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int prgAND = reg &0x02? 0x0F: 0x1F;
 	int chrAND = reg &0x02? 0x7F: 0xFF;
 	int prgOR = reg <<4;
@@ -35,29 +35,29 @@ static void sync() {
 	MMC3_syncMirror();
 }
 
-static int getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	if ((reg &0x03) == 0x03 && ~reg &0x08)
 		return MMC3_getPRGBank(bank &1) &~1 | bank &1;
 	else
 		return MMC3_getPRGBank(bank);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	MMC3_power();
 }
 
-void Mapper504_Init(CartInfo *info) {
+void Mapper504_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, getPRGBank, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/505.c

@@ -60,6 +60,6 @@ void Mapper505_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, readPad, writeReg);
 	info->Power = power;
 	info->Reset = reset;
-	AddExState(&reg, 2, 0, "EXPR");
+	AddExState(&reg, 2 | FCEUSTATE_RLSB, 0, "EXPR");
 	AddExState(&pad, 1, 0, "DIPS");
 }

src/boards/506.c

@@ -25,32 +25,32 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int prgAND =~reg &3? 0x0F: 0x1F;
 	int chrAND = reg &3? 0x7F: 0xFF;
-	int prgOR  = reg <<5 &0x20  | reg <<3 &0x10;
-	int chrOR  = reg <<7 &0x100 |~reg <<7 &0x80;
+	int prgOR = reg <<5 &0x20  | reg <<3 &0x10;
+	int chrOR = reg <<7 &0x100 |~reg <<7 &0x80;
 	MMC3_syncPRG(prgAND, prgOR &~prgAND);
 	MMC3_syncCHR(chrAND, chrOR &~chrAND);
 	MMC3_syncMirror();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	MMC3_power();
 }
 
-void Mapper506_Init(CartInfo *info) {
+void Mapper506_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/512.c

@@ -29,13 +29,13 @@ static uint8 reg;
 static void sync () {
 	MMC3_syncPRG(0x3F, 0x00);
 	MMC3_syncWRAM(0);
-	
+
 	if (reg &0x02) {
 		setchr4r(0x10, 0x0000, 0);
 		setchr4r(0x10, 0x1000, 0);
 	} else
 		MMC3_syncCHR(0xFF, 0x000);
-	
+
 	if (reg == 1) { /* The game uses six nametables - the two console-internal ones, plus four occupying the second half of 8 KiB CHR-RAM.*/
 		setntamem(CHRptr[0x10] +0x1000, 1, 0);
 		setntamem(CHRptr[0x10] +0x1400, 1, 1);

src/boards/524.c

@@ -24,7 +24,7 @@
 static uint8  irqEnabled;
 static uint16 irqCounter;
 
-static SFORMAT BTL900218_stateRegs[] ={
+static SFORMAT stateRegs[] ={
 	{ &irqEnabled, 1, "IRQE" },
 	{ &irqCounter, 2 | FCEUSTATE_RLSB, "CNTL" },
 	{ 0 }
@@ -36,7 +36,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(BTL900218_writeIRQ) {
+static DECLFW (writeIRQ) {
 	if (A &8) {
 		if (A &4) {
 			irqEnabled =0;
@@ -47,19 +47,19 @@ DECLFW(BTL900218_writeIRQ) {
 	}
 }
 
-void FP_FASTAPASS(1) BTL900218_cpuCycle(int a) {
+static void FP_FASTAPASS(1) cpuCycle (int a) {
 	while (a--) if (irqEnabled && ++irqCounter &1024) X6502_IRQBegin(FCEU_IQEXT);
 }
 
-void BTL900218_power(void) {
+static void power (void) {
 	irqEnabled =irqCounter =0;
 	VRC24_power();
-	SetWriteHandler(0xF000, 0xFFFF, BTL900218_writeIRQ);
+	SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
 }
 
 void BTL900218_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
-	AddExState(BTL900218_stateRegs, ~0, 0, 0);
-	info->Power =BTL900218_power;
-	MapIRQHook =BTL900218_cpuCycle;
+	AddExState(stateRegs, ~0, 0, 0);
+	info->Power =power;
+	MapIRQHook =cpuCycle;
 }

src/boards/525.c

@@ -27,7 +27,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFW(UNLKS7021A_writeCHR) {
+DECLFW (UNLKS7021A_writeCHR) {
 	VRC24_writeReg(0xB000 +(A <<11 &0x3000 | A <<1 &0x0002), V &0x0F);
 	VRC24_writeReg(0xB001 +(A <<11 &0x3000 | A <<1 &0x0002), V >>4);
 }
@@ -39,5 +39,5 @@ void UNLKS7021A_power (void) {
 
 void UNLKS7021A_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
-	info->Power =UNLKS7021A_power;
+	info->Power = UNLKS7021A_power;
 }

src/boards/529.c

@@ -36,25 +36,25 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-DECLFR(UNLT230_readEEPROM) {
+static DECLFR (readEEPROM) {
 	return eeprom_93Cx6_read()? 0x01: 0x00;
 }
 	
-DECLFW(UNLT230_writeEEPROM) {
+static DECLFW (writeEEPROM) {
 	eeprom_93Cx6_write(A &0x04, A &0x02, A &0x01);
 }
 
-void UNLT230_power (void) {
+static void power (void) {
 	VRC24_power();
 	eeprom_93Cx6_init(256, 16);
-	SetReadHandler(0x5000, 0x5FFF, UNLT230_readEEPROM);
-	SetWriteHandler(0xF800, 0xFFFF, UNLT230_writeEEPROM);
+	SetReadHandler(0x5000, 0x5FFF, readEEPROM);
+	SetWriteHandler(0xF800, 0xFFFF, writeEEPROM);
 }
 
 void UNLT230_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, NULL);
 	if (info->PRGRamSaveSize) {
-		info->Power =UNLT230_power;
+		info->Power =power;
 		AddExState(stateRegs, ~0, 0, 0);
 		eeprom_93Cx6_storage = eeprom_data;
 		info->battery = 1;

src/boards/530.c

@@ -27,26 +27,26 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-int UNLAX5705_getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	int result =VRC24_getPRGBank(bank);
 	return result <<2 &0x8 | result >>2 &0x2 | result &~0xA;
 }
 
-int UNLAX5705_getCHRBank(uint8 bank) {
+static int getCHRBank (uint8 bank) {
 	int result =VRC24_getCHRBank(bank);
 	return result <<1 &0x40 | result >>1 &0x20 | result &~0x60;
 }
 
-DECLFW(UNLAX5705_unscrambleAddress) {
+static DECLFW (unscrambleAddress) {
 	VRC24_writeReg(A &~0x1000 | A <<9 &0x1000, V);
 }
 
-void UNLAX5705_power (void) {
+static void power (void) {
 	VRC24_power();
-	SetWriteHandler(0x8000, 0xFFFF, UNLAX5705_unscrambleAddress);
+	SetWriteHandler(0x8000, 0xFFFF, unscrambleAddress);
 }
 
 void UNLAX5705_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x01, 0x02, 1, UNLAX5705_getPRGBank, UNLAX5705_getCHRBank, NULL, NULL, NULL);
-	info->Power =UNLAX5705_power;
+	VRC4_init(info, sync, 0x01, 0x02, 1, getPRGBank, getCHRBank, NULL, NULL, NULL);
+	info->Power =power;
 }

src/boards/542.c

@@ -36,7 +36,7 @@ static void sync () {
 	if (reg &1) setchr1r(0x10, 0x0C00, 1);
 }
 
-DECLFW(Mapper542_writeExtra) {
+DECLFW (writeExtra) {
 	if (A &0x800) {
 		reg =A >>12;
 		sync();
@@ -45,16 +45,16 @@ DECLFW(Mapper542_writeExtra) {
 }
 
 
-void Mapper542_power (void) {
+void power (void) {
 	reg =0;
 	VRC24_power();
 	SetReadHandler(0x6000, 0x7FFF, CartBR);
-	SetWriteHandler(0xD000, 0xEFFF, Mapper542_writeExtra);
+	SetWriteHandler(0xD000, 0xEFFF, writeExtra);
 }
 
 void Mapper542_Init (CartInfo *info) {
 	VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL);
-	info->Power =Mapper542_power;
+	info->Power =power;
 	AddExState(stateRegs, ~0, 0, 0);
 	SetupCartCHRMapping(0x10, NTARAM, 0x200, 1);
 }

src/boards/544.c

@@ -78,7 +78,7 @@ static DECLFW (externalSelect) {
 }
 
 
-void power (void) {
+static void power (void) {
 	mask =0xFC;
 	compare =0x28;
 	nt[0] =nt[1] =0xE0;

src/boards/548.c

@@ -33,7 +33,7 @@ static SFORMAT stateRegs[] ={
 	{ &reg, 1, "REGM" },
 	{ &latch, 1, "LATC" },
 	{ &counting, 1, "IRQA" },
-	{ &counter, 2, "IRQC" },
+	{ &counter, 2 | FCEUSTATE_RLSB, "IRQC" },
         { 0 }
 };
 
@@ -72,7 +72,7 @@ static void FP_FASTAPASS(1) cpuCycle (int a) {
 	}
 }
 
-static void reset() {
+static void reset () {
 	FDSSoundReset();
 	X6502_IRQEnd(FCEU_IQEXT);
 	latch = 0x07;
@@ -82,7 +82,7 @@ static void reset() {
 	sync();
 }
 
-static void power() {
+static void power () {
 	FDSSoundPower();
 	SetReadHandler(0x6000, 0xFFFF, CartBR);
 	SetWriteHandler(0x4800, 0x4FFF, writeLatch);
@@ -91,7 +91,7 @@ static void power() {
 	reset();
 }
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	sync();
 }
 

src/boards/556.c

@@ -31,8 +31,8 @@ static uint8 reg[4];
 static uint8 index;
 
 static SFORMAT StateRegs[] = {
-	{ reg,            5, "REGS" },
-	{ &index,         1, "INDX" },
+	{ reg, 4, "REGS" },
+	{ &index, 1, "INDX" },
 	{ 0 },
 };
 

src/boards/557.c

@@ -24,14 +24,14 @@
 #include "asic_n118.h"
 #include "cartram.h"
 
-static void sync() {
+static void sync () {
 	setprg8r(0x10, 0x6000, 0);
 	N118_syncPRG(0x0F, 0x00);
 	setchr8(0);
 	setmirror(N118_getCHRBank(7) &0x20? MI_H: MI_V);
 }
 
-void Mapper557_Init(CartInfo *info) {
+void Mapper557_Init (CartInfo *info) {
 	N118_init(info, sync, NULL, NULL);
 	WRAM_init(info, 8);
 }

src/boards/559.c

@@ -38,11 +38,11 @@ static void sync () {
 	setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
 }
 
-int Mapper559_getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	return bank ==2? prg: VRC24_getPRGBank(bank);
 }
 
-DECLFW(Mapper559_externalSelect) {
+static DECLFW (externalSelect) {
 	if (A &4)
 		nt[A &3] =V;
 	else
@@ -50,20 +50,20 @@ DECLFW(Mapper559_externalSelect) {
 	sync();
 }
 
-DECLFW(Mapper559_nibblizeData) {
+static DECLFW (nibblizeData) {
 	VRC24_writeReg(A, V >>(A &0x400? 4: 0));
 }
 
-void Mapper559_power (void) {
+static void power (void) {
 	nt[0] =nt[1] =0xE0;
 	nt[2] =nt[3] =0xE1;
 	prg =0xFE;
 	VRC24_power();
-	SetWriteHandler(0xB000, 0xFFFF, Mapper559_nibblizeData);
+	SetWriteHandler(0xB000, 0xFFFF, nibblizeData);
 }
 
 void Mapper559_Init (CartInfo *info) {
-	VRC4_init(info, sync, 0x400, 0x800, 1, Mapper559_getPRGBank, NULL, NULL, NULL, Mapper559_externalSelect);
-	info->Power =Mapper559_power;
+	VRC4_init(info, sync, 0x400, 0x800, 1, getPRGBank, NULL, NULL, NULL, externalSelect);
+	info->Power =power;
 	AddExState(stateRegs, ~0, 0, 0);
 }

src/boards/563.c

@@ -36,7 +36,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-static DECLFW(Mapper563_writeIRQ) {
+static DECLFW (Mapper563_writeIRQ) {
 	X6502_IRQEnd(FCEU_IQEXT);
 	switch(A &0x1C) {
 		case 0x0C: irqEnabled =0; break;
@@ -49,8 +49,8 @@ static void Mapper563_scanline (void) { /* Actually, a sixteen-stage counter tri
 	if (!(++irqCounter &1) && irqEnabled) X6502_IRQBegin(FCEU_IQEXT);
 }
 
-static void Mapper563_power(void) {
-	irqEnabled =irqCounter =0;
+static void Mapper563_power (void) {
+	irqEnabled = irqCounter =0;
 	VRC24_power();
 	SetWriteHandler(0xF000, 0xFFFF, Mapper563_writeIRQ);
 }
@@ -58,6 +58,6 @@ static void Mapper563_power(void) {
 void Mapper563_Init (CartInfo *info) {
 	VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
 	AddExState(Mapper563_stateRegs, ~0, 0, 0);
-	info->Power =Mapper563_power;
+	info->Power = Mapper563_power;
 	GameHBIRQHook = Mapper563_scanline;
 }

src/boards/565.c

@@ -38,7 +38,7 @@ static void sync () {
 	VRC24_syncMirror();
 }
 
-static DECLFW(writeIRQ) {
+static DECLFW (writeIRQ) {
 	switch(A &0x0C) {
 		case 0:
 			irqCounter = V;
@@ -64,7 +64,7 @@ static void FP_FASTAPASS(1) cpuCycle (int a) {
 	}
 }
 
-static void power(void) {
+static void power (void) {
 	irqEnabled = irqCounter = irqPrescaler = 0;
 	VRC24_power();
 	SetWriteHandler(0xF000, 0xFFFF, writeIRQ);

src/boards/567.c

@@ -25,7 +25,7 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	MMC3_syncPRG(0x0F, reg <<4);
 	if (reg == 0x0F)
 		MMC3_syncCHR(0x1FF, 0x400);
@@ -34,36 +34,36 @@ static void sync() {
 	MMC3_syncMirror();
 }
 
-static int getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	if (reg == 0x08) {
 		return MMC3_getPRGBank(bank &1) &~3 | bank &3;
 	} else
 		return MMC3_getPRGBank(bank);
 }
 
-static int getCHRBank(uint8 bank) {
+static int getCHRBank (uint8 bank) {
 	if (reg == 0x0F)
 		return MMC3_getCHRBank(bank &6 | bank >>1 &1) <<1 | bank &1;
 	else
 		return MMC3_getCHRBank(bank);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	MMC3_power();
 }
 
-void Mapper567_Init(CartInfo *info) {
+void Mapper567_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_SHARP, getPRGBank, getCHRBank, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/569.c

@@ -25,7 +25,7 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int chrAND = reg &0x04? 0x1FF: reg &0x02? 0xFF: 0x7F;
 	int chrOR = reg <<7;
 	MMC3_syncPRG(0x0F, reg <<4 &~0x0F);
@@ -33,36 +33,36 @@ static void sync() {
 	MMC3_syncMirror();
 }
 
-static int getPRGBank(uint8 bank) {
+static int getPRGBank (uint8 bank) {
 	if (reg &0x08) {
 		return MMC3_getPRGBank(0) &~3 | bank &3;
 	} else
 		return MMC3_getPRGBank(bank);
 }
 
-static int getCHRBank(uint8 bank) {
+static int getCHRBank (uint8 bank) {
 	if (reg &0x04)
 		return MMC3_getCHRBank(bank &6 | bank >>1 &1) <<1 | bank &1;
 	else
 		return MMC3_getCHRBank(bank);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
 	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	MMC3_power();
 }
 
-void Mapper569_Init(CartInfo *info) {
+void Mapper569_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_SHARP, getPRGBank, getCHRBank, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/570.c

@@ -25,27 +25,27 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int prgAND = 0x0F;
 	int chrAND = reg &0x03? 0x0FF: 0x1FF;
-	int prgOR  = reg <<4;
-	int chrOR  = !!(reg &0x03)*0x200 | !!(reg &0x02)*0x100;
+	int prgOR = reg <<4;
+	int chrOR = !!(reg &0x03)*0x200 | !!(reg &0x02)*0x100;
 	VRC24_syncPRG(prgAND, prgOR &~prgAND);
 	VRC24_syncCHR(chrAND, chrOR &~chrAND);
 	VRC24_syncMirror();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = A &0xFF;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
-	sync();
+	VRC24_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	VRC24_power();
 	SetWriteHandler(0x5000, 0x5FFF, writeReg);

src/boards/572.c

@@ -25,34 +25,34 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int prgAND = 0x1F;
 	int chrAND = 0x7F;
-	int prgOR  = reg <<5;
-	int chrOR  = reg <<7;
+	int prgOR = reg <<5;
+	int chrOR = reg <<7;
 	MMC3_syncPRG(prgAND, prgOR &~prgAND);
 	MMC3_syncCHR(chrAND, chrOR &~chrAND);
 	MMC3_syncMirror();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (~reg &0x08) {
 		reg = A &0xFF;
 		sync();
 	}
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
-	sync();
+	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	reg = 0;
 	MMC3_power();
 }
 
-void Mapper572_Init(CartInfo *info) {
+void Mapper572_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/577.c

@@ -23,7 +23,7 @@
 
 static uint8 pad;
 
-static DECLFR(readOB) {
+static DECLFR (readOB) {
 	return X.DB;
 }
 
@@ -34,12 +34,12 @@ static void sync () {
 	setchr8(Latch_address >>1);
 }
 
-static void power() {
+static void power () {
 	pad = 0;
 	Latch_power();
 }
 
-static void reset() {
+static void reset () {
 	pad += 0x10;
 	Latch_clear();
 }

src/boards/578.c

@@ -25,7 +25,7 @@
 
 static uint8 reg;
 
-static void sync() {
+static void sync () {
 	int prgAND = reg &0x02 && reg &0x04? 0x1F: 0x0F;
 	int chrAND = reg &0x02 && reg &0x04? 0xFF: 0x7F;
 	int prgOR  = reg <<4;
@@ -35,24 +35,24 @@ static void sync() {
 	MMC3_syncMirror();
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg = V;
 	sync();
 }
 
-static void reset() {
+static void reset () {
 	reg = 0;
 	MMC3_clear();
 }
 
-static void power() {
+static void power () {
 	int i;
 	reg = 0;
 	MMC3_power();
-	for (int i = 0x8000; i < 0xFFFF; i +=4) SetWriteHandler(i |2, i |3, writeReg);
+	for (i = 0x8000; i < 0xFFFF; i +=4) SetWriteHandler(i |2, i |3, writeReg);
 }
 
-void Mapper578_Init(CartInfo *info) {
+void Mapper578_Init (CartInfo *info) {
 	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
 	info->Power = power;
 	info->Reset = reset;

src/boards/584.c

@@ -33,21 +33,21 @@ static void sync () {
 	setmirror(reg[1] &0x20? MI_V: MI_H);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	if (A &0x100) {
 		reg[A >>13 &1] = V;
 		sync();
 	}
 }
 
-static void power() {
+static void power () {
 	SetReadHandler(0x6000, 0xFFFF, CartBR);
 	SetWriteHandler(0x4020, 0x7FFF, writeReg);
 	reg[0] = reg[1] = 0;
 	sync();
 }
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	sync();
 }
 

src/boards/585.c

@@ -23,7 +23,7 @@
 
 static uint8 pad;
 
-static DECLFR(readOB) {
+static DECLFR (readOB) {
 	return X.DB;
 }
 
@@ -39,12 +39,12 @@ static void sync () {
 	setmirror(Latch_address &0x10? MI_V: MI_H);
 }
 
-static void power() {
+static void power () {
 	pad = 0;
 	Latch_power();
 }
 
-static void reset() {
+static void reset () {
 	pad += 0x20;
 	Latch_clear();
 }

src/boards/587.c

@@ -41,19 +41,19 @@ static void sync () {
 		setmirror(reg[0] &0x01? MI_H: MI_V);
 }
 
-static DECLFW(writeReg) {
+static DECLFW (writeReg) {
 	reg[reg[0] &0x80? 1: 0] = V;
 	sync();
 }
 
-static void power() {
+static void power () {
 	SetReadHandler(0x6000, 0xFFFF, CartBR);
 	SetWriteHandler(0x8000, 0xFFFF, writeReg);
 	reg[0] = reg[1] = 0;
 	sync();
 }
 
-static void stateRestore(int version) {
+static void stateRestore (int version) {
 	sync();
 }
 

src/boards/594.c

@@ -1,7 +1,7 @@
 /* FCEUmm - NES/Famicom Emulator
  *
  * Copyright notice for this file:
- *  Copyright (C) 2020
+ *  Copyright (C) 2025 NewRisingSun
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,7 +24,6 @@
 #include "asic_mmc3.h"
 #include "fifo.h"
 #include "msm6585.h"
-#include <stdio.h>
 
 static uint8 reg[4];
 static FIFO fifo;
@@ -104,7 +103,7 @@ static void mapperSound_fillBufferHigh () {
 	soundOffset = SOUNDTS;
 }
 
-static void mapperSound_setSoundOffset(int32 newSoundOffset) {
+static void mapperSound_setSoundOffset (int32 newSoundOffset) {
 	soundOffset = newSoundOffset;
 }
 
@@ -118,7 +117,7 @@ static void mapperSound_init (void) {
 	MSM6585_init(&adpcm, FSettings.soundq >=1? 1789773: FSettings.SndRate*16, serveADPCM);
 }
 
-static void close() {
+static void close () {
 	FIFO_close(&fifo);
 }
 

src/boards/asic_fme7.c

@@ -58,15 +58,15 @@ void FME7_syncMirror () {
 	setmirror(FME7_reg[12] &2? (FME7_reg[12] &1? MI_1: MI_0): FME7_reg[12] &1? MI_H: MI_V);
 }
 
-DECLFR(FME7_readWRAM) {
+DECLFR (FME7_readWRAM) {
 	return ~FME7_reg[8] &0x40 || FME7_reg[8] &0x80? CartBR(A): A >>8;
 }
 
-DECLFW(FME7_writeWRAM) {
+DECLFW (FME7_writeWRAM) {
 	if (FME7_reg[8] &0x80) CartBW(A, V);
 }
 
-DECLFW(FME7_writeReg) {
+DECLFW (FME7_writeReg) {
 	if (A &0x2000) {
 		FME7_reg[FME7_index &0xF] = V;
 		if ((FME7_index &0xF) == 13) X6502_IRQEnd(FCEU_IQEXT);
@@ -84,7 +84,7 @@ void FP_FASTAPASS(1) FME7_cpuCycle (int a) {
 	}
 }
 
-static void FME7_clear () {
+void FME7_clear () {
 	int i;
 	for (i = 0; i < 16; i++) FME7_reg[i] = 0;
 	FME7_cbSync();

src/boards/asic_fme7.h

@@ -25,10 +25,11 @@ void FME7_syncWRAM (int);
 void FME7_syncPRG (int, int);
 void FME7_syncCHR (int, int);
 void FME7_syncMirror ();
-DECLFR(FME7_readWRAM);
-DECLFW(MMC3_writeWRAM);
-DECLFW(FME7_writeReg);
+DECLFR (FME7_readWRAM);
+DECLFW (FME7_writeWRAM);
+DECLFW (FME7_writeReg);
 void FP_FASTAPASS(1) FME7_cpuCycle (int);
+void FME7_clear ();
 void FME7_activate (uint8, void (*)());
 void FME7_addExState ();
 void FME7_restore (int);

src/boards/asic_h3001.c

@@ -33,11 +33,11 @@ static uint16 H3001_count;
 static SFORMAT H3001_state[] = {
 	{ H3001_prg,    2, "H31P" },
 	{ H3001_chr,    8, "H31C" },
-	{&H3001_layout, 4, "H31L" },
-	{&H3001_nt,     4, "H31M" },
-	{&H3001_irq,    4, "H31N" },
-	{&H3001_reload, 2, "H31R" },
-	{&H3001_count,  2, "H31T" },
+	{&H3001_layout, 1, "H31L" },
+	{&H3001_nt,     1, "H31M" },
+	{&H3001_irq,    1, "H31N" },
+	{&H3001_reload, 2 | FCEUSTATE_RLSB, "H31R" },
+	{&H3001_count,  2 | FCEUSTATE_RLSB, "H31T" },
 	{ 0 }
 };
 
@@ -68,7 +68,7 @@ void H3001_syncMirror () {
 	setmirror(H3001_nt &0x40? (H3001_nt &0x80? MI_1: MI_0): H3001_nt &0x80? MI_H: MI_V);
 }
 
-DECLFW(H3001_write) {
+DECLFW (H3001_write) {
 	switch(A >>12 &7) {
 		case 0: case 2:
 			H3001_prg[A >>13 &1] = V;
@@ -114,7 +114,7 @@ void FP_FASTAPASS(1) H3001_cpuCycle (int a) {
 	}
 }
 
-static void H3001_clear () {
+void H3001_clear () {
 	int i;
 	for (i = 0; i < 2; i++) H3001_prg[i] = i;
 	for (i = 0; i < 8; i++) H3001_chr[i] = i;

src/boards/asic_h3001.h

@@ -25,6 +25,7 @@ void H3001_syncPRG (int, int);
 void H3001_syncCHR (int, int);
 void H3001_syncMirror ();
 DECLFW (H3001_write);
+void H3001_clear ();
 void H3001_activate (uint8, void (*)());
 void H3001_addExState ();
 void H3001_restore (int);

src/boards/asic_latch.c

@@ -33,7 +33,7 @@ static SFORMAT Latch_state[] = {
 	{ 0 }
 };
 
-DECLFW(Latch_write) {
+DECLFW (Latch_write) {
 	uint16 newAddress = A &0xFFFF;
 	if (Latch_cbWrite) Latch_cbWrite(&newAddress, &V, CartBR(A));
 	Latch_address = newAddress;

src/boards/asic_mmc1.c

@@ -64,14 +64,14 @@ int MMC1_getCHRBank (uint8 bank) {
 		return MMC1_reg[1] &~1 |bank;
 }
 
-DECLFR(MMC1_readWRAM) {
+DECLFR (MMC1_readWRAM) {
 	if (MMC1_type == MMC1_TYPE_MMC1A || ~MMC1_reg[3] &0x10)
 		return MMC1_cbReadWRAM? MMC1_cbReadWRAM(A): CartBR(A);
 	else
 		return A >>8;
 }
 
-DECLFW(MMC1_writeWRAM) {
+DECLFW (MMC1_writeWRAM) {
 	if (MMC1_type == MMC1_TYPE_MMC1A || ~MMC1_reg[3] &0x10) {
 		CartBW(A, V);
 		if (MMC1_cbWriteWRAM) MMC1_cbWriteWRAM(A, V);
@@ -92,11 +92,11 @@ void MMC1_syncMirror () {
 	setmirror(MMC1_reg[0] &2? (MMC1_reg[0] &1? MI_H: MI_V): (MMC1_reg[0] &1? MI_1: MI_0));
 }
 
-void FP_FASTAPASS(1) MMC1_cpuCycle(int a) {
+void FP_FASTAPASS(1) MMC1_cpuCycle (int a) {
 	while (a--) if (MMC1_filter) MMC1_filter--;
 }
 
-DECLFW(MMC1_writeReg) {
+DECLFW (MMC1_writeReg) {
 	if (V &0x80) {
 		MMC1_reg[0] |= 0x0C;
 		MMC1_shift = 0;
@@ -115,7 +115,7 @@ DECLFW(MMC1_writeReg) {
 	MMC1_filter = 2;
 }
 
-void MMC1_clear() {
+void MMC1_clear () {
 	MMC1_reg[0] = 0x0C; MMC1_reg[1] = 0; MMC1_reg[2] = 0; MMC1_reg[3] = 0; /* "Bad News Baseball" is sensitive to the initial CHR bank register content. 0/0 seems to work. */
 	MMC1_bits = 0; MMC1_shift = 0; MMC1_filter = 0;
 	MMC1_cbSync();

src/boards/asic_mmc2and4.c

@@ -65,12 +65,12 @@ static void FP_FASTAPASS(1) MMC24_trapPPUAddressChange (uint32 A) {
 	}
 }
 
-DECLFW(MMC24_write) {
+DECLFW (MMC24_write) {
 	MMC24_reg[(A >>12) -0xA] = V;
 	MMC24_cbSync();
 }
 
-static void MMC24_clear () {
+void MMC24_clear () {
 	MMC24_reg[0] = 0; MMC24_reg[1] = 0; MMC24_reg[2] = 2; MMC24_reg[3] = 0; MMC24_reg[4] = 0; MMC24_reg[5] = 0;
 	MMC24_latch[0] = 0; MMC24_latch[1] = 0;
 	MMC24_cbSync();

src/boards/asic_mmc2and4.h

@@ -27,6 +27,7 @@ void MMC4_syncPRG (int, int);
 void MMC24_syncCHR (int, int);
 void MMC24_syncMirror ();
 DECLFW (MMC24_write);
+void MMC24_clear ();
 void MMC24_power ();
 void MMC24_restore (int);
 void MMC24_addExState ();

src/boards/asic_mmc3.c

@@ -66,14 +66,14 @@ uint8 MMC3_getMirroring (void) {
 	return MMC3_mirroring;
 }
 
-DECLFR(MMC3_readWRAM) {
+DECLFR (MMC3_readWRAM) {
 	if (MMC3_wramControl &0x80 || MMC3_type == MMC3_TYPE_AX5202P || MMC3_type == MMC3_TYPE_MMC6)
 		return MMC3_cbReadWRAM? MMC3_cbReadWRAM(A): CartBR(A);
 	else
 		return A >>8;
 }
 
-DECLFW(MMC3_writeWRAM) {
+DECLFW (MMC3_writeWRAM) {
 	if ((MMC3_wramControl &0x80 || MMC3_type == MMC3_TYPE_AX5202P) && ~MMC3_wramControl &0x40 || MMC3_type == MMC3_TYPE_MMC6) {
 		CartBW(A, V);
 		if (MMC3_cbWriteWRAM) MMC3_cbWriteWRAM(A, V);

src/boards/asic_n118.c

@@ -51,7 +51,7 @@ void N118_syncCHR (int AND, int OR) {
 	for (bank = 0; bank < 8; bank++) setchr1(bank <<10, N118_cbGetCHRBank(bank) &AND |OR);
 }
 
-DECLFW(N118_writeReg) {
+DECLFW (N118_writeReg) {
 	if (A &1) {
 		N118_reg[N118_index &7] = V;
 		N118_cbSync();

src/boards/asic_pt8154.c

@@ -44,19 +44,19 @@ void PT8154_syncMirror () {
 	MMC3_syncMirror();
 }
 
-DECLFW(PT8154_writeExtra) {
+DECLFW (PT8154_writeExtra) {
 	if (A &0x100) {
 		PT8154_reg = V >>4;
 		PT8154_cbSync();
 	}
 }
 
-DECLFW(PT8154_writeWRAM) {
+DECLFW (PT8154_writeWRAM) {
 	PT8154_reg = A;
 	PT8154_cbSync();
 }
 
-static void PT8154_clear () {
+void PT8154_clear () {
 	PT8154_reg = 0;
 	PT8154_cbSync();
 }

src/boards/asic_pt8154.h

@@ -26,6 +26,7 @@ void PT8154_syncCHR (int, int);
 void PT8154_syncMirror ();
 DECLFW (PT8154_writeExtra);
 DECLFW (PT8154_writeWRAM);
+void PT8154_clear ();
 void PT8154_activate (uint8, void (*)());
 void PT8154_addExState ();
 void PT8154_restore (int);

src/boards/asic_qj.c

@@ -42,12 +42,12 @@ void QJ_syncMirror () {
 	MMC3_syncMirror();
 }
 
-DECLFW(QJ_writeWRAM) {
+DECLFW (QJ_writeWRAM) {
 	QJ_reg = V;
 	QJ_cbSync();
 }
 
-static void QJ_clear () {
+void QJ_clear () {
 	QJ_reg = 0;
 	QJ_cbSync();
 }

src/boards/asic_qj.h

@@ -26,6 +26,7 @@ void QJ_syncPRG (int, int);
 void QJ_syncCHR (int, int);
 void QJ_syncMirror ();
 DECLFW (QJ_write);
+void QJ_clear ();
 void QJ_activate (uint8, void (*)());
 void QJ_addExState ();
 void QJ_restore (int);

src/boards/asic_tc3294.c

@@ -52,14 +52,14 @@ void TC3294_syncMirror () {
 	MMC3_syncMirror();
 }
 
-DECLFW(TC3294_write) {
+DECLFW(TC3294_writeReg) {
 	if (~TC3294_reg[3] &0x40) {
 		TC3294_reg[TC3294_index++ &3] = V;
 		TC3294_cbSync();
 	}
 }
 
-static void TC3294_clear () {
+void TC3294_clear () {
 	TC3294_reg[0] = 0x00; TC3294_reg[1] = 0x00; TC3294_reg[2] = 0x0F; TC3294_reg[3] = 0x00;
 	TC3294_index = 0;
 	TC3294_cbSync();
@@ -73,7 +73,7 @@ static void TC3294_configure (void (*sync)()) {
 }
 
 void TC3294_activate (uint8 clear, void (*sync)()) {
-	MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_write);
+	MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_writeReg);
 	TC3294_configure(sync);
 	TC3294_setHandlers();
 	if (clear)
@@ -97,7 +97,7 @@ void TC3294_power () {
 }
 
 void TC3294_init (CartInfo *info, void (*sync)()) {
-	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_write);
+	MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_writeReg);
 	TC3294_addExState();
 	TC3294_configure(sync);
 	info->Power = TC3294_power;

src/boards/asic_tc3294.h

@@ -26,7 +26,8 @@ void TC3294_syncWRAM (int);
 void TC3294_syncPRG (int, int);
 void TC3294_syncCHR (int, int);
 void TC3294_syncMirror ();
-DECLFW (TC3294_write);
+DECLFW (TC3294_writeReg);
+void TC3294_clear ();
 void TC3294_activate (uint8, void (*)());
 void TC3294_addExState ();
 void TC3294_restore (int);

src/boards/asic_vrc1.c

@@ -45,19 +45,19 @@ void VRC1_syncMirror () {
 	setmirror(VRC1_reg[1] &0x01? MI_H: MI_V);
 }
 
-DECLFW(VRC1_write) {
+DECLFW (VRC1_writeReg) {
 	VRC1_reg[A >>12 &7] = V;
 	VRC1_cbSync();
 }
 
-static void VRC1_clear () {
+void VRC1_clear () {
 	VRC1_reg[0] = 0x00; VRC1_reg[1] = 0; VRC1_reg[2] = 2; VRC1_reg[3] = 0;VRC1_reg[4] = 0x00; VRC1_reg[5] = 0; VRC1_reg[6] = 2; VRC1_reg[7] = 0;
 	VRC1_cbSync();
 }
 
 static void VRC1_setHandlers () {
 	SetReadHandler (0x8000, 0xFFFF, CartBR);
-	SetWriteHandler(0x8000, 0xFFFF, VRC1_write);
+	SetWriteHandler(0x8000, 0xFFFF, VRC1_writeReg);
 }
 
 static void VRC1_configure (void (*sync)()) {

src/boards/asic_vrc1.h

@@ -24,7 +24,8 @@
 void VRC1_syncPRG (int, int);
 void VRC1_syncCHR (int, int);
 void VRC1_syncMirror ();
-DECLFW (VRC1_write);
+DECLFW (VRC1_writeReg);
+void VRC1_clear ();
 void VRC1_activate (uint8, void (*)());
 void VRC1_addExState ();
 void VRC1_restore (int);

src/boards/asic_vrc2and4.c

@@ -29,13 +29,13 @@ static int (*VRC24_cbGetCHRBank)(uint8);
 static DECLFR((*VRC24_cbReadWRAM));
 static DECLFW((*VRC24_cbWriteWRAM));
 static DECLFW((*VRC24_cbExternalSelect));
-static uint8 VRC24_isVRC4;       /* VRC2 or VRC4? VRC2 has no single-screen mirroring, no PRG A14 swap and no IRQ counter */
+static uint8 VRC24_isVRC4; /* VRC2 or VRC4? VRC2 has no single-screen mirroring, no PRG A14 swap and no IRQ counter */
 static uint8 VRC24_useRepeatBit; /* Some VRC4 clones ignore the "repeat" bit in the IRQ Mode register */
 static uint8 VRC24_prg[2];
 static uint16 VRC24_chr[8];
 static uint8 VRC24_mirroring;
 static uint8 VRC24_misc;
-uint8 VRC2_pins;                  /* EEPROM interface */
+uint8 VRC2_pins; /* EEPROM interface */
 static uint8 VRC4_latch;
 static uint8 VRC4_mode;
 static uint8 VRC4_count;
@@ -103,11 +103,11 @@ void VRC24_syncMirror () {
 	setmirror(VRC24_isVRC4 && VRC24_mirroring &2? (VRC24_mirroring &1? MI_1: MI_0): (VRC24_mirroring &1? MI_H: MI_V));
 }
 
-DECLFR(VRC2_readMicrowire) {
+DECLFR (VRC2_readMicrowire) {
 	return VRC2_pins;
 }
 
-DECLFR(VRC24_readWRAM) {
+DECLFR (VRC24_readWRAM) {
 	if (VRC24_misc &1 || !VRC24_isVRC4) {
 		if (VRC24_cbReadWRAM)
 			return VRC24_cbReadWRAM(A);
@@ -120,12 +120,12 @@ DECLFR(VRC24_readWRAM) {
 		return A >>8;
 }
 
-DECLFW(VRC2_writeMicrowire) {
+DECLFW (VRC2_writeMicrowire) {
 	VRC2_pins = V;
 	VRC24_cbSync();
 }
 
-DECLFW(VRC24_writeWRAM) {
+DECLFW (VRC24_writeWRAM) {
 	if (VRC24_misc &1 || !VRC24_isVRC4) {
 		if (WRAMSize)
 			CartBW(((A -0x6000) &(WRAMSize -1)) +0x6000, V);
@@ -134,7 +134,7 @@ DECLFW(VRC24_writeWRAM) {
 	}
 }
 
-DECLFW(VRC24_writeReg) {
+DECLFW (VRC24_writeReg) {
 	unsigned int index, addr;
 	addr = A &0xF000 | (A &VRC24_A0? 1: 0) | (A &VRC24_A1? 2: 0); /* address as the chip sees it */
 	switch (addr &0xF000) {
@@ -194,7 +194,7 @@ void FP_FASTAPASS(1) VRC4_cpuCycle (int a) {
 	}
 }
 
-static void VRC24_clear() {
+void VRC24_clear () {
 	VRC24_prg[0] = 0; VRC24_prg[1] = 0;
 	VRC24_chr[0] = 0; VRC24_chr[1] = 1; VRC24_chr[2] = 2; VRC24_chr[3] = 3; VRC24_chr[4] = 4; VRC24_chr[5] = 5; VRC24_chr[6] = 6; VRC24_chr[7] = 7;
 	VRC24_mirroring = VRC2_pins = VRC4_latch = VRC4_mode = VRC4_count = VRC4_cycles = 0;

src/boards/asic_vrc2and4.h

@@ -38,6 +38,7 @@ DECLFW(VRC24_writeReg);
 
 void FP_FASTAPASS(1) VRC4_cpuCycle(int);
 void VRC24_reconfigure (int, int);
+void VRC24_clear ();
 void VRC2_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)));
 void VRC4_activate (uint8, void (*)(), int, int, uint8, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)), DECLFW((*)));
 void VRC2_addExState ();

src/boards/asic_vrc3.c

@@ -48,7 +48,7 @@ void VRC3_syncCHR (int AND, int OR) {
 	setchr8(OR);
 }
 
-DECLFW(VRC3_write) {
+DECLFW (VRC3_write) {
 	int shift;
 	switch (A >>12 &7) {
 		case 0: case 1: case 2: case 3:
@@ -81,7 +81,7 @@ void FP_FASTAPASS(1) VRC3_cpuCycle (int a) {
 	}
 }
 
-static void VRC3_clear () {
+void VRC3_clear () {
 	VRC3_prg = VRC3_irq = VRC3_count = VRC3_reload = 0;
 	X6502_IRQEnd(FCEU_IQEXT);
 	VRC3_cbSync();

src/boards/asic_vrc3.h

@@ -25,6 +25,7 @@ void VRC3_syncWRAM (int);
 void VRC3_syncPRG (int, int);
 void VRC3_syncCHR (int, int);
 DECLFW (VRC3_write);
+void VRC3_clear ();
 void VRC3_activate (uint8, void (*)());
 void VRC3_addExState ();
 void VRC3_restore (int);

src/boards/asic_vrc6.c

@@ -83,21 +83,21 @@ int VRC6_getCHRBank (uint8 bank) { /* Only emulates features used by known games
 	return VRC6_chr[bank &7];
 }
 
-DECLFR(VRC6_readWRAM) {
+DECLFR (VRC6_readWRAM) {
 	if (VRC6_misc &0x80)
 		return VRC6_cbReadWRAM? VRC6_cbReadWRAM(A): CartBR(A);
 	else
 		return A >>8;
 }
 
-DECLFW(VRC6_writeWRAM) {
+DECLFW (VRC6_writeWRAM) {
 	if (VRC6_misc &0x80) {
 		CartBW(A, V);
 		if (VRC6_cbWriteWRAM) VRC6_cbWriteWRAM(A, V);
 	}
 }
 
-DECLFW(VRC6_writeReg) {
+DECLFW (VRC6_writeReg) {
 	unsigned int index;
 	index = (A &VRC6_A0? 1: 0) | (A &VRC6_A1? 2: 0);
 	switch (A >>12 &7) {
@@ -151,7 +151,7 @@ void FP_FASTAPASS(1) VRC6_cpuCycle (int a) {
 	}
 }
 
-static void VRC6_clear () {
+void VRC6_clear () {
 	VRC6_prg[0] = 0; VRC6_prg[1] = 0xFE;
 	VRC6_chr[0] = 0; VRC6_chr[1] = 1; VRC6_chr[2] = 2; VRC6_chr[3] = 3; VRC6_chr[4] = 4; VRC6_chr[5] = 5; VRC6_chr[6] = 6; VRC6_chr[7] = 7;
 	VRC6_misc = VRC6_latch = VRC6_mode = VRC6_count = VRC6_cycles = 0;

src/boards/asic_vrc6.h

@@ -31,6 +31,7 @@ DECLFR(VRC6_readWRAM);
 DECLFW(MMC3_writeWRAM);
 DECLFW(VRC6_writeReg);
 void FP_FASTAPASS(1) VRC6_cpuCycle (int);
+void VRC6_clear ();
 void VRC6_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)));
 void VRC6_addExState ();
 void VRC6_restore (int);

src/boards/asic_vrc7.c

@@ -68,15 +68,15 @@ void VRC7_syncMirror () {
 	setmirror(VRC7_misc &2? (VRC7_misc &1? MI_1: MI_0): VRC7_misc &1? MI_H: MI_V);
 }
 
-DECLFR(VRC7_readWRAM) {
+DECLFR (VRC7_readWRAM) {
 	return VRC7_misc &0x80? CartBR(A): A >>8;
 }
 
-DECLFW(VRC7_writeWRAM) {
+DECLFW (VRC7_writeWRAM) {
 	if (VRC7_misc &0x80) CartBW(A, V);
 }
 
-DECLFW(VRC7_writeReg) {
+DECLFW (VRC7_writeReg) {
 	unsigned int index;
 	index = A &VRC7_A0? 1: 0;
 	switch (A >>12 &7) {
@@ -128,7 +128,7 @@ void FP_FASTAPASS(1) VRC7_cpuCycle (int a) {
 	}
 }
 
-static void VRC7_clear () {
+void VRC7_clear () {
 	VRC7_prg[0] = 0; VRC7_prg[1] = 1; VRC7_prg[2] = 0xFE;
 	VRC7_chr[0] = 0; VRC7_chr[1] = 1; VRC7_chr[2] = 2; VRC7_chr[3] = 3; VRC7_chr[4] = 4; VRC7_chr[5] = 5; VRC7_chr[6] = 6; VRC7_chr[7] = 7;
 	VRC7_misc = VRC7_latch = VRC7_mode = VRC7_count = VRC7_cycles = 0;

src/boards/asic_vrc7.h

@@ -29,6 +29,7 @@ DECLFR(VRC7_readWRAM);
 DECLFW(MMC3_writeWRAM);
 DECLFW(VRC7_writeReg);
 void FP_FASTAPASS(1) VRC7_cpuCycle (int);
+void VRC7_clear ();
 void VRC7_activate (uint8, void (*)(), int);
 void VRC7_addExState ();
 void VRC7_restore (int);

src/boards/bmck3006.c

@@ -26,7 +26,7 @@
 #include "mapinc.h"
 #include "mmc3.h"
 
-static uint8 submapper; // 0: K-3006, 1: unmarked, 2: TL 8058, 3: K-3091/GN-16
+static uint8 submapper; /* 0: K-3006, 1: unmarked, 2: TL 8058, 3: K-3091/GN-16 */
 
 static DECLFR (readPad) {
 	return CartBR(A &~3 | EXPREGS[2] &3);

src/boards/cartram.c

@@ -29,37 +29,37 @@ uint32 WRAMSize = 0;
 void CartRAM_close (void) { /* Need to combine this in one function to avoid the problem of having to properly cascade two separate Close() functions for WRAM and CHR-RAM each */
 	if (WRAMData) {
 		FCEU_gfree(WRAMData);
-		WRAMData =NULL;
+		WRAMData = NULL;
 	}
 	if (CHRRAMData) {
 		FCEU_gfree(CHRRAMData);
-		CHRRAMData =NULL;
+		CHRRAMData = NULL;
 	}
 }
 
 void CartRAM_init (CartInfo *info, uint8 defaultWRAMSizeKiB, uint8 defaultCHRRAMSizeKiB) {
-	WRAMSize =info->iNES2? (info->PRGRamSize +info->PRGRamSaveSize): (defaultWRAMSizeKiB *1024);
+	WRAMSize = info->iNES2? (info->PRGRamSize +info->PRGRamSaveSize): (defaultWRAMSizeKiB *1024);
 	if (WRAMSize) {
-		WRAMData =(uint8*)FCEU_gmalloc(WRAMSize);
+		WRAMData = (uint8*)FCEU_gmalloc(WRAMSize);
 		SetupCartPRGMapping(0x10, WRAMData, WRAMSize, 1);
 		AddExState(WRAMData, WRAMSize, 0, "WRAM");
-		if (info->battery) {
-			info->SaveGame[0] =WRAMData;
-			info->SaveGameLen[0] =WRAMSize;
+		if (info->battery && (info->PRGRamSaveSize || !info->iNES2)) {
+			info->SaveGame[0] = WRAMData;
+			info->SaveGameLen[0] = info->iNES2? info->PRGRamSaveSize: WRAMSize;
 		}
 	}
-	CHRRAMSize =info->iNES2? (info->CHRRamSize +info->CHRRamSaveSize): (defaultCHRRAMSizeKiB *1024);
+	CHRRAMSize = info->iNES2? (info->CHRRamSize +info->CHRRamSaveSize): (defaultCHRRAMSizeKiB *1024);
 	if (ROM_size == 0) CHRRAMSize = 0; /* If there is no CHR-ROM, then any CHR-RAM will not be "extra" and therefore will be handled by ines.c, not here. */
 	if (CHRRAMSize) {
-		CHRRAMData =(uint8*)FCEU_gmalloc(CHRRAMSize);
+		CHRRAMData = (uint8*)FCEU_gmalloc(CHRRAMSize);
 		SetupCartCHRMapping(0x10, CHRRAMData, CHRRAMSize, 1);
 		AddExState(CHRRAMData, CHRRAMSize, 0, "CRAM");
-		if (info->battery) {
-			info->SaveGame[info->SaveGameLen[0]? 1: 0] =CHRRAMData;
-			info->SaveGameLen[info->SaveGameLen[0]? 1: 0] =CHRRAMSize;
+		if (info->battery && (info->CHRRamSaveSize || !info->iNES2)) {
+			info->SaveGame[info->SaveGameLen[0]? 1: 0] = CHRRAMData;
+			info->SaveGameLen[info->SaveGameLen[0]? 1: 0] = info->iNES2? info->CHRRamSaveSize: CHRRAMSize;
 		}
 	}
-	if (WRAMSize || CHRRAMSize) info->Close =CartRAM_close;
+	if (WRAMSize || CHRRAMSize) info->Close = CartRAM_close;
 }
 
 void CHRRAM_init (CartInfo *info, uint8 defaultCHRRAMSizeKiB) {

src/boards/fifo.c

@@ -31,8 +31,8 @@ void FIFO_init (FIFO *fifo, size_t newCapacity) {
 	fifo->capacity = newCapacity;
 	fifo->data = (uint8*)FCEU_gmalloc(newCapacity);
 	AddExState(fifo->data, fifo->capacity, 0, "FIFD");
-	AddExState(&fifo->front, 2, 0, "FIFF");
-	AddExState(&fifo->back, 2, 0, "FIFB");
+	AddExState(&fifo->front, 2 | FCEUSTATE_RLSB, 0, "FIFF");
+	AddExState(&fifo->back, 2 | FCEUSTATE_RLSB, 0, "FIFB");
 }
 
 void FIFO_close (FIFO *fifo) {

src/boards/msm6585.c

@@ -2,54 +2,54 @@
 #include "msm6585.h"
 
 static const int16_t diff_lookup[49*16] = {
-	2, 6, 10, 14, 18, 22, 26, 30, -2, -6, -10, -14, -18, -22, -26, -30, 
-	2, 6, 10, 14, 19, 23, 27, 31, -2, -6, -10, -14, -19, -23, -27, -31, 
-	2, 6, 11, 15, 21, 25, 30, 34, -2, -6, -11, -15, -21, -25, -30, -34, 
-	2, 7, 12, 17, 23, 28, 33, 38, -2, -7, -12, -17, -23, -28, -33, -38, 
-	2, 7, 13, 18, 25, 30, 36, 41, -2, -7, -13, -18, -25, -30, -36, -41, 
-	3, 9, 15, 21, 28, 34, 40, 46, -3, -9, -15, -21, -28, -34, -40, -46, 
-	3, 10, 17, 24, 31, 38, 45, 52, -3, -10, -17, -24, -31, -38, -45, -52, 
-	3, 10, 18, 25, 34, 41, 49, 56, -3, -10, -18, -25, -34, -41, -49, -56, 
-	4, 12, 21, 29, 38, 46, 55, 63, -4, -12, -21, -29, -38, -46, -55, -63, 
-	4, 13, 22, 31, 41, 50, 59, 68, -4, -13, -22, -31, -41, -50, -59, -68, 
-	5, 15, 25, 35, 46, 56, 66, 76, -5, -15, -25, -35, -46, -56, -66, -76, 
-	5, 16, 27, 38, 50, 61, 72, 83, -5, -16, -27, -38, -50, -61, -72, -83, 
-	6, 18, 31, 43, 56, 68, 81, 93, -6, -18, -31, -43, -56, -68, -81, -93, 
-	6, 19, 33, 46, 61, 74, 88, 101, -6, -19, -33, -46, -61, -74, -88, -101, 
-	7, 22, 37, 52, 67, 82, 97, 112, -7, -22, -37, -52, -67, -82, -97, -112, 
-	8, 24, 41, 57, 74, 90, 107, 123, -8, -24, -41, -57, -74, -90, -107, -123, 
-	9, 27, 45, 63, 82, 100, 118, 136, -9, -27, -45, -63, -82, -100, -118, -136, 
-	10, 30, 50, 70, 90, 110, 130, 150, -10, -30, -50, -70, -90, -110, -130, -150, 
-	11, 33, 55, 77, 99, 121, 143, 165, -11, -33, -55, -77, -99, -121, -143, -165, 
-	12, 36, 60, 84, 109, 133, 157, 181, -12, -36, -60, -84, -109, -133, -157, -181, 
-	13, 39, 66, 92, 120, 146, 173, 199, -13, -39, -66, -92, -120, -146, -173, -199, 
-	14, 43, 73, 102, 132, 161, 191, 220, -14, -43, -73, -102, -132, -161, -191, -220, 
-	16, 48, 81, 113, 146, 178, 211, 243, -16, -48, -81, -113, -146, -178, -211, -243, 
-	17, 52, 88, 123, 160, 195, 231, 266, -17, -52, -88, -123, -160, -195, -231, -266, 
-	19, 58, 97, 136, 176, 215, 254, 293, -19, -58, -97, -136, -176, -215, -254, -293, 
-	21, 64, 107, 150, 194, 237, 280, 323, -21, -64, -107, -150, -194, -237, -280, -323, 
-	23, 70, 118, 165, 213, 260, 308, 355, -23, -70, -118, -165, -213, -260, -308, -355, 
-	26, 78, 130, 182, 235, 287, 339, 391, -26, -78, -130, -182, -235, -287, -339, -391, 
-	28, 85, 143, 200, 258, 315, 373, 430, -28, -85, -143, -200, -258, -315, -373, -430, 
-	31, 94, 157, 220, 284, 347, 410, 473, -31, -94, -157, -220, -284, -347, -410, -473, 
-	34, 103, 173, 242, 313, 382, 452, 521, -34, -103, -173, -242, -313, -382, -452, -521, 
-	38, 114, 191, 267, 345, 421, 498, 574, -38, -114, -191, -267, -345, -421, -498, -574, 
-	42, 126, 210, 294, 379, 463, 547, 631, -42, -126, -210, -294, -379, -463, -547, -631, 
-	46, 138, 231, 323, 417, 509, 602, 694, -46, -138, -231, -323, -417, -509, -602, -694, 
-	51, 153, 255, 357, 459, 561, 663, 765, -51, -153, -255, -357, -459, -561, -663, -765, 
-	56, 168, 280, 392, 505, 617, 729, 841, -56, -168, -280, -392, -505, -617, -729, -841, 
-	61, 184, 308, 431, 555, 678, 802, 925, -61, -184, -308, -431, -555, -678, -802, -925, 
-	68, 204, 340, 476, 612, 748, 884, 1020, -68, -204, -340, -476, -612, -748, -884, -1020, 
-	74, 223, 373, 522, 672, 821, 971, 1120, -74, -223, -373, -522, -672, -821, -971, -1120, 
-	82, 246, 411, 575, 740, 904, 1069, 1233, -82, -246, -411, -575, -740, -904, -1069, -1233, 
-	90, 271, 452, 633, 814, 995, 1176, 1357, -90, -271, -452, -633, -814, -995, -1176, -1357, 
-	99, 298, 497, 696, 895, 1094, 1293, 1492, -99, -298, -497, -696, -895, -1094, -1293, -1492, 
-	109, 328, 547, 766, 985, 1204, 1423, 1642, -109, -328, -547, -766, -985, -1204, -1423, -1642, 
-	120, 360, 601, 841, 1083, 1323, 1564, 1804, -120, -360, -601, -841, -1083, -1323, -1564, -1804, 
-	132, 397, 662, 927, 1192, 1457, 1722, 1987, -132, -397, -662, -927, -1192, -1457, -1722, -1987, 
-	145, 436, 728, 1019, 1311, 1602, 1894, 2185, -145, -436, -728, -1019, -1311, -1602, -1894, -2185, 
-	160, 480, 801, 1121, 1442, 1762, 2083, 2403, -160, -480, -801, -1121, -1442, -1762, -2083, -2403, 
-	176, 528, 881, 1233, 1587, 1939, 2292, 2644, -176, -528, -881, -1233, -1587, -1939, -2292, -2644, 
+	2, 6, 10, 14, 18, 22, 26, 30, -2, -6, -10, -14, -18, -22, -26, -30,
+	2, 6, 10, 14, 19, 23, 27, 31, -2, -6, -10, -14, -19, -23, -27, -31,
+	2, 6, 11, 15, 21, 25, 30, 34, -2, -6, -11, -15, -21, -25, -30, -34,
+	2, 7, 12, 17, 23, 28, 33, 38, -2, -7, -12, -17, -23, -28, -33, -38,
+	2, 7, 13, 18, 25, 30, 36, 41, -2, -7, -13, -18, -25, -30, -36, -41,
+	3, 9, 15, 21, 28, 34, 40, 46, -3, -9, -15, -21, -28, -34, -40, -46,
+	3, 10, 17, 24, 31, 38, 45, 52, -3, -10, -17, -24, -31, -38, -45, -52,
+	3, 10, 18, 25, 34, 41, 49, 56, -3, -10, -18, -25, -34, -41, -49, -56,
+	4, 12, 21, 29, 38, 46, 55, 63, -4, -12, -21, -29, -38, -46, -55, -63,
+	4, 13, 22, 31, 41, 50, 59, 68, -4, -13, -22, -31, -41, -50, -59, -68,
+	5, 15, 25, 35, 46, 56, 66, 76, -5, -15, -25, -35, -46, -56, -66, -76,
+	5, 16, 27, 38, 50, 61, 72, 83, -5, -16, -27, -38, -50, -61, -72, -83,
+	6, 18, 31, 43, 56, 68, 81, 93, -6, -18, -31, -43, -56, -68, -81, -93,
+	6, 19, 33, 46, 61, 74, 88, 101, -6, -19, -33, -46, -61, -74, -88, -101,
+	7, 22, 37, 52, 67, 82, 97, 112, -7, -22, -37, -52, -67, -82, -97, -112,
+	8, 24, 41, 57, 74, 90, 107, 123, -8, -24, -41, -57, -74, -90, -107, -123,
+	9, 27, 45, 63, 82, 100, 118, 136, -9, -27, -45, -63, -82, -100, -118, -136,
+	10, 30, 50, 70, 90, 110, 130, 150, -10, -30, -50, -70, -90, -110, -130, -150,
+	11, 33, 55, 77, 99, 121, 143, 165, -11, -33, -55, -77, -99, -121, -143, -165,
+	12, 36, 60, 84, 109, 133, 157, 181, -12, -36, -60, -84, -109, -133, -157, -181,
+	13, 39, 66, 92, 120, 146, 173, 199, -13, -39, -66, -92, -120, -146, -173, -199,
+	14, 43, 73, 102, 132, 161, 191, 220, -14, -43, -73, -102, -132, -161, -191, -220,
+	16, 48, 81, 113, 146, 178, 211, 243, -16, -48, -81, -113, -146, -178, -211, -243,
+	17, 52, 88, 123, 160, 195, 231, 266, -17, -52, -88, -123, -160, -195, -231, -266,
+	19, 58, 97, 136, 176, 215, 254, 293, -19, -58, -97, -136, -176, -215, -254, -293,
+	21, 64, 107, 150, 194, 237, 280, 323, -21, -64, -107, -150, -194, -237, -280, -323,
+	23, 70, 118, 165, 213, 260, 308, 355, -23, -70, -118, -165, -213, -260, -308, -355,
+	26, 78, 130, 182, 235, 287, 339, 391, -26, -78, -130, -182, -235, -287, -339, -391,
+	28, 85, 143, 200, 258, 315, 373, 430, -28, -85, -143, -200, -258, -315, -373, -430,
+	31, 94, 157, 220, 284, 347, 410, 473, -31, -94, -157, -220, -284, -347, -410, -473,
+	34, 103, 173, 242, 313, 382, 452, 521, -34, -103, -173, -242, -313, -382, -452, -521,
+	38, 114, 191, 267, 345, 421, 498, 574, -38, -114, -191, -267, -345, -421, -498, -574,
+	42, 126, 210, 294, 379, 463, 547, 631, -42, -126, -210, -294, -379, -463, -547, -631,
+	46, 138, 231, 323, 417, 509, 602, 694, -46, -138, -231, -323, -417, -509, -602, -694,
+	51, 153, 255, 357, 459, 561, 663, 765, -51, -153, -255, -357, -459, -561, -663, -765,
+	56, 168, 280, 392, 505, 617, 729, 841, -56, -168, -280, -392, -505, -617, -729, -841,
+	61, 184, 308, 431, 555, 678, 802, 925, -61, -184, -308, -431, -555, -678, -802, -925,
+	68, 204, 340, 476, 612, 748, 884, 1020, -68, -204, -340, -476, -612, -748, -884, -1020,
+	74, 223, 373, 522, 672, 821, 971, 1120, -74, -223, -373, -522, -672, -821, -971, -1120,
+	82, 246, 411, 575, 740, 904, 1069, 1233, -82, -246, -411, -575, -740, -904, -1069, -1233,
+	90, 271, 452, 633, 814, 995, 1176, 1357, -90, -271, -452, -633, -814, -995, -1176, -1357,
+	99, 298, 497, 696, 895, 1094, 1293, 1492, -99, -298, -497, -696, -895, -1094, -1293, -1492,
+	109, 328, 547, 766, 985, 1204, 1423, 1642, -109, -328, -547, -766, -985, -1204, -1423, -1642,
+	120, 360, 601, 841, 1083, 1323, 1564, 1804, -120, -360, -601, -841, -1083, -1323, -1564, -1804,
+	132, 397, 662, 927, 1192, 1457, 1722, 1987, -132, -397, -662, -927, -1192, -1457, -1722, -1987,
+	145, 436, 728, 1019, 1311, 1602, 1894, 2185, -145, -436, -728, -1019, -1311, -1602, -1894, -2185,
+	160, 480, 801, 1121, 1442, 1762, 2083, 2403, -160, -480, -801, -1121, -1442, -1762, -2083, -2403,
+	176, 528, 881, 1233, 1587, 1939, 2292, 2644, -176, -528, -881, -1233, -1587, -1939, -2292, -2644,
 	194, 582, 970, 1358, 1746, 2134, 2522, 2910, -194, -582, -970, -1358, -1746, -2134, -2522, -2910
 };
 static const int16_t index_shift[8] = { -1, -1, -1, -1, 2, 4, 6, 8 };
@@ -59,16 +59,16 @@ void MSM6585_init (MSM6585* chip, int32 newHostClock, int (*newGetInput)(void))
 	chip->getInput = newGetInput;
 	AddExState(&chip->whichNibble, 1, 0, "MSMW");
 	AddExState(&chip->input, 1, 0, "MSMI");
-	AddExState(&chip->signal, 2, 0, "MSMO");
-	AddExState(&chip->count, 4, 0, "MSMC");
-	AddExState(&chip->rate, 4, 0, "MSMR");
-	AddExState(&chip->step, 2, 0, "MSMS");
+	AddExState(&chip->signal, 2 | FCEUSTATE_RLSB, 0, "MSMO");
+	AddExState(&chip->count, 4 | FCEUSTATE_RLSB, 0, "MSMC");
+	AddExState(&chip->rate, 4 | FCEUSTATE_RLSB, 0, "MSMR");
+	AddExState(&chip->step, 2 | FCEUSTATE_RLSB, 0, "MSMS");
 }
 
 void MSM6585_reset (MSM6585* chip) {
 	chip->count = 0;
 	chip->step = 0;
-	chip->signal = -2;	
+	chip->signal = -2;
 }
 
 void MSM6585_setRate (MSM6585* chip, uint8 rateByte) {
@@ -78,8 +78,8 @@ void MSM6585_setRate (MSM6585* chip, uint8 rateByte) {
 void MSM6585_run (MSM6585* chip) {
 	chip->count += chip->rate;
 	while (chip->count >= chip->hostClock) {
+		uint8_t nibble;
 		chip->count -= chip->hostClock;
-		uint8_t nibble;		
 		if (chip->whichNibble)
 			nibble = chip->input &0x0F;
 		else {
@@ -92,7 +92,7 @@ void MSM6585_run (MSM6585* chip) {
 		if (chip->signal <-2048) chip->signal =-2048;
 		chip->step += index_shift[nibble &7];
 		if (chip->step > 48) chip->step = 48;
-		if (chip->step <  0) chip->step =  0;	
+		if (chip->step <  0) chip->step =  0;
 	}
 }