More C89 build fixes - for loop initial declarations
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twinaphex
@@ -68,61 +68,81 @@ static SFORMAT JYASIC_stateRegs[] = {
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{ 0 }
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};
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static uint8 rev (uint8_t val) {
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static uint8 rev (uint8_t val)
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{
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return ((val <<6) &0x40) | ((val <<4) &0x20) | ((val <<2) &0x10) | (val &0x08) | ((val >>2) &0x04) | ((val >>4) &0x02) | ((val >>6) &0x01);
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}
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static void syncPRG (int AND, int OR) {
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static void syncPRG (int AND, int OR)
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{
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uint8_t prgLast =mode[0] &0x04? prg[3]: 0xFF;
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uint8_t prg6000 =0;
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switch (mode[0] &0x03) {
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case 0: setprg32(0x8000, prgLast &AND >>2 |OR >>2);
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prg6000 =prg[3] <<2 |3;
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break;
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case 1: setprg16(0x8000, prg[1] &AND >>1 |OR >>1);
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setprg16(0xC000, prgLast &AND >>1 |OR >>1);
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prg6000 =prg[3] <<1 |1;
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break;
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case 2: setprg8(0x8000, prg[0] &AND |OR);
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setprg8(0xA000, prg[1] &AND |OR);
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setprg8(0xC000, prg[2] &AND |OR);
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setprg8(0xE000, prgLast &AND |OR);
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prg6000 =prg[3];
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break;
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case 3: setprg8(0x8000, rev(prg[0]) &AND |OR);
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setprg8(0xA000, rev(prg[1]) &AND |OR);
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setprg8(0xC000, rev(prg[2]) &AND |OR);
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setprg8(0xE000, rev( prgLast) &AND |OR);
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prg6000 =rev(prg[3]);
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break;
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}
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switch (mode[0] &0x03)
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{
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case 0:
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setprg32(0x8000, prgLast &AND >>2 |OR >>2);
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prg6000 =prg[3] <<2 |3;
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break;
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case 1:
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setprg16(0x8000, prg[1] &AND >>1 |OR >>1);
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setprg16(0xC000, prgLast &AND >>1 |OR >>1);
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prg6000 =prg[3] <<1 |1;
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break;
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case 2:
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setprg8(0x8000, prg[0] &AND |OR);
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setprg8(0xA000, prg[1] &AND |OR);
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setprg8(0xC000, prg[2] &AND |OR);
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setprg8(0xE000, prgLast &AND |OR);
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prg6000 =prg[3];
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break;
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case 3:
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setprg8(0x8000, rev(prg[0]) &AND |OR);
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setprg8(0xA000, rev(prg[1]) &AND |OR);
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setprg8(0xC000, rev(prg[2]) &AND |OR);
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setprg8(0xE000, rev( prgLast) &AND |OR);
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prg6000 =rev(prg[3]);
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break;
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}
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if (mode[0] &0x80) /* Map ROM */
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setprg8 (0x6000, prg6000 &AND |OR);
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else
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if (WRAMSIZE) /* Otherwise map WRAM if it exists */
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setprg8r(0x10, 0x6000, 0);
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if (WRAMSIZE) /* Otherwise map WRAM if it exists */
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setprg8r(0x10, 0x6000, 0);
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}
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static void syncCHR (int AND, int OR)
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{
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08) /* MMC4 mode[0] with 4 KiB CHR mode[0] */
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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/* MMC4 mode[0] with 4 KiB CHR mode[0] */
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08)
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{
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int chrBank;
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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}
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else
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switch(mode[0] &0x18) {
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{
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int chrBank;
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switch(mode[0] &0x18)
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{
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case 0x00: /* 8 KiB CHR mode[0] */
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setchr8(chr[0] &AND >>3 | OR >>3);
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break;
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case 0x08: /* 4 KiB CHR mode[0] */
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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break;
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case 0x10:
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for (int chrBank =0; chrBank <8; chrBank +=2) setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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for (chrBank =0; chrBank <8; chrBank +=2)
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setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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break;
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case 0x18:
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for (int chrBank =0; chrBank <8; chrBank +=1) setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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for (chrBank =0; chrBank <8; chrBank +=1)
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setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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break;
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}
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PPUCHRRAM =mode[2] &0x40? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
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}
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PPUCHRRAM = (mode[2] & 0x40) ? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
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}
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static void syncNT (int AND, int OR)
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@@ -133,13 +153,17 @@ static void syncNT (int AND, int OR)
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/* First, set normal CIRAM pages using extended registers ... */
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setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
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if (mode[0] &0x20) for (int ntBank =0; ntBank <4; ntBank++)
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if (mode[0] &0x20)
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{
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/* Then replace with ROM nametables if such are generally enabled */
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
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/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
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if (vromHere)
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setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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int ntBank;
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for (ntBank =0; ntBank <4; ntBank++)
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{
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/* Then replace with ROM nametables if such are generally enabled */
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
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/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
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if (vromHere)
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setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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}
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}
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}
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else
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@@ -161,18 +185,23 @@ static void syncNT (int AND, int OR)
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}
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}
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static void clockIRQ (void) {
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static void clockIRQ (void)
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{
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uint8_t mask =irqControl &0x04? 0x07: 0xFF;
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if (irqEnabled) switch (irqControl &0xC0) {
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case 0x40:
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irqPrescaler =(irqPrescaler &~mask) | (++irqPrescaler &mask);
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if ((irqPrescaler &mask) ==0x00 && (irqControl &0x08? irqCounter: ++irqCounter) ==0x00) X6502_IRQBegin(FCEU_IQEXT);
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break;
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case 0x80:
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irqPrescaler =(irqPrescaler &~mask) | (--irqPrescaler &mask);
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if ((irqPrescaler &mask) ==mask && (irqControl &0x08? irqCounter: --irqCounter) ==0xFF) X6502_IRQBegin(FCEU_IQEXT);
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break;
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}
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if (irqEnabled)
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switch (irqControl &0xC0)
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{
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case 0x40:
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irqPrescaler =(irqPrescaler &~mask) | (++irqPrescaler &mask);
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if ((irqPrescaler &mask) ==0x00 && (irqControl &0x08? irqCounter: ++irqCounter) ==0x00)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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case 0x80:
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irqPrescaler =(irqPrescaler &~mask) | (--irqPrescaler &mask);
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if ((irqPrescaler &mask) ==mask && (irqControl &0x08? irqCounter: --irqCounter) ==0xFF)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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}
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}
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static DECLFW(trapCPUWrite)
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@@ -258,22 +287,26 @@ static DECLFW(writeALU)
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}
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}
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static DECLFW(writePRG) {
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static DECLFW(writePRG)
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{
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prg[A &3] = V;
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sync();
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}
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static DECLFW(writeCHRLow) {
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static DECLFW(writeCHRLow)
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{
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chr[A &7] =chr[A &7] &0xFF00 | V;
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sync();
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}
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static DECLFW(writeCHRHigh) {
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static DECLFW(writeCHRHigh)
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{
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chr[A &7] =chr[A &7] &0x00FF | V <<8;
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sync();
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}
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static DECLFW(writeNT) {
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static DECLFW(writeNT)
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{
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if (~A &4)
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nt[A &3] =nt[A &3] &0xFF00 | V;
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else
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