Mapper 116: use the modularized ASIC cores.
This commit is contained in:
NewRisingSun
416
src/boards/116.c
416
src/boards/116.c
@@ -1,7 +1,7 @@
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2011 CaH4e3
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* Copyright (C) 2023
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -16,353 +16,113 @@
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* SL12 Protected 3-in-1 mapper hardware (VRC2, MMC3, MMC1)
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* the same as 603-5052 board (TODO: add reading registers, merge)
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* SL1632 2-in-1 protected board, similar to SL12 (TODO: find difference)
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*
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* Known PCB:
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*
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* Garou Densetsu Special (G0904.PCB, Huang-1, GAL dip: W conf.)
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* Kart Fighter (008, Huang-1, GAL dip: W conf.)
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* Somari (008, C5052-13, GAL dip: P conf., GK2-P/GK2-V maskroms)
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* Somari (008, Huang-1, GAL dip: W conf., GK1-P/GK1-V maskroms)
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* AV Mei Shao Nv Zhan Shi (aka AV Pretty Girl Fighting) (SL-12 PCB, Hunag-1, GAL dip: unk conf. SL-11A/SL-11B maskroms)
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* Samurai Spirits (Full version) (Huang-1, GAL dip: unk conf. GS-2A/GS-4A maskroms)
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* Contra Fighter (603-5052 PCB, C5052-3, GAL dip: unk conf. SC603-A/SCB603-B maskroms)
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*
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*/
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/* NES 2.0 Mapper 556
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* Used for the for the 餓狼傳說 激鬥篇 HiK 7-in-1 (JY-215) multicart.
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*/
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#include "mapinc.h"
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#include "asic_mmc1.h"
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#include "asic_mmc3.h"
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#include "asic_vrc2and4.h"
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static uint8 vrc2_chr[8] = { 0 };
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static uint8 vrc2_prg[2] = { 0 };
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static uint8 vrc2_mirr = 0;
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static uint8 submapper;
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static uint8 reg;
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static uint8 init;
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static uint8 mmc3_regs[10] = { 0 };
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static uint8 mmc3_ctrl = 0;
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static uint8 mmc3_mirr = 0;
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static uint8 mmc1_regs[4] = { 0 };
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static uint8 mmc1_buffer = 0;
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static uint8 mmc1_shift = 0;
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static uint8 IRQCount = 0;
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static uint8 IRQLatch = 0;
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static uint8 IRQa = 0;
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static uint8 IRQReload = 0;
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static uint8 mode = 0;
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static uint8 submapper = 0;
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static uint8 game = 0;
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extern uint32 ROM_size;
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extern uint32 VROM_size;
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static SFORMAT StateRegs[] =
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{
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{ &mode, 1, "MODE" },
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{ vrc2_chr, 8, "VRCC" },
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{ vrc2_prg, 2, "VRCP" },
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{ &vrc2_mirr, 1, "VRCM" },
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{ mmc3_regs, 10, "M3RG" },
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{ &mmc3_ctrl, 1, "M3CT" },
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{ &mmc3_mirr, 1, "M3MR" },
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{ &IRQReload, 1, "IRQR" },
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{ &IRQCount, 1, "IRQC" },
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{ &IRQLatch, 1, "IRQL" },
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{ &IRQa, 1, "IRQA" },
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{ mmc1_regs, 4, "M1RG" },
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{ &mmc1_buffer, 1, "M1BF" },
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{ &mmc1_shift, 1, "M1MR" },
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{ &submapper, 1, "SUBM" },
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{ &game, 1, "GAME" },
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{ 0 }
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static SFORMAT StateRegs[] = {
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{ ®, 1, "MODE" },
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{ &init, 1, "INIT" },
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{ 0 },
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};
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static void SyncPRG(void) {
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uint8 mask = (submapper != 3) ? 0x3F : (game ? 0x0F : 0x1F);
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uint8 outer = game ? (game + 1) * 0x10 : 0;
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switch (mode & 3) {
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case 0:
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setprg8(0x8000, (outer & ~mask) | (vrc2_prg[0] & mask));
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setprg8(0xA000, (outer & ~mask) | (vrc2_prg[1] & mask));
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setprg8(0xC000, (outer & ~mask) | (~1 & mask));
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setprg8(0xE000, (outer & ~mask) | (~0 & mask));
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break;
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case 1:
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{
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uint32 swap = (mmc3_ctrl >> 5) & 2;
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setprg8(0x8000, (outer & ~mask) | (mmc3_regs[6 + swap] & mask));
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setprg8(0xA000, (outer & ~mask) | (mmc3_regs[7] & mask));
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setprg8(0xC000, (outer & ~mask) | (mmc3_regs[6 + (swap ^ 2)] & mask));
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setprg8(0xE000, (outer & ~mask) | (mmc3_regs[9] & mask));
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break;
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}
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case 2:
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case 3:
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{
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uint8 bank = mmc1_regs[3] & mask;
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if (mmc1_regs[0] & 8) {
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if (submapper == 2)
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bank >>= 1;
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if (mmc1_regs[0] & 4) {
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setprg16(0x8000, bank);
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setprg16(0xC000, 0x0F);
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} else {
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setprg16(0x8000, 0);
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setprg16(0xC000, bank);
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}
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} else
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setprg32(0x8000, ((outer & ~mask) >> 1) | (bank >> 1));
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}
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break;
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static void sync (void) {
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int prgAND = 0x3F;
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int chrAND = 0xFF;
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int prgOR = 0x00 &~prgAND;
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int chrOR = reg <<6 &0x100 &~chrAND;
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if (reg &0x02) {
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prgAND >>= 1;
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prgOR >>= 1;
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chrAND >>= 2;
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chrOR >>= 2;
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MMC1_syncPRG(prgAND, prgOR);
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MMC1_syncCHR(chrAND, chrOR);
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MMC1_syncMirror();
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} else
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if (reg &0x01) {
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MMC3_syncPRG(prgAND, prgOR);
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MMC3_syncCHR(chrAND, chrOR);
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MMC3_syncMirror();
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} else {
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VRC24_syncPRG(prgAND, prgOR);
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VRC24_syncCHR(chrAND, chrOR);
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VRC24_syncMirror();
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}
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}
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static void SyncCHR(void) {
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uint32 mask = game ? 0x7F : 0xFF;
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uint32 outer = game ? (game + 1) * 0x80 : 0;
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uint32 base = (mode & 4) << 6;
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switch (mode & 3) {
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case 0:
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setchr1(0x0000, ((outer | base) & ~mask) | (vrc2_chr[0] & mask));
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setchr1(0x0400, ((outer | base) & ~mask) | (vrc2_chr[1] & mask));
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setchr1(0x0800, ((outer | base) & ~mask) | (vrc2_chr[2] & mask));
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setchr1(0x0c00, ((outer | base) & ~mask) | (vrc2_chr[3] & mask));
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setchr1(0x1000, ((outer | base) & ~mask) | (vrc2_chr[4] & mask));
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setchr1(0x1400, ((outer | base) & ~mask) | (vrc2_chr[5] & mask));
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setchr1(0x1800, ((outer | base) & ~mask) | (vrc2_chr[6] & mask));
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setchr1(0x1c00, ((outer | base) & ~mask) | (vrc2_chr[7] & mask));
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break;
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case 1: {
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uint32 swap = (mmc3_ctrl & 0x80) << 5;
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setchr1(0x0000 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[0] & 0xFE) & mask));
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setchr1(0x0400 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[0] | 1) & mask));
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setchr1(0x0800 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[1] & 0xFE) & mask));
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setchr1(0x0c00 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[1] | 1) & mask));
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setchr1(0x1000 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[2] & mask));
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setchr1(0x1400 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[3] & mask));
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setchr1(0x1800 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[4] & mask));
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setchr1(0x1c00 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[5] & mask));
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break;
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}
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case 2:
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case 3:
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if (mmc1_regs[0] & 0x10) {
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setchr4(0x0000, (outer & ~mask) | (mmc1_regs[1] & mask));
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setchr4(0x1000, (outer & ~mask) | (mmc1_regs[2] & mask));
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} else
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setchr8(((outer & ~mask) >> 1) | (mmc1_regs[1] & mask) >> 1);
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break;
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}
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int Huang2_getPRGBank (uint8 bank) {
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return MMC1_getPRGBank(bank) >>1;
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}
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static void SyncMIR(void) {
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switch (mode & 3) {
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case 0: {
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setmirror((vrc2_mirr & 1) ^ 1);
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break;
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}
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case 1: {
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setmirror((mmc3_mirr & 1) ^ 1);
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break;
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}
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case 2:
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case 3: {
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switch (mmc1_regs[0] & 3) {
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case 0: setmirror(MI_0); break;
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case 1: setmirror(MI_1); break;
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case 2: setmirror(MI_V); break;
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case 3: setmirror(MI_H); break;
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}
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break;
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}
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}
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}
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static void Sync(void) {
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SyncPRG();
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SyncCHR();
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SyncMIR();
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}
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static DECLFW(UNLSL12ModeWrite) {
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if (A & 0x100) {
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mode = V;
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if (A & 1) { /* hacky hacky, there are two configuration modes on SOMARI HUANG-1 PCBs
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* Solder pads with P1/P2 shorted called SOMARI P,
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* Solder pads with W1/W2 shorted called SOMARI W
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* Both identical 3-in-1 but W wanted MMC1 registers
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* to be reset when switch to MMC1 mode P one - doesn't
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* There is issue with W version of Somari at starting copyrights
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*/
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mmc1_regs[0] = 0xc;
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mmc1_regs[3] = 0;
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mmc1_buffer = 0;
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mmc1_shift = 0;
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}
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Sync();
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}
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}
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static DECLFW(UNLSL12Write) {
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/* FCEU_printf("%04X:%02X\n",A,V); */
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switch (mode & 3) {
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case 0: {
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if ((A >= 0xB000) && (A <= 0xE003)) {
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int32 ind = ((((A & 2) | (A >> 10)) >> 1) + 2) & 7;
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int32 sar = ((A & 1) << 2);
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vrc2_chr[ind] = (vrc2_chr[ind] & (0xF0 >> sar)) | ((V & 0x0F) << sar);
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SyncCHR();
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} else
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switch (A & 0xF000) {
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case 0x8000: vrc2_prg[0] = V; SyncPRG(); break;
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case 0xA000: vrc2_prg[1] = V; SyncPRG(); break;
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case 0x9000: vrc2_mirr = V; SyncMIR(); break;
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}
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break;
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}
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case 1: {
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switch (A & 0xE001) {
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case 0x8000: {
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uint8 old_ctrl = mmc3_ctrl;
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mmc3_ctrl = V;
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if ((old_ctrl & 0x40) != (mmc3_ctrl & 0x40))
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SyncPRG();
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if ((old_ctrl & 0x80) != (mmc3_ctrl & 0x80))
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SyncCHR();
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break;
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}
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case 0x8001:
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mmc3_regs[mmc3_ctrl & 7] = V;
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if ((mmc3_ctrl & 7) < 6)
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SyncCHR();
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else
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SyncPRG();
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break;
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case 0xA000:
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mmc3_mirr = V;
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SyncMIR();
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break;
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case 0xC000:
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IRQLatch = V;
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break;
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case 0xC001:
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IRQReload = 1;
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break;
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case 0xE000:
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X6502_IRQEnd(FCEU_IQEXT);
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IRQa = 0;
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break;
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case 0xE001:
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IRQa = 1;
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break;
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}
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break;
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}
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case 2:
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case 3: {
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if (V & 0x80) {
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mmc1_regs[0] |= 0xc;
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mmc1_buffer = mmc1_shift = 0;
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SyncPRG();
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} else {
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uint8 n = (A >> 13) - 4;
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mmc1_buffer |= (V & 1) << (mmc1_shift++);
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if (mmc1_shift == 5) {
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mmc1_regs[n] = mmc1_buffer;
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mmc1_buffer = mmc1_shift = 0;
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switch (n) {
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case 0: SyncMIR(); break;
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case 2: SyncCHR(); break;
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case 3:
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case 1: SyncPRG(); break;
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}
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}
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}
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break;
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}
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}
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}
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static void UNLSL12HBIRQ(void) {
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if ((mode & 3) == 1) {
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int32 count = IRQCount;
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if (!count || IRQReload) {
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IRQCount = IRQLatch;
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IRQReload = 0;
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} else
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IRQCount--;
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if (!IRQCount) {
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if (IRQa)
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X6502_IRQBegin(FCEU_IQEXT);
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static void applyMode (uint8 clear) {
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if (reg &0x02) {
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MMC1_activate(clear && init &1, sync, MMC1_TYPE_MMC1B, submapper == 2? Huang2_getPRGBank: NULL, NULL, NULL, NULL);
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MMC1_writeReg(0x8000, 0x80);
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init &= ~1;
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} else
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if (reg &0x01) {
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MMC3_activate(clear && init &2, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, NULL);
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init &= ~2;
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} else {
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VRC2_activate(clear && init &4, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
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if (init &4) {
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VRC24_writeReg(0xB000, 0xFF); VRC24_writeReg(0xB001, 0xFF); VRC24_writeReg(0xB002, 0xFF); VRC24_writeReg(0xB003, 0xFF);
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VRC24_writeReg(0xC000, 0xFF); VRC24_writeReg(0xC001, 0xFF); VRC24_writeReg(0xC002, 0xFF); VRC24_writeReg(0xC003, 0xFF);
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VRC24_writeReg(0xD000, 0xFF); VRC24_writeReg(0xD001, 0xFF); VRC24_writeReg(0xD002, 0xFF); VRC24_writeReg(0xD003, 0xFF);
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VRC24_writeReg(0xE000, 0xFF); VRC24_writeReg(0xE001, 0xFF); VRC24_writeReg(0xE002, 0xFF); VRC24_writeReg(0xE003, 0xFF);
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init &= ~4;
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}
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}
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}
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static void StateRestore(int version) {
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Sync();
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}
|
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|
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static void UNLSL12Reset(void) {
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/* this is suppose to increment during power cycle */
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/* but we dont have a way to do that, so increment on reset instead. */
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if (submapper == 3) {
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game = game + 1;
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if (game > 4)
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game = 0;
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static DECLFW(writeReg) {
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if (A &0x100) {
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uint8 previousReg = reg;
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reg = V;
|
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if ((previousReg ^V) &3)
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applyMode(1);
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else
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sync();
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}
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Sync();
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}
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static void UNLSL12Power(void) {
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game = (submapper == 3) ? 4 : 0;
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mode = 1;
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vrc2_chr[0] = ~0;
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vrc2_chr[1] = ~0;
|
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vrc2_chr[2] = ~0;
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vrc2_chr[3] = ~0; /* W conf. of Somari wanted CHR3 has to be set to BB bank (or similar), but doesn't do that directly */
|
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vrc2_chr[4] = 4;
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vrc2_chr[5] = 5;
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vrc2_chr[6] = 6;
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vrc2_chr[7] = 7;
|
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vrc2_prg[0] = 0;
|
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vrc2_prg[1] = 1;
|
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vrc2_mirr = 0;
|
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mmc3_regs[0] = 0;
|
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mmc3_regs[1] = 2;
|
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mmc3_regs[2] = 4;
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mmc3_regs[3] = 5;
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mmc3_regs[4] = 6;
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mmc3_regs[5] = 7;
|
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mmc3_regs[6] = ~3;
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mmc3_regs[7] = ~2;
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mmc3_regs[8] = ~1;
|
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mmc3_regs[9] = ~0;
|
||||
mmc3_ctrl = mmc3_mirr = IRQCount = IRQLatch = IRQa = 0;
|
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mmc1_regs[0] = 0xc;
|
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mmc1_regs[1] = 0;
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mmc1_regs[2] = 0;
|
||||
mmc1_regs[3] = 0;
|
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mmc1_buffer = 0;
|
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mmc1_shift = 0;
|
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Sync();
|
||||
static void reset (void) {
|
||||
reg = 0;
|
||||
init = 7;
|
||||
applyMode(1);
|
||||
}
|
||||
|
||||
static void power (void) {
|
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reg = 0;
|
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init = 7;
|
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SetReadHandler(0x8000, 0xFFFF, CartBR);
|
||||
SetWriteHandler(0x4100, 0x5FFF, UNLSL12ModeWrite);
|
||||
SetWriteHandler(0x8000, 0xFFFF, UNLSL12Write);
|
||||
SetWriteHandler(0x4020, 0x5FFF, writeReg);
|
||||
applyMode(1);
|
||||
}
|
||||
|
||||
void UNLSL12_Init(CartInfo *info) {
|
||||
info->Power = UNLSL12Power;
|
||||
info->Reset = UNLSL12Reset;
|
||||
GameHBIRQHook = UNLSL12HBIRQ;
|
||||
GameStateRestore = StateRestore;
|
||||
AddExState(&StateRegs, ~0, 0, 0);
|
||||
submapper = info->submapper;
|
||||
if (submapper == 0) {
|
||||
/* PRG 128K and CHR 128K is Huang-2 (submapper 2) */
|
||||
if (ROM_size == 8 && VROM_size == 16)
|
||||
submapper = 2;
|
||||
}
|
||||
static void restore (int version) {
|
||||
applyMode(0);
|
||||
}
|
||||
|
||||
void UNLSL12_Init (CartInfo *info) {
|
||||
submapper = info->submapper;
|
||||
MMC1_addExState();
|
||||
MMC3_addExState();
|
||||
VRC24_addExState();
|
||||
info->Reset = reset;
|
||||
info->Power = power;
|
||||
GameStateRestore = restore;
|
||||
AddExState(StateRegs, ~0, 0, 0);
|
||||
}
|
||||
|
||||
@@ -96,7 +96,7 @@ void FP_FASTAPASS(1) MMC1_cpuCycle(int a) {
|
||||
while (a--) if (MMC1_filter) MMC1_filter--;
|
||||
}
|
||||
|
||||
DECLFW(MMC1_write) {
|
||||
DECLFW(MMC1_writeReg) {
|
||||
if (V &0x80) {
|
||||
MMC1_reg[0] |= 0x0C;
|
||||
MMC1_shift = 0;
|
||||
@@ -125,7 +125,7 @@ static void MMC1_setHandlers () {
|
||||
SetReadHandler (0x6000, 0x7FFF, MMC1_readWRAM);
|
||||
SetWriteHandler(0x6000, 0x7FFF, MMC1_writeWRAM);
|
||||
SetReadHandler (0x8000, 0xFFFF, CartBR);
|
||||
SetWriteHandler(0x8000, 0xFFFF, MMC1_write);
|
||||
SetWriteHandler(0x8000, 0xFFFF, MMC1_writeReg);
|
||||
MapIRQHook = MMC1_cpuCycle;
|
||||
}
|
||||
|
||||
|
||||
@@ -31,7 +31,7 @@ void MMC1_syncPRG (int, int);
|
||||
void MMC1_syncCHR (int, int);
|
||||
void MMC1_syncMirror ();
|
||||
void FP_FASTAPASS(1) MMC1_cpuCycle(int);
|
||||
DECLFW (MMC1_write);
|
||||
DECLFW (MMC1_writeReg);
|
||||
void MMC1_addExState ();
|
||||
void MMC1_restore (int);
|
||||
void MMC1_power ();
|
||||
|
||||
Reference in New Issue
Block a user