Add mapper116 multi-rom support (Mapper 116-瑪莉家族大集合 5-in-1)
This commit is contained in:
libretroadmin
104
src/boards/116.c
104
src/boards/116.c
@@ -53,7 +53,8 @@ static uint8 IRQa = 0;
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static uint8 IRQReload = 0;
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static uint8 mode = 0;
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static uint32 isHuang2 = 0;
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static uint8 submapper = 0;
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static uint8 game = 0;
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extern uint32 ROM_size;
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extern uint32 VROM_size;
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@@ -74,32 +75,36 @@ static SFORMAT StateRegs[] =
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{ mmc1_regs, 4, "M1RG" },
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{ &mmc1_buffer, 1, "M1BF" },
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{ &mmc1_shift, 1, "M1MR" },
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{ &submapper, 1, "SUBM" },
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{ &game, 1, "GAME" },
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{ 0 }
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};
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static void SyncPRG(void) {
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uint8 mask = (submapper != 3) ? 0x3F : (game ? 0x0F : 0x1F);
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uint8 outer = game ? (game + 1) * 0x10 : 0;
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switch (mode & 3) {
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case 0:
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setprg8(0x8000, vrc2_prg[0]);
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setprg8(0xA000, vrc2_prg[1]);
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setprg8(0xC000, ~1);
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setprg8(0xE000, ~0);
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setprg8(0x8000, (outer & ~mask) | (vrc2_prg[0] & mask));
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setprg8(0xA000, (outer & ~mask) | (vrc2_prg[1] & mask));
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setprg8(0xC000, (outer & ~mask) | (~1 & mask));
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setprg8(0xE000, (outer & ~mask) | (~0 & mask));
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break;
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case 1:
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{
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uint32 swap = (mmc3_ctrl >> 5) & 2;
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setprg8(0x8000, mmc3_regs[6 + swap]);
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setprg8(0xA000, mmc3_regs[7]);
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setprg8(0xC000, mmc3_regs[6 + (swap ^ 2)]);
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setprg8(0xE000, mmc3_regs[9]);
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setprg8(0x8000, (outer & ~mask) | (mmc3_regs[6 + swap] & mask));
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setprg8(0xA000, (outer & ~mask) | (mmc3_regs[7] & mask));
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setprg8(0xC000, (outer & ~mask) | (mmc3_regs[6 + (swap ^ 2)] & mask));
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setprg8(0xE000, (outer & ~mask) | (mmc3_regs[9] & mask));
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break;
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}
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case 2:
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case 3:
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{
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uint8 bank = mmc1_regs[3] & 0xF;
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uint8 bank = mmc1_regs[3] & mask;
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if (mmc1_regs[0] & 8) {
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if (isHuang2)
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if (submapper == 2)
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bank >>= 1;
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if (mmc1_regs[0] & 4) {
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setprg16(0x8000, bank);
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@@ -109,44 +114,46 @@ static void SyncPRG(void) {
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setprg16(0xC000, bank);
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}
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} else
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setprg32(0x8000, bank >> 1);
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setprg32(0x8000, ((outer & ~mask) >> 1) | (bank >> 1));
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}
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break;
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}
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}
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static void SyncCHR(void) {
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uint32 base = (mode & 4) << 6;
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uint32 mask = game ? 0x7F : 0xFF;
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uint32 outer = game ? (game + 1) * 0x80 : 0;
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uint32 base = (mode & 4) << 6;
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switch (mode & 3) {
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case 0:
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setchr1(0x0000, base | vrc2_chr[0]);
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setchr1(0x0400, base | vrc2_chr[1]);
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setchr1(0x0800, base | vrc2_chr[2]);
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setchr1(0x0c00, base | vrc2_chr[3]);
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setchr1(0x1000, base | vrc2_chr[4]);
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setchr1(0x1400, base | vrc2_chr[5]);
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setchr1(0x1800, base | vrc2_chr[6]);
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setchr1(0x1c00, base | vrc2_chr[7]);
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setchr1(0x0000, ((outer | base) & ~mask) | (vrc2_chr[0] & mask));
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setchr1(0x0400, ((outer | base) & ~mask) | (vrc2_chr[1] & mask));
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setchr1(0x0800, ((outer | base) & ~mask) | (vrc2_chr[2] & mask));
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setchr1(0x0c00, ((outer | base) & ~mask) | (vrc2_chr[3] & mask));
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setchr1(0x1000, ((outer | base) & ~mask) | (vrc2_chr[4] & mask));
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setchr1(0x1400, ((outer | base) & ~mask) | (vrc2_chr[5] & mask));
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setchr1(0x1800, ((outer | base) & ~mask) | (vrc2_chr[6] & mask));
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setchr1(0x1c00, ((outer | base) & ~mask) | (vrc2_chr[7] & mask));
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break;
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case 1: {
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uint32 swap = (mmc3_ctrl & 0x80) << 5;
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setchr1(0x0000 ^ swap, base | ((mmc3_regs[0]) & 0xFE));
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setchr1(0x0400 ^ swap, base | (mmc3_regs[0] | 1));
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setchr1(0x0800 ^ swap, base | ((mmc3_regs[1]) & 0xFE));
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setchr1(0x0c00 ^ swap, base | (mmc3_regs[1] | 1));
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setchr1(0x1000 ^ swap, base | mmc3_regs[2]);
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setchr1(0x1400 ^ swap, base | mmc3_regs[3]);
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setchr1(0x1800 ^ swap, base | mmc3_regs[4]);
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setchr1(0x1c00 ^ swap, base | mmc3_regs[5]);
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setchr1(0x0000 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[0] & 0xFE) & mask));
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setchr1(0x0400 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[0] | 1) & mask));
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setchr1(0x0800 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[1] & 0xFE) & mask));
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setchr1(0x0c00 ^ swap, ((outer | base) & ~mask) | ((mmc3_regs[1] | 1) & mask));
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setchr1(0x1000 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[2] & mask));
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setchr1(0x1400 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[3] & mask));
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setchr1(0x1800 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[4] & mask));
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setchr1(0x1c00 ^ swap, ((outer | base) & ~mask) | (mmc3_regs[5] & mask));
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break;
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}
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case 2:
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case 3:
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if (mmc1_regs[0] & 0x10) {
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setchr4(0x0000, mmc1_regs[1]);
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setchr4(0x1000, mmc1_regs[2]);
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setchr4(0x0000, (outer & ~mask) | (mmc1_regs[1] & mask));
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setchr4(0x1000, (outer & ~mask) | (mmc1_regs[2] & mask));
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} else
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setchr8(mmc1_regs[1] >> 1);
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setchr8(((outer & ~mask) >> 1) | (mmc1_regs[1] & mask) >> 1);
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break;
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}
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}
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@@ -181,8 +188,7 @@ static void Sync(void) {
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}
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static DECLFW(UNLSL12ModeWrite) {
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/* FCEU_printf("%04X:%02X\n",A,V); */
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if ((A & 0x4100) == 0x4100) {
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if (A & 0x100) {
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mode = V;
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if (A & 1) { /* hacky hacky, there are two configuration modes on SOMARI HUANG-1 PCBs
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* Solder pads with P1/P2 shorted called SOMARI P,
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@@ -299,8 +305,20 @@ static void StateRestore(int version) {
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Sync();
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}
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static void UNLSL12Reset(void) {
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/* this is suppose to increment during power cycle */
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/* but we dont have a way to do that, so increment on reset instead. */
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if (submapper == 3) {
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game = game + 1;
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if (game > 4)
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game = 0;
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}
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Sync();
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}
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static void UNLSL12Power(void) {
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mode = 0;
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game = (submapper == 3) ? 4 : 0;
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mode = 1;
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vrc2_chr[0] = ~0;
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vrc2_chr[1] = ~0;
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vrc2_chr[2] = ~0;
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@@ -331,16 +349,20 @@ static void UNLSL12Power(void) {
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mmc1_shift = 0;
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Sync();
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x4100, 0x7FFF, UNLSL12ModeWrite);
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SetWriteHandler(0x4100, 0x5FFF, UNLSL12ModeWrite);
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SetWriteHandler(0x8000, 0xFFFF, UNLSL12Write);
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}
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void UNLSL12_Init(CartInfo *info) {
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info->Power = UNLSL12Power;
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GameHBIRQHook = UNLSL12HBIRQ;
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info->Power = UNLSL12Power;
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info->Reset = UNLSL12Reset;
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GameHBIRQHook = UNLSL12HBIRQ;
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GameStateRestore = StateRestore;
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AddExState(&StateRegs, ~0, 0, 0);
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/* PRG 128K and CHR 128K is Huang-2 */
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if (ROM_size == 8 && VROM_size == 16)
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isHuang2 = 1;
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submapper = info->submapper;
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if (submapper == 0) {
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/* PRG 128K and CHR 128K is Huang-2 (submapper 2) */
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if (ROM_size == 8 && VROM_size == 16)
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submapper = 2;
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}
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}
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