core: stdint typedefs, LE optimizations, frame determinism
Three follow-up audit passes on top of the memory-safety / leak / savestate-portability work in1185db8. ============================================================== Pass 1: replace custom typedefs with C99 stdint types throughout ============================================================== The custom uint8 / uint16 / uint32 / uint64 / int8 / int16 / int32 / int64 typedefs in src/fceu-types.h were just simple aliases for the C99 stdint.h types. Replace them with the standard names directly. - 498 files modified - ~3,400 token replacements (uint8 -> uint8_t, etc) - fceu-types.h slimmed down to just INLINE / GINLINE / FASTAPASS macros and the readfunc / writefunc function-pointer typedefs (those now use uint8_t / uint32_t natively) - Build clean on `make platform=unix` with zero new warnings - Output binary size unchanged - confirming semantic equivalence Mechanical replacement done with a Python script that uses word- boundary regex to avoid false positives (e.g. 'uint32_t' was correctly left alone because '_' is a word character so 'uint32' is not a complete word inside it). ================================================================ Pass 2: prefer memcpy on LE hosts for endian read/write helpers ================================================================ fceu-endian.c's write32le_mem, FCEU_en32lsb, and FCEU_de32lsb performed bytewise composition/decomposition unconditionally. On LE hosts the in-memory representation already matches the desired LE on-disk format, so a single memcpy is equivalent and lets the compiler emit a single load/store rather than four byte ops. - The bytewise path is kept inside #ifdef MSB_FIRST for BE hosts where it implements the actual byte swap - Both forms produce identical results; this is a code-clarity change more than a performance one (the optimizer was already merging the shifts on LE), but it documents the intent and removes a strict-aliasing-flavoured cast through *(uint32_t*)Bufo - Added missing #include <string.h> in fceu-endian.c which was relying on transitive includes for memcpy Other MSB_FIRST sites in the codebase (state.c FlipByteOrder guards, ppu.c sprite-line rendering, boards/unrom512.c flash-write- counter access) were already optimized for LE; they were verified correct rather than changed. ================================================================ Pass 3: frame determinism for replay and netplay ================================================================ Two libc rand() sites in core were replaced with a local xorshift32 PRNG so that NES games which read uninitialised memory or hit hardware "weak bit" emulation produce reproducible behaviour across runs. NES titles routinely read uninitialised RAM (variables not zeroed before use, sprite Y-position set by junk-on-stack), so the RAM contents at power-on subtly affect game behaviour. With libc rand(), those contents depend on whether anyone else seeded rand() in the same process - a different libretro frontend, a different audio backend init order, or any frontend that does srand(time(0)) all break replay / netplay frame-determinism. 1. fceu.c FCEU_MemoryRand. Used to fill RAM (PowerNES) and CHR-RAM (iNES_Init) at power-on when option_ramstate=2 (random init). Replaced with a local xorshift32 PRNG, exposed via a new FCEU_MemoryRand_Reseed(uint32_t) function called once per power-on: - PowerNES seeds from the first 4 bytes of GameInfo->MD5 (set by all loaders before PowerNES runs) so identical ROMs produce identical RAM, different ROMs differ - iNES_Init seeds from iNESCart.PRGCRC32 before the CHR-RAM fill so two builds of the same ROM get the same CHR-RAM - The PRNG state advances across multiple FCEU_MemoryRand calls within one power-on so RAM and CHR-RAM get different content (matching NES hardware reality) 2. boards/rt-01.c UNLRT01Read. The RT-01 board has 'weak bit' protected EPROM regions; reads of 0xCE80-0xCEFF and 0xFE80- 0xFEFF return 0xF2 with the low 3 bits randomised. Replaced libc rand() with a local xorshift32 seeded at power-on, and added the PRNG state to the savestate via AddExState with key "WBKS" so save / load / rewind / netplay rollback all stay deterministic. In addition, two long-double-to-int truncations were changed to double for cross-platform FP determinism: - sound.c SetSoundVariables: soundtsinc - boards/n106.c DoNamcoSound: inc long double has platform-dependent precision (80-bit on x87, 64-bit with -mfpmath=sse, 128-bit on PowerPC), so the truncated integer result varied across these platforms. double is guaranteed 64-bit IEEE-754 portably. After this pass, the core has no time(), clock(), gettimeofday(), clock_gettime(), getpid(), getuid(), getgid(), getenv(), gethostid(), pthread, std::thread, OpenMP, signal handler, or non-deterministic- malloc dependency. Verified with a Python scanner that greps the source for these patterns; runs clean. The PPU / APU / CPU power-on already explicitly memset all state buffers to 0 (deterministic), and ROM/CHR-ROM allocation already memsets to 0xFF before partial fread (deterministic regardless of file truncation). Combined with the memory-safety hardening in1185db8(which prevents savestate-loaded indices from going out-of-bounds and producing unpredictable behaviour), the core now offers genuine frame-deterministic replay across runs, builds, and host endian.
This commit is contained in:
U-DESKTOP-SPFP6AQ\twistedtechre
86
src/cart.h
86
src/cart.h
@@ -6,8 +6,8 @@ typedef struct {
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void (*Power)(void);
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void (*Reset)(void);
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void (*Close)(void);
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uint8 *SaveGame[4]; /* Pointers to memory to save/load. */
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uint32 SaveGameLen[4]; /* How much memory to save/load. */
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uint8_t *SaveGame[4]; /* Pointers to memory to save/load. */
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uint32_t SaveGameLen[4]; /* How much memory to save/load. */
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/* Set by iNES/UNIF loading code. */
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int iNES2; /* iNES version */
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@@ -28,71 +28,71 @@ typedef struct {
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int CHRRamSaveSize; /* chr ram size in bytes (non-volatile or battery backed) */
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int miscROMSize;
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int miscROMNumber;
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uint64 totalFileSize;
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uint64_t totalFileSize;
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int region; /* video system timing (ntsc, pal, dendy */
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uint8 MD5[16];
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uint32 PRGCRC32;
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uint32 CHRCRC32;
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uint32 CRC32; /* Should be set by the iNES/UNIF loading
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uint8_t MD5[16];
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uint32_t PRGCRC32;
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uint32_t CHRCRC32;
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uint32_t CRC32; /* Should be set by the iNES/UNIF loading
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* code, used by mapper/board code, maybe
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* other code in the future.
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*/
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} CartInfo;
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extern uint8 *Page[32], *VPage[8], *MMC5SPRVPage[8], *MMC5BGVPage[8];
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extern uint8_t *Page[32], *VPage[8], *MMC5SPRVPage[8], *MMC5BGVPage[8];
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void ResetCartMapping(void);
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void SetupCartPRGMapping(int chip, uint8 *p, uint32 size, int ram);
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void SetupCartCHRMapping(int chip, uint8 *p, uint32 size, int ram);
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void SetupCartMirroring(int m, int hard, uint8 *extra);
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void SetupCartPRGMapping(int chip, uint8_t *p, uint32_t size, int ram);
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void SetupCartCHRMapping(int chip, uint8_t *p, uint32_t size, int ram);
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void SetupCartMirroring(int m, int hard, uint8_t *extra);
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DECLFR(CartBROB);
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DECLFR(CartBR);
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DECLFW(CartBW);
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extern uint8 *PRGptr[32];
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extern uint8 *CHRptr[32];
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extern uint8_t *PRGptr[32];
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extern uint8_t *CHRptr[32];
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extern uint32 PRGsize[32];
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extern uint32 CHRsize[32];
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extern uint32_t PRGsize[32];
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extern uint32_t CHRsize[32];
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extern uint32 PRGmask2[32];
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extern uint32 PRGmask4[32];
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extern uint32 PRGmask8[32];
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extern uint32 PRGmask16[32];
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extern uint32 PRGmask32[32];
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extern uint32_t PRGmask2[32];
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extern uint32_t PRGmask4[32];
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extern uint32_t PRGmask8[32];
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extern uint32_t PRGmask16[32];
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extern uint32_t PRGmask32[32];
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extern uint32 CHRmask1[32];
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extern uint32 CHRmask2[32];
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extern uint32 CHRmask4[32];
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extern uint32 CHRmask8[32];
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extern uint32_t CHRmask1[32];
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extern uint32_t CHRmask2[32];
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extern uint32_t CHRmask4[32];
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extern uint32_t CHRmask8[32];
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void FASTAPASS(2) setprg2(uint32 A, uint32 V);
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void FASTAPASS(2) setprg4(uint32 A, uint32 V);
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void FASTAPASS(2) setprg8(uint32 A, uint32 V);
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void FASTAPASS(2) setprg16(uint32 A, uint32 V);
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void FASTAPASS(2) setprg32(uint32 A, uint32 V);
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void FASTAPASS(2) setprg2(uint32_t A, uint32_t V);
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void FASTAPASS(2) setprg4(uint32_t A, uint32_t V);
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void FASTAPASS(2) setprg8(uint32_t A, uint32_t V);
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void FASTAPASS(2) setprg16(uint32_t A, uint32_t V);
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void FASTAPASS(2) setprg32(uint32_t A, uint32_t V);
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void FASTAPASS(3) setprg2r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setprg4r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setprg8r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setprg16r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setprg32r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setprg2r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setprg4r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setprg8r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setprg16r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setprg32r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setchr1r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setchr2r(int r, uint32 A, uint32 V);
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void FASTAPASS(3) setchr4r(int r, uint32 A, uint32 V);
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void FASTAPASS(2) setchr8r(int r, uint32 V);
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void FASTAPASS(3) setchr1r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setchr2r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(3) setchr4r(int r, uint32_t A, uint32_t V);
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void FASTAPASS(2) setchr8r(int r, uint32_t V);
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void FASTAPASS(2) setchr1(uint32 A, uint32 V);
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void FASTAPASS(2) setchr2(uint32 A, uint32 V);
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void FASTAPASS(2) setchr4(uint32 A, uint32 V);
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void FASTAPASS(2) setchr8(uint32 V);
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void FASTAPASS(2) setchr1(uint32_t A, uint32_t V);
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void FASTAPASS(2) setchr2(uint32_t A, uint32_t V);
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void FASTAPASS(2) setchr4(uint32_t A, uint32_t V);
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void FASTAPASS(2) setchr8(uint32_t V);
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void FASTAPASS(1) setmirror(int t);
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void setmirrorw(int a, int b, int c, int d);
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void FASTAPASS(3) setntamem(uint8 *p, int ram, uint32 b);
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void FASTAPASS(3) setntamem(uint8_t *p, int ram, uint32_t b);
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#define MI_H 0
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#define MI_V 1
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