core: stdint typedefs, LE optimizations, frame determinism
Three follow-up audit passes on top of the memory-safety / leak / savestate-portability work in1185db8. ============================================================== Pass 1: replace custom typedefs with C99 stdint types throughout ============================================================== The custom uint8 / uint16 / uint32 / uint64 / int8 / int16 / int32 / int64 typedefs in src/fceu-types.h were just simple aliases for the C99 stdint.h types. Replace them with the standard names directly. - 498 files modified - ~3,400 token replacements (uint8 -> uint8_t, etc) - fceu-types.h slimmed down to just INLINE / GINLINE / FASTAPASS macros and the readfunc / writefunc function-pointer typedefs (those now use uint8_t / uint32_t natively) - Build clean on `make platform=unix` with zero new warnings - Output binary size unchanged - confirming semantic equivalence Mechanical replacement done with a Python script that uses word- boundary regex to avoid false positives (e.g. 'uint32_t' was correctly left alone because '_' is a word character so 'uint32' is not a complete word inside it). ================================================================ Pass 2: prefer memcpy on LE hosts for endian read/write helpers ================================================================ fceu-endian.c's write32le_mem, FCEU_en32lsb, and FCEU_de32lsb performed bytewise composition/decomposition unconditionally. On LE hosts the in-memory representation already matches the desired LE on-disk format, so a single memcpy is equivalent and lets the compiler emit a single load/store rather than four byte ops. - The bytewise path is kept inside #ifdef MSB_FIRST for BE hosts where it implements the actual byte swap - Both forms produce identical results; this is a code-clarity change more than a performance one (the optimizer was already merging the shifts on LE), but it documents the intent and removes a strict-aliasing-flavoured cast through *(uint32_t*)Bufo - Added missing #include <string.h> in fceu-endian.c which was relying on transitive includes for memcpy Other MSB_FIRST sites in the codebase (state.c FlipByteOrder guards, ppu.c sprite-line rendering, boards/unrom512.c flash-write- counter access) were already optimized for LE; they were verified correct rather than changed. ================================================================ Pass 3: frame determinism for replay and netplay ================================================================ Two libc rand() sites in core were replaced with a local xorshift32 PRNG so that NES games which read uninitialised memory or hit hardware "weak bit" emulation produce reproducible behaviour across runs. NES titles routinely read uninitialised RAM (variables not zeroed before use, sprite Y-position set by junk-on-stack), so the RAM contents at power-on subtly affect game behaviour. With libc rand(), those contents depend on whether anyone else seeded rand() in the same process - a different libretro frontend, a different audio backend init order, or any frontend that does srand(time(0)) all break replay / netplay frame-determinism. 1. fceu.c FCEU_MemoryRand. Used to fill RAM (PowerNES) and CHR-RAM (iNES_Init) at power-on when option_ramstate=2 (random init). Replaced with a local xorshift32 PRNG, exposed via a new FCEU_MemoryRand_Reseed(uint32_t) function called once per power-on: - PowerNES seeds from the first 4 bytes of GameInfo->MD5 (set by all loaders before PowerNES runs) so identical ROMs produce identical RAM, different ROMs differ - iNES_Init seeds from iNESCart.PRGCRC32 before the CHR-RAM fill so two builds of the same ROM get the same CHR-RAM - The PRNG state advances across multiple FCEU_MemoryRand calls within one power-on so RAM and CHR-RAM get different content (matching NES hardware reality) 2. boards/rt-01.c UNLRT01Read. The RT-01 board has 'weak bit' protected EPROM regions; reads of 0xCE80-0xCEFF and 0xFE80- 0xFEFF return 0xF2 with the low 3 bits randomised. Replaced libc rand() with a local xorshift32 seeded at power-on, and added the PRNG state to the savestate via AddExState with key "WBKS" so save / load / rewind / netplay rollback all stay deterministic. In addition, two long-double-to-int truncations were changed to double for cross-platform FP determinism: - sound.c SetSoundVariables: soundtsinc - boards/n106.c DoNamcoSound: inc long double has platform-dependent precision (80-bit on x87, 64-bit with -mfpmath=sse, 128-bit on PowerPC), so the truncated integer result varied across these platforms. double is guaranteed 64-bit IEEE-754 portably. After this pass, the core has no time(), clock(), gettimeofday(), clock_gettime(), getpid(), getuid(), getgid(), getenv(), gethostid(), pthread, std::thread, OpenMP, signal handler, or non-deterministic- malloc dependency. Verified with a Python scanner that greps the source for these patterns; runs clean. The PPU / APU / CPU power-on already explicitly memset all state buffers to 0 (deterministic), and ROM/CHR-ROM allocation already memsets to 0xFF before partial fread (deterministic regardless of file truncation). Combined with the memory-safety hardening in1185db8(which prevents savestate-loaded indices from going out-of-bounds and producing unpredictable behaviour), the core now offers genuine frame-deterministic replay across runs, builds, and host endian.
This commit is contained in:
U-DESKTOP-SPFP6AQ\twistedtechre
@@ -24,30 +24,30 @@
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#include "mmc3.h"
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void (*sync)(void);
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static uint8 allowExtendedMirroring;
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static uint8_t allowExtendedMirroring;
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static uint8 mode[4];
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static uint8* WRAM = NULL;
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static uint32 WRAMSIZE;
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static uint8_t mode[4];
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static uint8_t* WRAM = NULL;
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static uint32_t WRAMSIZE;
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static uint8 irqControl;
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static uint8 irqEnabled;
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static uint8 irqPrescaler;
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static uint8 irqCounter;
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static uint8 irqXor;
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static uint32 lastPPUAddress;
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static uint8_t irqControl;
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static uint8_t irqEnabled;
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static uint8_t irqPrescaler;
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static uint8_t irqCounter;
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static uint8_t irqXor;
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static uint32_t lastPPUAddress;
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static uint8 prg[4];
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static uint16 chr[8];
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static uint16 nt[4];
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static uint8 latch[2];
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static uint8 mul[2];
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static uint8 adder;
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static uint8 test;
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static uint8 dipSwitch;
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static uint8 submapper;
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static uint8_t prg[4];
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static uint16_t chr[8];
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static uint16_t nt[4];
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static uint8_t latch[2];
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static uint8_t mul[2];
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static uint8_t adder;
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static uint8_t test;
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static uint8_t dipSwitch;
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static uint8_t submapper;
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static uint8 cpuWriteHandlersSet;
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static uint8_t cpuWriteHandlersSet;
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static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
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static SFORMAT JYASIC_stateRegs[] = {
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@@ -71,7 +71,7 @@ static SFORMAT JYASIC_stateRegs[] = {
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{ 0 }
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};
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static uint8 rev (uint8_t val)
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static uint8_t rev (uint8_t val)
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{
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return ((val <<6) &0x40) | ((val <<4) &0x20) | ((val <<2) &0x10) | (val &0x08) | ((val >>2) &0x04) | ((val >>4) &0x02) | ((val >>6) &0x01);
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}
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@@ -218,7 +218,7 @@ static DECLFW(trapCPUWrite)
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cpuWriteHandlers[A](A, V);
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}
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A)
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32_t A)
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{
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if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A)
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{
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@@ -460,7 +460,7 @@ void JYASIC_init (CartInfo *info)
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if (WRAMSIZE)
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{
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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WRAM = (uint8_t*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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}
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@@ -691,7 +691,7 @@ void Mapper421_Init(CartInfo *info)
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}
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/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */
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static uint8 HSK007Reg[4];
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static uint8_t HSK007Reg[4];
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void sync394 (void) /* Called when J.Y. ASIC is active */
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{
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int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x060;
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@@ -700,7 +700,7 @@ void sync394 (void) /* Called when J.Y. ASIC is active */
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syncCHR(0xFF, chrOR);
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syncNT (0xFF, chrOR);
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}
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static void Mapper394_PWrap(uint32 A, uint8 V)
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static void Mapper394_PWrap(uint32_t A, uint8_t V)
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{
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int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
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int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x060;
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@@ -711,7 +711,7 @@ static void Mapper394_PWrap(uint32 A, uint8 V)
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setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2);
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}
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static void Mapper394_CWrap(uint32 A, uint8 V)
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static void Mapper394_CWrap(uint32_t A, uint8_t V)
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{
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int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
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int chrOR =submapper ==1? (HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x200 | HSK007Reg[1] <<6 &0x100): (HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x300);
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@@ -719,7 +719,7 @@ static void Mapper394_CWrap(uint32 A, uint8 V)
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}
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static DECLFW(Mapper394_Write)
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{
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uint8 oldMode =HSK007Reg[1];
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uint8_t oldMode =HSK007Reg[1];
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A &=3;
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HSK007Reg[A] =V;
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if (A ==1)
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