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Merge pull request #329 from negativeExponent/updates_and_fixes

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mapper updates and fixes
This commit is contained in:
Twinaphex
2020-02-29 19:06:15 +01:00
committed by GitHub
parent aac87ab091 46fe43a4f2
commit 4368cedaa4
24 changed files with 416 additions and 516 deletions
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48
src/boards/15.c
View File

@@ -27,34 +27,42 @@ static uint8 *WRAM = NULL;
static uint32 WRAMSIZE;
static SFORMAT StateRegs[] =
{
{ &latchea, 2, "AREG" },
{ &latchea, 2 | FCEUSTATE_RLSB, "AREG" },
{ &latched, 1, "DREG" },
{ 0 }
};
static void Sync(void) {
int i;
setmirror(((latched >> 6) & 1) ^ 1);
switch (latchea) {
case 0x8000:
for (i = 0; i < 4; i++)
setprg8(0x8000 + (i << 13), (((latched & 0x7F) << 1) + i) ^ (latched >> 7));
uint32 preg[4];
uint32 bank = (latched & 0x3F) << 1;
switch (latchea & 0x03) {
case 0:
preg[0] = bank + 0;
preg[1] = bank + 1;
preg[2] = bank + 2;
preg[3] = bank + 3;
break;
case 0x8002:
for (i = 0; i < 4; i++)
setprg8(0x8000 + (i << 13), ((latched & 0x7F) << 1) + (latched >> 7));
case 2:
bank = bank | (latched >> 7);
preg[0] = bank;
preg[1] = bank;
preg[2] = bank;
preg[3] = bank;
break;
case 0x8001:
case 0x8003:
for (i = 0; i < 4; i++) {
unsigned int b;
b = latched & 0x7F;
if (i >= 2 && !(latchea & 0x2))
b = 0x7F;
setprg8(0x8000 + (i << 13), (i & 1) + ((b << 1) ^ (latched >> 7)));
}
case 1:
case 3:
preg[0] = bank + 0;
preg[1] = bank + 1;
preg[2] = (((latchea & 0x02) == 0) ? (bank | 0xE) : bank) + 0;
preg[3] = (((latchea & 0x02) == 0) ? (bank | 0xE) : bank) + 1;
break;
}
setprg8(0x8000, preg[0]);
setprg8(0xA000, preg[1]);
setprg8(0xC000, preg[2]);
setprg8(0xE000, preg[3]);
setmirror(((latched >> 6) & 1) ^ 1);
}
static DECLFW(M15Write) {
@@ -76,7 +84,7 @@ static void M15Power(void) {
SetWriteHandler(0x6000, 0x7FFF, CartBW);
SetWriteHandler(0x8000, 0xFFFF, M15Write);
SetReadHandler(0x8000, 0xFFFF, CartBR);
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
Sync();
}

3
src/boards/218.c
View File

@@ -21,9 +21,6 @@
#include "mapinc.h"
#include "../ines.h"
static uint8 mirror;
static uint8 mask;
static void M218Power(void) {
setchr8(0);
setprg32(0x8000, 0);

20
src/boards/225.c
View File

@@ -2,6 +2,8 @@
*
* Copyright notice for this file:
* Copyright (C) 2011 CaH4e3
* Copyright (C) 2019 Libretro Team
* Copyright (C) 2020 negativeExponent
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,15 +21,20 @@
*
* PCB-018 board, discrete multigame cart 110-in-1
*
* Mapper 225
* Mapper 255
*
*/
/* 2020-2-20 - merge mapper 255, re-implement extra RAM */
#include "mapinc.h"
static uint8 prot[4], prg, mode, chr, mirr;
static uint8 extraRAM[4], prg, mode, chr, mirr;
static SFORMAT StateRegs[] =
{
{ prot, 4, "PROT" },
{ extraRAM, 4, "PROT" },
{ &prg, 1, "PRG" },
{ &chr, 1, "CHR" },
{ &mode, 1, "MODE" },
@@ -55,10 +62,13 @@ static DECLFW(M225Write) {
}
static DECLFW(M225LoWrite) {
/* e.g. 115-in-1 [p1][!] CRC32 0xb39d30b4 */
if (A & 0x800) extraRAM[A & 3] = V & 0x0F;
}
static DECLFR(M225LoRead) {
return 0;
if (A & 0x800) return extraRAM[A & 3];
return X.DB;
}
static void M225Power(void) {
@@ -87,3 +97,7 @@ void Mapper225_Init(CartInfo *info) {
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
}
void Mapper255_Init(CartInfo *info) {
Mapper225_Init(info);
}

83
src/boards/235.c
View File

@@ -2,6 +2,7 @@
*
* Copyright notice for this file:
* Copyright (C) 2005 CaH4e3
* Copyright (C) 2020 negativeExponent
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,35 +20,76 @@
*/
#include "mapinc.h"
#include "../ines.h"
static uint8 *CHRRAM;
static uint32 CHRRAMSIZE;
static uint16 cmdreg;
static uint8 unrom, reg, type, openbus;
static SFORMAT StateRegs[] =
{
{ &cmdreg, 2, "CREG" },
{ &cmdreg, 2 | FCEUSTATE_RLSB, "CREG" },
{ &unrom, 1, "UNRM" },
{ &reg, 1, "UNRG" },
{ &type, 1, "TYPE" },
{ &openbus, 1, "OPNB" },
{ 0 }
};
static void Sync(void) {
if (cmdreg & 0x400)
setmirror(MI_0);
else
setmirror(((cmdreg >> 13) & 1) ^ 1);
if (cmdreg & 0x800) {
setprg16(0x8000, ((cmdreg & 0x300) >> 3) | ((cmdreg & 0x1F) << 1) | ((cmdreg >> 12) & 1));
setprg16(0xC000, ((cmdreg & 0x300) >> 3) | ((cmdreg & 0x1F) << 1) | ((cmdreg >> 12) & 1));
} else
setprg32(0x8000, ((cmdreg & 0x300) >> 4) | (cmdreg & 0x1F));
if (type && unrom) {
setprg16(0x8000, 0x80 | reg & 7);
setprg16(0xC000, 0x80 | 7);
setchr8(0);
setmirror(MI_V);
} else {
uint8 bank = ((cmdreg & 0x300) >> 3) | (cmdreg & 0x1F);
if (cmdreg & 0x400)
setmirror(MI_0);
else
setmirror(((cmdreg >> 13) & 1) ^ 1);
if (bank >= PRGsize[0] / 32768)
openbus = 1;
else if (cmdreg & 0x800) {
setprg16(0x8000, (bank << 1) | ((cmdreg >> 12) & 1));
setprg16(0xC000, (bank << 1) | ((cmdreg >> 12) & 1));
} else
setprg32(0x8000, bank);
setchr8(0);
}
}
static DECLFR(M235Read) {
if (openbus) {
openbus = 0;
return X.DB;
}
return CartBR(A);
}
static DECLFW(M235Write) {
cmdreg = A;
reg = V;
Sync();
}
static void M235Close(void) {
if (CHRRAM)
FCEU_free(CHRRAM);
CHRRAM = NULL;
}
static void M235Reset(void) {
cmdreg = 0;
unrom = (unrom + type) & 1;
Sync();
}
static void M235Power(void) {
setchr8(0);
SetWriteHandler(0x8000, 0xFFFF, M235Write);
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetReadHandler(0x8000, 0xFFFF, M235Read);
cmdreg = 0;
Sync();
}
@@ -57,7 +99,24 @@ static void M235Restore(int version) {
}
void Mapper235_Init(CartInfo *info) {
info->Reset = M235Reset;
info->Power = M235Power;
info->Close = M235Close;
GameStateRestore = M235Restore;
AddExState(&StateRegs, ~0, 0, 0);
/* some nes 2.0 header do can have no chr-ram.
* one such cart is 210-in-1 and Contra 4-in-1 (212-in-1,212 Hong Kong,Reset Based)(Unl).nes (0x745A6791)
*/
if (CHRsize[0] == 0) {
CHRRAMSIZE = 8192;
CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE);
SetupCartCHRMapping(0, CHRRAM, CHRRAMSIZE, 1);
AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM");
}
type = 0;
/* carts with unrom game, reset-based */
if ((info->CRC32) == 0x745A6791) /* 210-in-1 and Contra 4-in-1 (212-in-1,212 Hong Kong,Reset Based)(Unl).nes */
type = 1;
}

79
src/boards/255.c
View File

@@ -1,79 +0,0 @@
/* FCEUmm - NES/Famicom Emulator
*
* Copyright (C) 2019 Libretro Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* added 2019-5-23
* Mapper 255
* https://wiki.nesdev.com/w/index.php/INES_Mapper_225
* 115-in-1 [p1][!] CRC32 0xb39d30b4
* Seems to handle up to last game in the multicarts than m225 but causes
* graphics garbage past it, else games works fine */
#include "mapinc.h"
static uint8 preg, creg, mode, mirr;
static SFORMAT StateRegs[] =
{
{ &preg, 1, "PRG0" },
{ &creg, 1, "CHR0" },
{ &mode, 1, "MODE" },
{ &mirr, 1, "MIRR" },
{ 0 }
};
static void Sync(void) {
setprg16(0x8000, preg & ~mode);
setprg16(0xC000, preg | mode);
setchr8(creg);
setmirror(mirr ^ 1);
}
static DECLFW(M255Write) {
uint32 bank = (A >> 8 & 0x40);
preg = bank | ((A >> 6) & 0x3F);
creg = bank | (A & 0x3F);
mirr = (A >> 13) & 1;
mode = ((~A) >> 12 & 1);
Sync();
}
static void M255Power(void) {
preg = 0;
mode = 1;
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0xFFFF, M255Write);
}
static void M255Reset(void) {
preg = 0;
mode = 1;
Sync();
}
static void StateRestore(int version) {
Sync();
}
void Mapper255_Init(CartInfo *info) {
info->Reset = M255Reset;
info->Power = M255Power;
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
}

8
src/boards/267.c
View File

@@ -26,15 +26,15 @@
#define OUTER_BANK (((EXPREGS[0] & 0x20) >> 2) | (EXPREGS[0] & 0x06))
static void M267CW(uint32 A, uint8 V) {
setchr1(A, (V & 0x7F) | (OUTER_BANK << 6));
setchr1(A, (V & 0x7F) | (OUTER_BANK << 6));
}
static void M267PW(uint32 A, uint8 V) {
setprg8(A, (V & 0x1F) | (OUTER_BANK << 4));
setprg8(A, (V & 0x1F) | (OUTER_BANK << 4));
}
static DECLFW(M267Write) {
EXPREGS[0] = V;
EXPREGS[0] = V;
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
}
@@ -46,7 +46,7 @@ static void M267Reset(void) {
static void M267Power(void) {
EXPREGS[0] = 0;
GenMMC3Power();
GenMMC3Power();
SetWriteHandler(0x6000, 0x6FFF, M267Write);
}

7
src/boards/269.c
View File

@@ -54,6 +54,12 @@ static DECLFW(M269Write5) {
}
}
static void M269Close(void) {
if (CHRROM)
FCEU_free(CHRROM);
CHRROM = NULL;
}
static void M269Reset(void) {
EXPREGS[0] = EXPREGS[1] = EXPREGS[3] = EXPREGS[4] = 0;
EXPREGS[2] = 0x0F;
@@ -85,5 +91,6 @@ void Mapper269_Init(CartInfo *info) {
pwrap = M269PW;
info->Power = M269Power;
info->Reset = M269Reset;
info->Close = M269Close;
AddExState(EXPREGS, 5, 0, "EXPR");
}

8
src/boards/353.c
View File

@@ -84,13 +84,13 @@ static void M353MW(uint8 V) {
static DECLFW(M353Write) {
if (A & 0x80) {
EXPREGS[0] = (A >> 13) & 0x03;
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
} else {
if (A < 0xC000) {
MMC3_CMDWrite(A, V);
FixMMC3PRG(MMC3_cmd);
} else
FixMMC3PRG(MMC3_cmd);
} else
MMC3_IRQWrite(A, V);
}
}

72
src/boards/357.c
View File

@@ -38,66 +38,66 @@ static SFORMAT StateRegs[] =
{
{ &IRQCount, 4 | FCEUSTATE_RLSB, "IRQC" },
{ &IRQa, 4 | FCEUSTATE_RLSB, "IRQA" },
{ &dipswitch, 1, "DPSW" },
{ &dipswitch, 1, "DPSW" },
{ &preg, 4, "REG" },
{ 0 }
};
static void Sync(void) {
if (dipswitch == 0) {
/* SMB2J Mode */
setprg4(0x5000, 16);
setprg8(0x6000, preg[1] ? 0 : 2);
setprg8(0x8000, 1);
setprg8(0xa000, 0);
setprg8(0xc000, banks[preg[0]]);
setprg8(0xe000, preg[1] ? 8 : 10);
} else {
/* UNROM Mode */
setprg16(0x8000, outer_bank[dipswitch] | preg[2]);
setprg16(0xc000, outer_bank[dipswitch] | 7);
}
if (dipswitch == 0) {
/* SMB2J Mode */
setprg4(0x5000, 16);
setprg8(0x6000, preg[1] ? 0 : 2);
setprg8(0x8000, 1);
setprg8(0xa000, 0);
setprg8(0xc000, banks[preg[0]]);
setprg8(0xe000, preg[1] ? 8 : 10);
} else {
/* UNROM Mode */
setprg16(0x8000, outer_bank[dipswitch] | preg[2]);
setprg16(0xc000, outer_bank[dipswitch] | 7);
}
setchr8(0);
setmirror(dipswitch == 3 ? MI_H : MI_V);
setmirror(dipswitch == 3 ? MI_H : MI_V);
}
static DECLFW(M357WriteLo) {
switch (A & 0x71ff) {
case 0x4022: preg[0] = V & 7; Sync(); break;
case 0x4120: preg[1] = V & 1; Sync(); break;
}
switch (A & 0x71ff) {
case 0x4022: preg[0] = V & 7; Sync(); break;
case 0x4120: preg[1] = V & 1; Sync(); break;
}
}
static DECLFW(M357WriteIRQ) {
IRQa = V & 1;
if (!IRQa) {
IRQCount = 0;
X6502_IRQEnd(FCEU_IQEXT);
}
IRQa = V & 1;
if (!IRQa) {
IRQCount = 0;
X6502_IRQEnd(FCEU_IQEXT);
}
}
static DECLFW(M357WriteUNROM) {
preg[2] = V & 7;
Sync();
preg[2] = V & 7;
Sync();
}
static void M357Power(void) {
preg[0] = 0;
preg[1] = 0;
IRQa = IRQCount = 0;
preg[0] = 0;
preg[1] = 0;
IRQa = IRQCount = 0;
Sync();
SetReadHandler(0x5000, 0xffff, CartBR);
SetWriteHandler(0x4022, 0x4022, M357WriteLo);
SetWriteHandler(0x4120, 0x4120, M357WriteLo);
SetWriteHandler(0x4122, 0x4122, M357WriteIRQ);
SetWriteHandler(0x8000, 0xffff, M357WriteUNROM);
SetWriteHandler(0x4120, 0x4120, M357WriteLo);
SetWriteHandler(0x4122, 0x4122, M357WriteIRQ);
SetWriteHandler(0x8000, 0xffff, M357WriteUNROM);
}
static void M357Reset(void) {
IRQa = IRQCount = 0;
dipswitch++;
dipswitch &= 3;
Sync();
IRQa = IRQCount = 0;
dipswitch++;
dipswitch &= 3;
Sync();
}
static void FP_FASTAPASS(1) M357IRQHook(int a) {

14
src/boards/359.c
View File

@@ -149,13 +149,13 @@ static void M359Power(void) {
}
static void FP_FASTAPASS(1) M359CPUHook(int a) {
if (!irqPA12) {
if (IRQa && IRQCount16) {
IRQCount16 -= a;
if (IRQCount16 <= 0)
X6502_IRQBegin(FCEU_IQEXT);
}
}
if (!irqPA12) {
if (IRQa && IRQCount16) {
IRQCount16 -= a;
if (IRQCount16 <= 0)
X6502_IRQBegin(FCEU_IQEXT);
}
}
}
static void M359IRQHook(void) {

30
src/boards/360.c
View File

@@ -26,33 +26,33 @@ static uint8 dipswitch;
static SFORMAT StateRegs[] =
{
{ &dipswitch, 1, "DPSW" },
{ &dipswitch, 1, "DPSW" },
{ 0 }
};
static void Sync(void) {
/* dip 0 and 1 is the same game SMB) */
if (dipswitch < 2)
setprg32(0x8000, dipswitch >> 1);
else {
setprg16(0x8000, dipswitch);
setprg16(0xC000, dipswitch);
}
setchr8(dipswitch);
setmirror(((dipswitch & 0x10) >> 4) ^ 1);
/* dip 0 and 1 is the same game SMB) */
if (dipswitch < 2)
setprg32(0x8000, dipswitch >> 1);
else {
setprg16(0x8000, dipswitch);
setprg16(0xC000, dipswitch);
}
setchr8(dipswitch);
setmirror(((dipswitch & 0x10) >> 4) ^ 1);
}
static void M360Power(void) {
dipswitch = 0;
dipswitch = 0;
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0XFFFF, CartBW);
SetWriteHandler(0x8000, 0XFFFF, CartBW);
}
static void M360Reset(void) {
dipswitch = (dipswitch + 1) & 31;
Sync();
FCEU_printf("dipswitch = %d\n", dipswitch);
dipswitch = (dipswitch + 1) & 31;
Sync();
FCEU_printf("dipswitch = %d\n", dipswitch);
}
static void StateRestore(int version) {

4
src/boards/372.c
View File

@@ -38,8 +38,8 @@ static void M372CW(uint32 A, uint8 V) {
else if (EXPREGS[2])
NV &= 0; /* hack ;( don't know exactly how it should be */
NV |= EXPREGS[0] | ((EXPREGS[2] & 0xF0) << 4);
if (EXPREGS[2] & 0x20)
setchr1r(0x10, A, V);
if (EXPREGS[2] & 0x20)
setchr1r(0x10, A, V);
else
setchr1(A, NV);
} else

92
src/boards/382.c
View File

@@ -31,68 +31,68 @@ static uint8 mirr;
static uint8 lock;
static SFORMAT StateRegs[] = {
{ &preg[0], 1, "PRG0" },
{ &preg[1], 1, "PRG1" },
{ &mode, 1, "MODE" },
{ &mirr, 1, "MIRR" },
{ &lock, 1, "LOCK" },
{ 0 }
{ &preg[0], 1, "PRG0" },
{ &preg[1], 1, "PRG1" },
{ &mode, 1, "MODE" },
{ &mirr, 1, "MIRR" },
{ &lock, 1, "LOCK" },
{ 0 }
};
static void Sync(void) {
switch (mode) {
case 1:
/* bnrom */
setprg32(0x8000, (preg[1] << 2) | (preg[0] & 3));
break;
default:
/* unrom */
setprg16(0x8000, (preg[1] << 3) | (preg[0] & 7));
setprg16(0xC000, (preg[1] << 3) | 7);
break;
}
setchr8(0);
setmirror(mirr ^ 1);
/* FCEU_printf("inB[0]:%02x outB[1]:%02x mode:%02x mirr:%02x lock:%02x\n", preg[0], preg[1], mode, mirr, lock); */
switch (mode) {
case 1:
/* bnrom */
setprg32(0x8000, (preg[1] << 2) | (preg[0] & 3));
break;
default:
/* unrom */
setprg16(0x8000, (preg[1] << 3) | (preg[0] & 7));
setprg16(0xC000, (preg[1] << 3) | 7);
break;
}
setchr8(0);
setmirror(mirr ^ 1);
/* FCEU_printf("inB[0]:%02x outB[1]:%02x mode:%02x mirr:%02x lock:%02x\n", preg[0], preg[1], mode, mirr, lock); */
}
static DECLFW(M382Write) {
if (!lock) {
preg[1] = (A & 0x07);
mode = (A & 0x08) >> 3;
mirr = (A & 0x10) >> 4;
lock = (A & 0x20) >> 5;
}
/* inner bank subject to bus conflicts */
preg[0] = V & CartBR(A);
Sync();
if (!lock) {
preg[1] = (A & 0x07);
mode = (A & 0x08) >> 3;
mirr = (A & 0x10) >> 4;
lock = (A & 0x20) >> 5;
}
/* inner bank subject to bus conflicts */
preg[0] = V & CartBR(A);
Sync();
}
static void M382Power(void) {
preg[0] = preg[1] = 0;
mode = 0;
mirr = 0;
lock = 0;
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0xFFFF, M382Write);
preg[0] = preg[1] = 0;
mode = 0;
mirr = 0;
lock = 0;
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0xFFFF, M382Write);
}
static void M382Reset(void) {
preg[1] = 0;
mode = 0;
mirr = 0;
lock = 0;
Sync();
preg[1] = 0;
mode = 0;
mirr = 0;
lock = 0;
Sync();
}
static void StateRestore(int version) {
Sync();
Sync();
}
void Mapper382_Init(CartInfo* info) {
info->Power = M382Power;
info->Reset = M382Reset;
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
info->Power = M382Power;
info->Reset = M382Reset;
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
}

64
src/boards/390.c
View File

@@ -28,56 +28,56 @@ static uint8 dipswitch;
static SFORMAT StateRegs[] =
{
{ &regs, 2, "REG" },
{ &dipswitch, 1, "DPSW" },
{ &dipswitch, 1, "DPSW" },
{ 0 }
};
static void Sync(void) {
switch ((regs[1] >> 4) & 3) {
case 0:
case 1:
/* UNROM */
setprg16(0x8000, regs[1]);
setprg16(0xC000, regs[1] | 7);
break;
case 2:
/* Maybe unused, NROM-256? */
setprg32(0x8000, regs[1] >> 1);
break;
case 3:
/* NROM-128 */
setprg16(0x8000, regs[1]);
setprg16(0xC000, regs[1]);
break;
}
setchr8(regs[0]);
setmirror(((regs[0] & 0x20) >> 5) ^ 1);
switch ((regs[1] >> 4) & 3) {
case 0:
case 1:
/* UNROM */
setprg16(0x8000, regs[1]);
setprg16(0xC000, regs[1] | 7);
break;
case 2:
/* Maybe unused, NROM-256? */
setprg32(0x8000, regs[1] >> 1);
break;
case 3:
/* NROM-128 */
setprg16(0x8000, regs[1]);
setprg16(0xC000, regs[1]);
break;
}
setchr8(regs[0]);
setmirror(((regs[0] & 0x20) >> 5) ^ 1);
}
static DECLFR(M390Read) {
uint8 ret = CartBR(A);
if ((regs[1] & 0x30) == 0x10)
ret |= dipswitch;
return ret;
uint8 ret = CartBR(A);
if ((regs[1] & 0x30) == 0x10)
ret |= dipswitch;
return ret;
}
static DECLFW(M390Write) {
regs[(A >> 14) & 1] = A & 0x3F;
Sync();
regs[(A >> 14) & 1] = A & 0x3F;
Sync();
}
static void M390Power(void) {
regs[0] = 0;
regs[1] = 0;
dipswitch = 11; /* hard-coded 150-in-1 menu */
regs[0] = 0;
regs[1] = 0;
dipswitch = 11; /* hard-coded 150-in-1 menu */
Sync();
SetReadHandler(0x8000, 0xffff, M390Read);
SetWriteHandler(0x8000, 0xffff, M390Write);
SetWriteHandler(0x8000, 0xffff, M390Write);
}
static void M390Reset(void) {
dipswitch = 11; /* hard-coded 150-in-1 menu */
Sync();
dipswitch = 11; /* hard-coded 150-in-1 menu */
Sync();
}
static void StateRestore(int version) {

18
src/boards/516.c
View File

@@ -25,27 +25,27 @@
static void M516CW(uint32 A, uint8 V) {
/* FCEU_printf("CHR: A:%04x V:%02x R0:%02x\n", A, V, EXPREGS[0]); */
setchr1(A, (V & 0x7F) | ((EXPREGS[0] << 5) & 0x180));
setchr1(A, (V & 0x7F) | ((EXPREGS[0] << 5) & 0x180));
}
static void M516PW(uint32 A, uint8 V) {
/* FCEU_printf("PRG: A:%04x V:%02x R0:%02x\n", A, V, EXPREGS[0]); */
setprg8(A, (V & 0x0F) | ((EXPREGS[0] << 4) & 0x30));
setprg8(A, (V & 0x0F) | ((EXPREGS[0] << 4) & 0x30));
}
static DECLFW(M516Write) {
/* FCEU_printf("Wr: A:%04x V:%02x R0:%02x\n", A, V, EXPREGS[0]); */
if (A & 0x10) {
EXPREGS[0] = A & 0xF;
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
}
MMC3_CMDWrite(A, V);
if (A & 0x10) {
EXPREGS[0] = A & 0xF;
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
}
MMC3_CMDWrite(A, V);
}
static void M516Power(void) {
EXPREGS[0] = 0;
GenMMC3Power();
GenMMC3Power();
SetWriteHandler(0x8000, 0xFFFF, M516Write);
}

26
src/boards/533.c
View File

@@ -30,13 +30,13 @@
static uint8 latche;
static SFORMAT StateRegs[] = {
{ &latche, 1, "LATC" },
{ 0 }
{ &latche, 1, "LATC" },
{ 0 }
};
static void Sync(void) {
setprg32(0x8000, 0);
setchr8((latche >> 4) & 1);
setprg32(0x8000, 0);
setchr8((latche >> 4) & 1);
}
static DECLFR(M533Read) {
@@ -44,23 +44,23 @@ static DECLFR(M533Read) {
}
static DECLFW(M533Write) {
latche = (V & CartBR(A));
Sync();
latche = (V & CartBR(A));
Sync();
}
static void M533Power(void) {
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBROB);
Sync();
SetReadHandler(0x8000, 0xFFFF, CartBROB);
SetReadHandler(0xE000, 0xEFFF, M533Read);
SetWriteHandler(0x8000, 0xFFFF, M533Write);
SetWriteHandler(0x8000, 0xFFFF, M533Write);
}
static void StateRestore(int version) {
Sync();
Sync();
}
void Mapper533_Init(CartInfo* info) {
info->Power = M533Power;
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
info->Power = M533Power;
GameStateRestore = StateRestore;
AddExState(&StateRegs, ~0, 0, 0);
}

63
src/boards/534.c
View File

@@ -25,60 +25,58 @@
static uint32 GetPRGBank(uint32 bank)
{
if (~bank & 1 && (MMC3_cmd & 0x40)) bank ^= 2;
if (~bank & 1 && (MMC3_cmd & 0x40)) bank ^= 2;
return (bank & 2) ? (0xFE | (bank & 1)) : DRegBuf[6 | (bank & 1)];
}
void SyncPRG_GNROM(int A14, int AND, int OR) {
setprg8(0x8000, ((GetPRGBank(0) & ~A14) & AND) | OR);
setprg8(0xA000, ((GetPRGBank(1) & ~A14) & AND) | OR);
setprg8(0xC000, ((GetPRGBank(0) | A14) & AND) | OR);
setprg8(0xE000, ((GetPRGBank(1) | A14) & AND) | OR);
setprg8(0x8000, ((GetPRGBank(0) & ~A14) & AND) | OR);
setprg8(0xA000, ((GetPRGBank(1) & ~A14) & AND) | OR);
setprg8(0xC000, ((GetPRGBank(0) | A14) & AND) | OR);
setprg8(0xE000, ((GetPRGBank(1) | A14) & AND) | OR);
}
static void M534PW(uint32 A, uint8 V) {
if (EXPREGS[0] & 0x40)
SyncPRG_GNROM(EXPREGS[3] & 0x02, 0x0F, ((EXPREGS[0] & 3) << 4));
else
setprg8(A, (V & 0x1F) | ((EXPREGS[0] & 0x2) << 4));
if (EXPREGS[0] & 0x40)
SyncPRG_GNROM(EXPREGS[3] & 0x02, 0x0F, ((EXPREGS[0] & 3) << 4));
else
setprg8(A, (V & 0x1F) | ((EXPREGS[0] & 0x2) << 4));
}
static void M534CW(uint32 A, uint8 V) {
setchr1(A, (V & 0xFF) | ((EXPREGS[2] & 0x0F) << 3) | ((EXPREGS[0] & 0x18) << 4));
setchr1(A, (V & 0xFF) | ((EXPREGS[2] & 0x0F) << 3) | ((EXPREGS[0] & 0x18) << 4));
}
static DECLFW(M534IRQWrite) {
MMC3_IRQWrite(0xC000 | (A & 1), V ^ 0xFF);
MMC3_IRQWrite(0xC000 | (A & 1), V ^ 0xFF);
}
static DECLFW(M534WriteLo) {
if ((A & 0x800) && (!(EXPREGS[3] & 0x80) || (A & 3) == 2)) {
EXPREGS[A & 3] = V;
FixMMC3CHR(MMC3_cmd);
FixMMC3PRG(MMC3_cmd);
}
if ((A & 0x800) && (!(EXPREGS[3] & 0x80) || (A & 3) == 2)) {
EXPREGS[A & 3] = V;
FixMMC3CHR(MMC3_cmd);
FixMMC3PRG(MMC3_cmd);
}
}
static void M534Power(void) {
EXPREGS[0] = 0x00;
EXPREGS[1] = 0x00;
EXPREGS[2] = 0x00;
EXPREGS[3] = 0x00;
GenMMC3Power();
SetWriteHandler(0x6000, 0x6FFF, M534WriteLo);
SetWriteHandler(0xC000, 0xDFFF, M534IRQWrite);
EXPREGS[0] = 0x00;
EXPREGS[1] = 0x00;
EXPREGS[2] = 0x00;
EXPREGS[3] = 0x00;
GenMMC3Power();
SetWriteHandler(0x6000, 0x6FFF, M534WriteLo);
SetWriteHandler(0xC000, 0xDFFF, M534IRQWrite);
}
static void M534Reset(void) {
EXPREGS[0] = 0x00;
EXPREGS[1] = 0x00;
EXPREGS[2] = 0x00;
EXPREGS[3] = 0x00;
EXPREGS[4] = (EXPREGS[4] + 1) & 7;
FCEU_printf("dipswitch = %d\n", EXPREGS[4]);
MMC3RegReset();
}
static void M534Close(void) {
EXPREGS[0] = 0x00;
EXPREGS[1] = 0x00;
EXPREGS[2] = 0x00;
EXPREGS[3] = 0x00;
EXPREGS[4] = (EXPREGS[4] + 1) & 7;
FCEU_printf("dipswitch = %d\n", EXPREGS[4]);
MMC3RegReset();
}
void Mapper534_Init(CartInfo *info) {
@@ -87,6 +85,5 @@ void Mapper534_Init(CartInfo *info) {
cwrap = M534CW;
info->Power = M534Power;
info->Reset = M534Reset;
info->Close = M534Close;
AddExState(EXPREGS, 5, 0, "EXPR");
}

90
src/boards/539.c
View File

@@ -26,67 +26,67 @@ static uint8 WRAM[8192];
static SFORMAT StateRegs[] =
{
{ &preg, 1, "PREG" },
{ &mirr, 1, "MIRR" }
{ &preg, 1, "PREG" },
{ &mirr, 1, "MIRR" }
};
static uint32 GetWRAMAddress(uint32 A) {
return ((A & 0x1FFF) |
((A < 0xC000) ? 0x1000 : 0x0000) |
((A < 0x8000) ? 0x0800 : 0x000));
return ((A & 0x1FFF) |
((A < 0xC000) ? 0x1000 : 0x0000) |
((A < 0x8000) ? 0x0800 : 0x000));
}
static void Sync(void) {
setprg8(0x6000, 13);
setprg8(0x8000, 12);
setprg8(0xA000, preg);
setprg8(0xC000, 14);
setprg8(0xE000, 15);
setchr8(0);
setmirror(((mirr & 8) >> 3) ^ 1);
setprg8(0x6000, 13);
setprg8(0x8000, 12);
setprg8(0xA000, preg);
setprg8(0xC000, 14);
setprg8(0xE000, 15);
setchr8(0);
setmirror(((mirr & 8) >> 3) ^ 1);
}
static DECLFR(M539Read) {
switch (A >> 8) {
case 0x60: case 0x62: case 0x64: case 0x65: case 0x82: case 0xC0: case 0xC1: case 0xC2:
case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7: case 0xC8: case 0xC9: case 0xCA:
case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF: case 0xD0: case 0xD1: case 0xDF:
return WRAM[GetWRAMAddress(A)];
default:
return CartBR(A);
}
switch (A >> 8) {
case 0x60: case 0x62: case 0x64: case 0x65: case 0x82: case 0xC0: case 0xC1: case 0xC2:
case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7: case 0xC8: case 0xC9: case 0xCA:
case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF: case 0xD0: case 0xD1: case 0xDF:
return WRAM[GetWRAMAddress(A)];
default:
return CartBR(A);
}
}
static DECLFW(M539Write) {
switch (A >> 8) {
case 0x60: case 0x62: case 0x64: case 0x65: case 0x82: case 0xC0: case 0xC1: case 0xC2:
case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7: case 0xC8: case 0xC9: case 0xCA:
case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF: case 0xD0: case 0xD1: case 0xDF:
WRAM[GetWRAMAddress(A)] = V;
break;
default:
switch (A & 0xF000) {
case 0xA000:
preg = V;
Sync();
break;
case 0xF000:
if ((A & 0x25) == 0x25) {
mirr = V;
Sync();
}
break;
}
break;
}
switch (A >> 8) {
case 0x60: case 0x62: case 0x64: case 0x65: case 0x82: case 0xC0: case 0xC1: case 0xC2:
case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7: case 0xC8: case 0xC9: case 0xCA:
case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF: case 0xD0: case 0xD1: case 0xDF:
WRAM[GetWRAMAddress(A)] = V;
break;
default:
switch (A & 0xF000) {
case 0xA000:
preg = V;
Sync();
break;
case 0xF000:
if ((A & 0x25) == 0x25) {
mirr = V;
Sync();
}
break;
}
break;
}
}
static void M539Power(void) {
preg = 0;
mirr = 0;
preg = 0;
mirr = 0;
Sync();
SetReadHandler(0x6000, 0xFFFF, M539Read);
SetWriteHandler(0x6000, 0xFFFF, M539Write);
SetWriteHandler(0x6000, 0xFFFF, M539Write);
}
static void StateRestore(int version) {
@@ -97,5 +97,5 @@ void Mapper539_Init(CartInfo *info) {
info->Power = M539Power;
GameStateRestore = StateRestore;
AddExState(WRAM, 8192, 0, "WRAM");
AddExState(&StateRegs, ~0, 0, 0);
AddExState(&StateRegs, ~0, 0, 0);
}

14
src/boards/datalatch.c
View File

@@ -153,13 +153,7 @@ static void CNROMSync(void) {
}
void CNROM_Init(CartInfo *info) {
unsigned _no_busc, _busc;
_busc = 1; /* by default, CNROM is set to emulate bus conflicts to all games */
_no_busc = 0;
if (GameInfo->cspecial == 1)
_no_busc = 1;
uint8 CNROM_busc = 1; /* by default, CNROM is set to emulate bus conflicts to all games */
/* TODO: move these to extended database when implemented. */
switch (info->CRC32) {
@@ -171,12 +165,10 @@ void CNROM_Init(CartInfo *info) {
case 0xe41b440f: /* Sidewinder (Joy Van) */
case 0xb0c871c5: /* Wei Lai Xiao Zi (Joy Van) */
case 0xb3be2f71: /* Yanshan Chess (Unl) */
_no_busc = 1;
CNROM_busc = 0;
break;
}
if (_no_busc == 1) _busc = 0;
Latch_Init(info, CNROMSync, 0, 0x8000, 0xFFFF, 1, _busc);
Latch_Init(info, CNROMSync, 0, 0x8000, 0xFFFF, 1, CNROM_busc);
}
/*------------------ Map 7 ---------------------------*/

99
src/boards/sachen.c
View File

@@ -36,105 +36,6 @@ static void S74LS374MSync(uint8 mirr) {
}
}
/* old mapper 150 and 243 */
/* static void S74LS374NSynco(void) {
setprg32(0x8000, latch[0]);
setchr8(latch[1] | latch[3] | latch[4]);
S74LS374MSync(latch[2]);
}
static DECLFW(S74LS374NWrite) {
A &= 0x4101;
if (A == 0x4100)
cmd = V & 7;
else {
switch (cmd) {
case 2: latch[0] = V & 1; latch[3] = (V & 1) << 3; break;
case 4: latch[4] = (V & 1) << 2; break;
case 5: latch[0] = V & 7; break;
case 6: latch[1] = V & 3; break;
case 7: latch[2] = V >> 1; break;
}
S74LS374NSynco();
}
}
static DECLFR(S74LS374NRead) {
uint8 ret;
if ((A & 0x4100) == 0x4100)
// ret=(X.DB&0xC0)|((~cmd)&0x3F);
ret = ((~cmd) & 0x3F) ^ dip;
else
ret = X.DB;
return ret;
}
static void S74LS374NPower(void) {
dip = 0;
latch[0] = latch[1] = latch[2] = latch[3] = latch[4] = 0;
S74LS374NSynco();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x4100, 0x7FFF, S74LS374NWrite);
SetReadHandler(0x4100, 0x5fff, S74LS374NRead);
}
static void S74LS374NReset(void) {
dip ^= 1;
latch[0] = latch[1] = latch[2] = latch[3] = latch[4] = 0;
S74LS374NSynco();
}
static void S74LS374NRestore(int version) {
S74LS374NSynco();
}
void S74LS374N_Init(CartInfo *info) {
info->Power = S74LS374NPower;
info->Reset = S74LS374NReset;
GameStateRestore = S74LS374NRestore;
AddExState(latch, 5, 0, "LATC");
AddExState(&cmd, 1, 0, "CMD");
AddExState(&dip, 1, 0, "DIP");
}
static void S74LS374NASynco(void) {
setprg32(0x8000, latch[0]);
setchr8(latch[1]);
S74LS374MSync(latch[2]);
}
static DECLFW(S74LS374NAWrite) {
A &= 0x4101;
if (A == 0x4100)
cmd = V & 7;
else {
switch (cmd) {
case 0: latch[0] = 0; latch[1] = 3; break;
case 2: latch[3] = (V & 1) << 3; break;
case 4: latch[1] = (latch[1] & 6) | (V & 3); break;
case 5: latch[0] = V & 1; break;
case 6: latch[1] = (latch[1] & 1) | latch[3] | ((V & 3) << 1); break;
case 7: latch[2] = V & 1; break;
}
S74LS374NASynco();
}
}
static void S74LS374NAPower(void) {
latch[0] = latch[2] = latch[3] = latch[4] = 0;
latch[1] = 3;
S74LS374NASynco();
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x4100, 0x7FFF, S74LS374NAWrite);
}
void S74LS374NA_Init(CartInfo *info) {
info->Power = S74LS374NAPower;
GameStateRestore = S74LS374NRestore;
AddExState(latch, 5, 0, "LATC");
AddExState(&cmd, 1, 0, "CMD");
}*/
static int type;
static void S8259Synco(void) {
int x;

82
src/boards/txcchip.c
View File

@@ -88,29 +88,29 @@ static uint8 TXC_CMDRead(void) {
static DECLFW(TXC_CMDWrite) {
if (A & 0x8000) {
if (txc.isJV001)
txc.output = (txc.accumulator & 0x0F) | (txc.inverter & 0xF0);
else
txc.output = (txc.accumulator & 0x0F) | ((txc.inverter << 1) & 0x10);
if (txc.isJV001)
txc.output = (txc.accumulator & 0x0F) | (txc.inverter & 0xF0);
else
txc.output = (txc.accumulator & 0x0F) | ((txc.inverter << 1) & 0x10);
} else {
switch (A & 0x103) {
case 0x100:
if (txc.increase)
txc.accumulator++;
else
txc.accumulator = ((txc.accumulator & ~txc.mask) | ((txc.staging ^ txc.invert) & txc.mask));
break;
case 0x101:
txc.invert = (V & 0x01) ? 0xFF : 0x00;
break;
case 0x102:
txc.staging = V & txc.mask;
txc.inverter = V & ~txc.mask;
break;
case 0x103:
txc.increase = ((V & 0x01) != 0);
break;
}
switch (A & 0x103) {
case 0x100:
if (txc.increase)
txc.accumulator++;
else
txc.accumulator = ((txc.accumulator & ~txc.mask) | ((txc.staging ^ txc.invert) & txc.mask));
break;
case 0x101:
txc.invert = (V & 0x01) ? 0xFF : 0x00;
break;
case 0x102:
txc.staging = V & txc.mask;
txc.inverter = V & ~txc.mask;
break;
case 0x103:
txc.increase = ((V & 0x01) != 0);
break;
}
}
txc.Y = !txc.invert || ((V & 0x10) != 0);
WSync();
@@ -149,14 +149,14 @@ static int CheckHash(CartInfo *info) {
uint64 partialmd5 = 0;
/* These carts do not work with new mapper implementation.
* This is a hack to use previous mapper implementation for such carts. */
* This is a hack to use previous mapper implementation for such carts. */
for (x = 0; x < 8; x++)
partialmd5 |= (uint64)info->MD5[15 - x] << (x * 8);
partialmd5 |= (uint64)info->MD5[15 - x] << (x * 8);
switch (partialmd5) {
case 0x2dd8f958850f21f4LL: /* Jin Gwok Sei Chuen Saang (Ch) [U][!] */
FCEU_printf(" WARNING: Using alternate mapper implementation.\n");
UNL22211_Init(info);
return 1;
FCEU_printf(" WARNING: Using alternate mapper implementation.\n");
UNL22211_Init(info);
return 1;
}
return 0;
}
@@ -178,7 +178,7 @@ static DECLFW(M36Write) {
static DECLFR(M36Read) {
uint8 ret = X.DB;
if ((A & 0x103) == 0x100)
ret = (X.DB & 0xCF) | ((TXC_CMDRead() << 4) & 0x30);
ret = (X.DB & 0xCF) | ((TXC_CMDRead() << 4) & 0x30);
return ret;
}
@@ -210,7 +210,7 @@ static DECLFW(M132Write) {
static DECLFR(M132Read) {
uint8 ret = X.DB;
if ((A & 0x103) == 0x100)
ret = ((X.DB & 0xF0) | (TXC_CMDRead() & 0x0F));
ret = ((X.DB & 0xF0) | (TXC_CMDRead() & 0x0F));
return ret;
}
@@ -232,9 +232,9 @@ void Mapper132_Init(CartInfo *info) {
static void M173Sync(void) {
setprg32(0x8000, 0);
if (CHRsize[0] > 0x2000)
setchr8(((txc.output & 0x01) | (txc.Y ? 0x02 : 0x00) | ((txc.output & 2) << 0x01)));
setchr8(((txc.output & 0x01) | (txc.Y ? 0x02 : 0x00) | ((txc.output & 2) << 0x01)));
else
setchr8(0);
setchr8(0);
}
void Mapper173_Init(CartInfo *info) {
@@ -258,7 +258,7 @@ static DECLFW(M136Write) {
static DECLFR(M136Read) {
uint8 ret = X.DB;
if ((A & 0x103) == 0x100)
ret = ((X.DB & 0xC0) | (TXC_CMDRead() & 0x3F));
ret = ((X.DB & 0xC0) | (TXC_CMDRead() & 0x3F));
return ret;
}
@@ -288,8 +288,8 @@ static DECLFW(M147Write) {
static DECLFR(M147Read) {
uint8 ret = X.DB;
if ((A & 0x103) == 0x100) {
uint8 value = TXC_CMDRead();
ret = ((value << 2) & 0xFC) | ((value >> 6) & 0x03);
uint8 value = TXC_CMDRead();
ret = ((value << 2) & 0xFC) | ((value >> 6) & 0x03);
}
return ret;
}
@@ -316,7 +316,7 @@ static void M172Sync(void) {
static uint8 GetValue(uint8 value) {
return (((value << 5) & 0x20) | ((value << 3) & 0x10) | ((value << 1) & 0x08) |
((value >> 1) & 0x04) | ((value >> 3) & 0x02) | ((value >> 5) & 0x01));
((value >> 1) & 0x04) | ((value >> 3) & 0x02) | ((value >> 5) & 0x01));
}
static DECLFW(M172Write) {
@@ -326,7 +326,7 @@ static DECLFW(M172Write) {
static DECLFR(M172Read) {
uint8 ret = X.DB;
if ((A & 0x103) == 0x100)
ret = (X.DB & 0xC0) | GetValue(TXC_CMDRead());
ret = (X.DB & 0xC0) | GetValue(TXC_CMDRead());
return ret;
}
@@ -356,10 +356,10 @@ static SFORMAT UNL22211StateRegs[] =
static void UNL22211Sync(void) {
setprg32(0x8000, (reg[2] >> 2) & 1);
if (is172)
setchr8((((cmd ^ reg[2]) >> 3) & 2) | (((cmd ^ reg[2]) >> 5) & 1)); /* 1991 DU MA Racing probably CHR bank sequence is WRONG, so it is possible to
* rearrange CHR banks for normal UNIF board and mapper 172 is unneccessary */
setchr8((((cmd ^ reg[2]) >> 3) & 2) | (((cmd ^ reg[2]) >> 5) & 1)); /* 1991 DU MA Racing probably CHR bank sequence is WRONG, so it is possible to
* rearrange CHR banks for normal UNIF board and mapper 172 is unneccessary */
else
setchr8(reg[2] & 3);
setchr8(reg[2] & 3);
}
static DECLFW(UNL22211WriteLo) {
@@ -377,9 +377,9 @@ static DECLFR(UNL22211ReadLo) {
return (reg[1] ^ reg[2]) | (is173 ? 0x01 : 0x40);
#if 0
if(reg[3])
return reg[2];
return reg[2];
else
return X.DB;
return X.DB;
#endif
}

5
src/ines-correct.h
View File

@@ -316,6 +316,11 @@
{0xd09f778d, 217, -1}, /* 9999999-in-1 (Static Splash, Alt Mapper)[p1][!] */
{0x62ef6c79, 232, 8}, /* Quattro Sports -Aladdin */
{0x2705eaeb, 234, -1}, /* Maxi 15 */
{0x80CBCACB, 235, -1}, /* 100-in-1 (Unl).nes */
{0x6175B9A0, 235, -1}, /* 150_in_1_199x-ASp */
{0x745A6791, 235, -1}, /* 210-in-1 and Contra 4-in-1 (212-in-1,212 Hong Kong,Reset Based)(Unl).nes */
{0xDF81364D, 235, -1}, /* 260-in-1 [p1][!].nes */
{0xA38F2F1D, 235, -1}, /* 1500-in-1.nes */
{0x6f12afc5, 235, -1}, /* Golden Game 150-in-1 */
{0x2537b3e6, 241, -1}, /* Dance Xtreme - Prima (Unl) */
{0x11611e89, 241, -1}, /* Darkseed (Unl) [p1] */

2
src/ines.c
View File

@@ -630,7 +630,7 @@ static BMAPPINGLocal bmap[] = {
{(uint8_t*)"BMC QUATTRO", 232, Mapper232_Init},
{(uint8_t*)"BMC 22+20-in-1 RST", 233, Mapper233_Init},
{(uint8_t*)"BMC MAXI", 234, Mapper234_Init},
{(uint8_t*)"", 235, Mapper235_Init},
{(uint8_t*)"Golden Game", 235, Mapper235_Init},
/* {(uint8_t*)"", 236, Mapper236_Init}, */
{(uint8_t*)"Teletubbies / Y2K", 237, Mapper237_Init},
{(uint8_t*)"UNL6035052", 238, UNL6035052_Init},

1
src/unif.c
View File

@@ -360,7 +360,6 @@ struct _unif_db {
static struct _unif_db unif_db[] = {
{ 0x8ebad077d08e6c78ULL, "A65AS", 1, -1 }, /* 3-in-1 (N080) [p1][U][!], not a real submapper */
{ 0x117181328eb1ad23ULL, "CNROM", 0, MI_H, NO_BUSC }, /* 75 Bingo (Sachen-English) [U] */
{ 0x616851e56946893bULL, "RESETNROM-XIN1", 0, MI_V }, /* Sheng Tian 2-in-1(Unl,ResetBase)[p1].unf */
{ 0x4cd729b5ae23a3cfULL, "RESETNROM-XIN1", 0, MI_H }, /* Sheng Tian 2-in-1(Unl,ResetBase)[p2].unf */