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M468: Cleanups and bugfixes

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This commit is contained in:
NewRisingSun
2023-01-03 01:01:38 +01:00
parent 07284ca4af
commit 03fd8fb1b8
4 changed files with 109 additions and 60 deletions
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58
src/boards/468_mmc1.h
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@@ -1,41 +1,40 @@
#define MMC1_reg regByte
#define MMC1_shift regByte[4]
#define MMC1_count regByte[5]
#define MMC1_filter regByte[6]
#define MMC1_reg regByte
#define MMC1_control regByte[0]
#define MMC1_chr0 regByte[1]
#define MMC1_chr1 regByte[2]
#define MMC1_prg regByte[3]
#define MMC1_shift regByte[4]
#define MMC1_count regByte[5]
#define MMC1_filter regByte[6]
static void MMC1_sync () {
int AND =prgAND >>1;
int OR =prgOR >>1 | (mapper &0x01? (MMC1_reg[1] &0x10): (mapperFlags &0x06));
if (MMC1_reg[0] &0x8) { /* 16 KiB mode */
if (MMC1_reg[0] &0x04) { /* OR logic */
setprg16(0x8000, MMC1_reg[3] &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
int OR =prgOR >>1 | (mapper &0x01? (MMC1_chr0 &0x10): (mapperFlags &0x06));
if (MMC1_control &0x08) { /* 16 KiB mode */
if (MMC1_control &0x04) { /* OR logic */
setprg16(0x8000, MMC1_prg &AND | OR &~AND);
setprg16(0xC000, 0xFF &AND | OR &~AND);
} else { /* AND logic */
setprg16(0x8000, 0x00 &AND | OR &~AND);
setprg16(0xC000, MMC1_reg[3] &AND | OR &~AND);
setprg16(0x8000, 0 &AND | OR &~AND);
setprg16(0xC000, MMC1_prg &AND | OR &~AND);
}
} else
setprg32(0x8000, (MMC1_reg[3] &AND | OR &~AND) >>1);
AND =mapper &0x01? 0x0F: 0x1F;
if (MMC1_reg[0] &0x10) { /* 4 KiB mode */
setchr4(0x0000, MMC1_reg[1] &AND);
setchr4(0x1000, MMC1_reg[2] &AND);
} else /* 8 KiB mode */
setchr8(MMC1_reg[1] >>1 &(AND >>1));
setprg32(0x8000, (MMC1_prg &AND | OR &~AND) >>1);
switch(MMC1_reg[0] &3) {
case 0: setmirror(MI_0); break;
case 1: setmirror(MI_1); break;
case 2: setmirror(MI_V); break;
case 3: setmirror(MI_H); break;
}
AND =mapper &0x01? 0x0F: 0x1F; /* SUROM needs to have the upper PRG bank bit, which is in the CHR registers, masked off */
if (MMC1_control &0x10) { /* 4 KiB mode */
setchr4(0x0000, MMC1_chr0 &AND);
setchr4(0x1000, MMC1_chr1 &AND);
} else /* 8 KiB mode */
setchr8(MMC1_chr0 >>1 &(AND >>1));
setmirror(MMC1_control &2? (MMC1_control &1? MI_H: MI_V): (MMC1_control &1? MI_1: MI_0));
}
static DECLFW(MMC1_writeReg) {
if (V &0x80) {
MMC1_shift =MMC1_count =0;
MMC1_reg[0] |=0x0C;
MMC1_control |=0x0C;
sync();
} else
if (!MMC1_filter) {
@@ -59,12 +58,15 @@ void MMC1_reset(uint8 clearRegs) {
MapIRQHook =MMC1_cpuCycle;
prgAND =mapperFlags &2? (mapperFlags &8? 0x07: 0x0F): 0x1F;
SetWriteHandler(0x8000, 0xFFFF, MMC1_writeReg);
if (clearRegs) MMC1_reg[0] =0x0C;
if (clearRegs) MMC1_control =0x0C;
sync();
}
#undef MMC1_reg
#undef MMC1_control
#undef MMC1_chr0
#undef MMC1_chr1
#undef MMC1_prg
#undef MMC1_shift
#undef MMC1_count
#undef MMC1_filter