226 lines
6.1 KiB
C
226 lines
6.1 KiB
C
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2022 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* BlazePro CPLD-based multicarts
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Unsolved issue: how is CHR RAM write-protection triggered?
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*/
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#include "mapinc.h"
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#include "state.h"
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static uint8 submapper;
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static uint8 eeprom[16], clock, state, command, output; /* Some strange serial EEPROM */
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static uint8 *WRAM;
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static uint32 WRAMSIZE;
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static int prevSFEXINDEX;
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extern int SFEXINDEX;
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extern SFORMAT SFMDATA[64];
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static uint8 mapper; /* 5700 MSB >>4 OR'd with submapper <<4 */
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static uint8 mapperFlags; /* 5700 LSB */
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static uint8 misc; /* 5601 */
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static uint8 misc2; /* 5702 */
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static void (*sync)();
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static uint16 prgOR;
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static uint8 prgAND;
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static uint8 regByte[16];
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static int16 regWord[9];
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#include "468_mmc1.h"
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#include "468_mmc24.h"
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#include "468_mmc3.h"
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#include "468_vrc1.h"
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#include "468_vrc24.h"
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#include "468_vrc3.h"
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#include "468_vrc6.h"
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#include "468_vrc7.h"
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#include "468_fme7.h"
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#include "468_discrete.h"
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#include "468_cnrom.h"
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#include "468_if12.h"
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#include "468_lf36.h"
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#include "468_nanjing.h"
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static SFORMAT stateRegs[] = {
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{ &mapper, 1, "SUP0" },
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{ &mapperFlags, 1, "SUP1" },
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{ &misc, 1, "SUP2" },
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{ &misc2, 1, "SUP3" },
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{ &prgOR, 2, "SUP4" },
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{ &prgAND, 1, "SUP5" },
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{ eeprom, 16,"EEPR" },
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{ &clock, 1, "EEP0" },
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{ &state, 1, "EEP1" },
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{ &command, 1, "EEP2" },
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{ &output, 1, "EEP3" },
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{ regByte, 16,"REGB" },
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{ regWord, 16,"REGW" },
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{ 0 }
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};
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void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */
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if (select)
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state =0;
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else
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if (!clock && newClock) {
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if (state <8) {
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command =command <<1 | newData*1;
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if (++state ==8 && (command &0xF0) !=0x50 && (command &0xF0) !=0xA0) state =0;
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} else {
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int mask =1 <<(15 -state);
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int address =command &0x0F;
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if ((command &0xF0) ==0xA0)
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eeprom[address] =eeprom[address] &~mask | newData*mask;
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else
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if ((command &0xF0) ==0x50)
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output =!!(eeprom[address] &mask);
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if (++state ==16) state =0;
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}
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}
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clock =newClock;
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}
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static DECLFR(readReg);
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static DECLFW(writeReg);
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static void setMapper(uint8 clearRegs) {
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int i;
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if (clearRegs) {
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for (i =0; i <16; i++) regByte[i] =0;
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for (i =0; i < 8; i++) regWord[i] =0;
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X6502_IRQEnd(FCEU_IQEXT);
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}
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SetReadHandler(0x5000, 0x5FFF, readReg);
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetWriteHandler(0x5000, 0x5FFF, writeReg);
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SetWriteHandler(0x6000, 0xFFFF, CartBW);
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MapIRQHook = NULL;
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PPU_hook = NULL;
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GameHBIRQHook = NULL;
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setprg8r(0x10, 0x6000, 0);
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switch(mapper) { /* 5700 MSB >>4 OR'd with submapper <<4 */
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case 0x00: case 0x01: case 0x32: MMC1_reset(clearRegs); break;
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case 0x0A: MMC2_reset(clearRegs); break;
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case 0x10: case 0x11: case 0x12: MMC3_reset(clearRegs); break;
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case 0x08: MMC4_reset(clearRegs); break;
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case 0x40: VRC1_reset(clearRegs); break;
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case 0x20: case 0x21: case 0x22: case 0x23: VRC24_reset(clearRegs); break;
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case 0x44: VRC3_reset(clearRegs); break;
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case 0x30: case 0x31: VRC6_reset(clearRegs); break;
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case 0x41: VRC7_reset(clearRegs); break;
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case 0x07: LF36_reset(clearRegs); break;
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case 0x50: FME7_reset(clearRegs); break;
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case 0x0E: case 0x1E: NANJING_reset(clearRegs); break;
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case 0x09: case 0x0B: case 0x17: case 0x37: UNROM_IF12_reset(clearRegs); break;
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case 0x04: case 0x06: case 0x14: case 0x16: ANROM_BNROM_reset(clearRegs); break;
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case 0x05: case 0x15: CNROM_BF9097_reset(clearRegs); break;
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case 0x0C: case 0x0D: case 0x1C: case 0x1D: GNROM_reset(clearRegs); break;
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default: break;
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}
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sync();
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}
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static DECLFR(readReg) {
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switch(A) {
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case 0x5301: case 0x5601:
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return output? 0x80: 0x00;
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default:
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return 0xFF;
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}
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}
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static DECLFW(writeReg) {
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switch(A) {
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case 0x5301:
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if (submapper ==0) setPins(!!(V &0x04), !!(V &0x02), !!(V &0x01));
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break;
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case 0x5601:
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if (~misc &0x80) {
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misc =V;
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if (submapper !=1) prgOR =prgOR &~0x2000 | V <<9 &0x2000;
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sync();
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}
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if (submapper ==1) setPins(!!(V &0x10), !!(V &0x02), !!(V &0x01));
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break;
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case 0x5700:
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mapper =V >>4 | submapper <<4;
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mapperFlags =V &0xF;
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prgOR =prgOR &~0x0010 | V <<4 &0x0010;
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setMapper(1);
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break;
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case 0x5701:
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prgOR =prgOR &~0x1FE0 | V <<5 &0x1FE0;
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sync();
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break;
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case 0x5702:
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if (submapper ==1) {
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misc2 =V;
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sync();
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}
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break;
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}
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}
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static void reset(void) {
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mapper =submapper <<4;
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mapperFlags =0x0F;
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misc =0;
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prgOR =0x7FF0;
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clock =command =output =1;
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command =state =0;
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setMapper(1);
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}
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static void power(void) {
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int i;
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for (i =0; i <16; i++) eeprom[i] =0;
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reset();
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}
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static void close(void) {
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if (WRAM)
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FCEU_gfree(WRAM);
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WRAM = NULL;
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}
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static void stateRestore(int version) {
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setMapper(0);
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}
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void Mapper468_Init(CartInfo *info) {
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submapper =info->submapper;
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info->Reset =reset;
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info->Power =power;
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info->Close =close;
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GameStateRestore =stateRestore;
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WRAMSIZE =8192;
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WRAM =(uint8*) FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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AddExState(stateRegs, ~0, 0, 0);
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prevSFEXINDEX =SFEXINDEX;
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}
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