303 lines
8.9 KiB
C
303 lines
8.9 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "asic_vrc2and4.h"
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#include "cartram.h"
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static void (*VRC24_cbSync)();
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static int VRC24_A0, VRC24_A1;
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static int (*VRC24_cbGetPRGBank)(uint8);
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static int (*VRC24_cbGetCHRBank)(uint8);
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static DECLFR((*VRC24_cbReadWRAM));
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static DECLFW((*VRC24_cbWriteWRAM));
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static DECLFW((*VRC24_cbExternalSelect));
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static uint8 VRC24_isVRC4; /* VRC2 or VRC4? VRC2 has no single-screen mirroring, no PRG A14 swap and no IRQ counter */
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static uint8 VRC24_useRepeatBit; /* Some VRC4 clones ignore the "repeat" bit in the IRQ Mode register */
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static uint8 VRC24_prg[2];
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static uint16 VRC24_chr[8];
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static uint8 VRC24_mirroring;
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static uint8 VRC24_misc;
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uint8 VRC2_pins; /* EEPROM interface */
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static uint8 VRC4_latch;
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static uint8 VRC4_mode;
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static uint8 VRC4_count;
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static signed short int VRC4_cycles;
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static SFORMAT VRC24_stateRegs[] = {
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{ VRC24_prg, 2, "VC2P" },
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{ &VRC24_chr[0], 2 | FCEUSTATE_RLSB, "V2C0" },
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{ &VRC24_chr[1], 2 | FCEUSTATE_RLSB, "V2C1" },
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{ &VRC24_chr[2], 2 | FCEUSTATE_RLSB, "V2C2" },
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{ &VRC24_chr[3], 2 | FCEUSTATE_RLSB, "V2C3" },
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{ &VRC24_chr[4], 2 | FCEUSTATE_RLSB, "V2C4" },
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{ &VRC24_chr[5], 2 | FCEUSTATE_RLSB, "V2C5" },
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{ &VRC24_chr[6], 2 | FCEUSTATE_RLSB, "V2C6" },
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{ &VRC24_chr[7], 2 | FCEUSTATE_RLSB, "V2C7" },
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{ &VRC24_mirroring, 1, "VC2N" },
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{ &VRC24_misc, 1, "VC4M" },
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{ 0 }
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};
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static SFORMAT VRC2_stateRegs[] = {
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{ &VRC2_pins, 1, "VC2E" },
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};
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static SFORMAT VRC4_stateRegs[] = {
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{ &VRC4_latch, 1, "V4LT" },
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{ &VRC4_mode, 1, "V4MO" },
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{ &VRC4_count, 1, "V4CT" },
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{ &VRC4_cycles, 2 | FCEUSTATE_RLSB, "V4CY" },
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{ 0 }
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};
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void VRC24_syncPRG (int AND, int OR) {
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setprg8(0x8000, VRC24_cbGetPRGBank(0) &AND | OR);
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setprg8(0xA000, VRC24_cbGetPRGBank(1) &AND | OR);
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setprg8(0xC000, VRC24_cbGetPRGBank(2) &AND | OR);
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setprg8(0xE000, VRC24_cbGetPRGBank(3) &AND | OR);
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}
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void VRC24_syncCHR (int AND, int OR) {
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setchr1(0x0000, VRC24_cbGetCHRBank(0) &AND | OR);
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setchr1(0x0400, VRC24_cbGetCHRBank(1) &AND | OR);
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setchr1(0x0800, VRC24_cbGetCHRBank(2) &AND | OR);
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setchr1(0x0C00, VRC24_cbGetCHRBank(3) &AND | OR);
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setchr1(0x1000, VRC24_cbGetCHRBank(4) &AND | OR);
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setchr1(0x1400, VRC24_cbGetCHRBank(5) &AND | OR);
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setchr1(0x1800, VRC24_cbGetCHRBank(6) &AND | OR);
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setchr1(0x1C00, VRC24_cbGetCHRBank(7) &AND | OR);
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}
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void VRC24_syncWRAM (int OR) {
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if (PRGsize[0x10]) setprg8r(0x10, 0x6000, OR);
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}
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int VRC24_getPRGBank (uint8 bank) {
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if (~bank &1 && VRC24_misc &2) bank ^= 2;
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return bank &2? (0xFE | bank &1): VRC24_prg[bank &1];
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}
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int VRC24_getCHRBank (uint8 bank) {
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return VRC24_chr[bank &7];
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}
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void VRC24_syncMirror () {
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setmirror(VRC24_isVRC4 && VRC24_mirroring &2? (VRC24_mirroring &1? MI_1: MI_0): (VRC24_mirroring &1? MI_H: MI_V));
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}
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DECLFR(VRC2_readMicrowire) {
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return VRC2_pins;
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}
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DECLFR(VRC24_readWRAM) {
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if (VRC24_misc &1 || !VRC24_isVRC4) {
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if (VRC24_cbReadWRAM)
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return VRC24_cbReadWRAM(A);
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else
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if (WRAMSize)
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CartBR(((A -0x6000) &(WRAMSize -1)) +0x6000);
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else
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return A >>8;
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} else
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return A >>8;
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}
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DECLFW(VRC2_writeMicrowire) {
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VRC2_pins = V;
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VRC24_cbSync();
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}
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DECLFW(VRC24_writeWRAM) {
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if (VRC24_misc &1 || !VRC24_isVRC4) {
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if (WRAMSize)
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CartBW(((A -0x6000) &(WRAMSize -1)) +0x6000, V);
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if (VRC24_cbWriteWRAM)
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VRC24_cbWriteWRAM(A, V);
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}
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}
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DECLFW(VRC24_writeReg) {
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unsigned int index, addr;
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addr = A &0xF000 | (A &VRC24_A0? 1: 0) | (A &VRC24_A1? 2: 0); /* address as the chip sees it */
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switch (addr &0xF000) {
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case 0x8000: case 0xA000:
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VRC24_prg[addr >>13 &1] = V;
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VRC24_cbSync();
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break;
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case 0x9000:
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if (!VRC24_isVRC4 || (addr &3) == 0) {
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VRC24_mirroring = V;
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VRC24_cbSync();
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} else
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if (VRC24_isVRC4 && (addr &3) == 2) {
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VRC24_misc = V;
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VRC24_cbSync();
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}
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if (VRC24_isVRC4 && (addr &3) == 3 && VRC24_cbExternalSelect) {
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VRC24_cbExternalSelect(A, V); /* Provide original address */
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}
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break;
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case 0xF000:
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if (VRC24_isVRC4) switch (addr &3) {
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case 0: VRC4_latch = VRC4_latch &0xF0 | V &0x0F; break;
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case 1: VRC4_latch = VRC4_latch &0x0F | V <<4; break;
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case 2: VRC4_mode = V;
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if (VRC4_mode &0x02) {
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VRC4_count = VRC4_latch;
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VRC4_cycles = 341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3: if (VRC24_useRepeatBit) VRC4_mode = VRC4_mode &~0x02 | VRC4_mode <<1 &0x02;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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break;
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default:
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index = (addr -0xB000) >>11 | addr >>1 &1;
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if (addr &1)
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VRC24_chr[index] = VRC24_chr[index] & 0x0F | V <<4;
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else
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VRC24_chr[index] = VRC24_chr[index] &~0x0F | V &0x0F;
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VRC24_cbSync();
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break;
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}
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}
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void FP_FASTAPASS(1) VRC4_cpuCycle (int a) {
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while (a--) {
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if (VRC4_mode &0x02 && (VRC4_mode &0x04 || (VRC4_cycles -= 3) <= 0)) {
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if (~VRC4_mode &0x04) VRC4_cycles += 341;
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if (!++VRC4_count) {
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VRC4_count = VRC4_latch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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}
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static void VRC24_clear() {
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VRC24_prg[0] = 0; VRC24_prg[1] = 0;
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VRC24_chr[0] = 0; VRC24_chr[1] = 1; VRC24_chr[2] = 2; VRC24_chr[3] = 3; VRC24_chr[4] = 4; VRC24_chr[5] = 5; VRC24_chr[6] = 6; VRC24_chr[7] = 7;
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VRC24_mirroring = VRC2_pins = VRC4_latch = VRC4_mode = VRC4_count = VRC4_cycles = 0;
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VRC24_misc = 1; /* Start with WRAM enabled */
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VRC24_cbSync();
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}
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static void VRC24_setHandlers () {
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if (VRC24_isVRC4 || WRAMSize) {
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SetReadHandler(0x6000, 0x7FFF, VRC24_readWRAM);
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SetWriteHandler(0x6000, 0x7FFF, VRC24_writeWRAM);
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} else {
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SetReadHandler(0x6000, 0x6FFF, VRC2_readMicrowire);
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SetWriteHandler(0x6000, 0x6FFF, VRC2_writeMicrowire);
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}
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x8000, 0xFFFF, VRC24_writeReg);
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if (VRC24_isVRC4) MapIRQHook = VRC4_cpuCycle;
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}
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static void VRC2_configure (void (*sync)(), int A0, int A1, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write))) {
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VRC24_cbSync = sync;
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VRC24_A0 = A0;
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VRC24_A1 = A1;
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VRC24_isVRC4 = 0;
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VRC24_cbGetPRGBank = prg? prg: VRC24_getPRGBank;
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VRC24_cbGetCHRBank = chr? chr: VRC24_getCHRBank;
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VRC24_cbReadWRAM = read;
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VRC24_cbWriteWRAM = write;
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}
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static void VRC4_configure (void (*sync)(), int A0, int A1, uint8 useRepeatBit, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write)), DECLFW((*externalSelect))) {
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VRC24_cbSync = sync;
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VRC24_A0 = A0;
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VRC24_A1 = A1;
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VRC24_isVRC4 = 1;
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VRC24_useRepeatBit = useRepeatBit;
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VRC24_cbGetPRGBank = prg? prg: VRC24_getPRGBank;
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VRC24_cbGetCHRBank = chr? chr: VRC24_getCHRBank;
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VRC24_cbReadWRAM = read;
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VRC24_cbWriteWRAM = write;
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VRC24_cbExternalSelect = externalSelect;
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}
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void VRC24_reconfigure(int A0, int A1) {
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VRC24_A0 = A0;
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VRC24_A1 = A1;
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}
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void VRC2_activate (uint8 clear, void (*sync)(), int A0, int A1, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write))) {
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VRC2_configure(sync, A0, A1, prg, chr, read, write);
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VRC24_setHandlers();
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if (clear)
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VRC24_clear();
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else
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VRC24_cbSync();
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}
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void VRC4_activate (uint8 clear, void (*sync)(), int A0, int A1, uint8 useRepeatBit, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write)), DECLFW((*externalSelect))) {
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VRC4_configure(sync, A0, A1, useRepeatBit, prg, chr, read, write, externalSelect);
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VRC24_setHandlers();
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if (clear)
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VRC24_clear();
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else
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VRC24_cbSync();
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}
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void VRC2_addExState () {
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AddExState(VRC24_stateRegs, ~0, 0, 0);
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AddExState(VRC2_stateRegs, ~0, 0, 0);
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}
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void VRC4_addExState () {
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AddExState(VRC24_stateRegs, ~0, 0, 0);
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AddExState(VRC4_stateRegs, ~0, 0, 0);
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}
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void VRC24_addExState () {
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AddExState(VRC24_stateRegs, ~0, 0, 0);
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AddExState(VRC2_stateRegs, ~0, 0, 0);
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AddExState(VRC4_stateRegs, ~0, 0, 0);
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}
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void VRC24_restore (int version) {
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VRC24_cbSync();
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}
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void VRC24_power () {
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VRC24_setHandlers();
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VRC24_clear();
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}
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void VRC2_init (CartInfo *info, void (*sync)(), int A0, int A1, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write))) {
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VRC2_addExState();
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VRC2_configure(sync, A0, A1, prg, chr, read, write);
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info->Power = VRC24_power;
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GameStateRestore = VRC24_restore;
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}
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void VRC4_init (CartInfo *info, void (*sync)(), int A0, int A1, uint8 useRepeatBit, int (*prg)(uint8), int (*chr)(uint8), DECLFR((*read)), DECLFW((*write)), DECLFW((*externalSelect))) {
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VRC4_addExState();
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VRC4_configure(sync, A0, A1, useRepeatBit, prg, chr, read, write, externalSelect);
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info->Power = VRC24_power;
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GameStateRestore = VRC24_restore;
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}
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