73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
#define MMC1_reg regByte
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#define MMC1_control regByte[0]
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#define MMC1_chr0 regByte[1]
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#define MMC1_chr1 regByte[2]
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#define MMC1_prg regByte[3]
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#define MMC1_shift regByte[4]
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#define MMC1_count regByte[5]
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#define MMC1_filter regByte[6]
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static void MMC1_sync () {
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int AND =prgAND >>1;
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int OR =prgOR >>1 | (mapper &0x01? (MMC1_chr0 &0x10): (mapperFlags &0x06));
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if (MMC1_control &0x08) { /* 16 KiB mode */
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if (MMC1_control &0x04) { /* OR logic */
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setprg16(0x8000, MMC1_prg &AND | OR &~AND);
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setprg16(0xC000, 0xFF &AND | OR &~AND);
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} else { /* AND logic */
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setprg16(0x8000, 0 &AND | OR &~AND);
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setprg16(0xC000, MMC1_prg &AND | OR &~AND);
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}
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} else
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setprg32(0x8000, (MMC1_prg &AND | OR &~AND) >>1);
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AND =mapper &0x01? 0x0F: 0x1F; /* SUROM needs to have the upper PRG bank bit, which is in the CHR registers, masked off */
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if (MMC1_control &0x10) { /* 4 KiB mode */
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setchr4(0x0000, MMC1_chr0 &AND);
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setchr4(0x1000, MMC1_chr1 &AND);
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} else /* 8 KiB mode */
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setchr8(MMC1_chr0 >>1 &(AND >>1));
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setmirror(MMC1_control &2? (MMC1_control &1? MI_H: MI_V): (MMC1_control &1? MI_1: MI_0));
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}
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static DECLFW(MMC1_writeReg) {
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if (V &0x80) {
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MMC1_shift =MMC1_count =0;
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MMC1_control |=0x0C;
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sync();
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} else
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if (!MMC1_filter) {
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MMC1_shift |=(V &1) <<MMC1_count++;
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if (MMC1_count ==5) {
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MMC1_reg[A >>13 &3] =MMC1_shift;
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MMC1_count =0;
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MMC1_shift =0;
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sync();
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}
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}
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MMC1_filter =2;
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}
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static void FP_FASTAPASS(1) MMC1_cpuCycle(int a) {
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while (a--) if (MMC1_filter) MMC1_filter--;
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}
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void MMC1_reset(uint8 clearRegs) {
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sync =MMC1_sync;
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MapIRQHook =MMC1_cpuCycle;
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prgAND =mapperFlags &2? (mapperFlags &8? 0x07: 0x0F): 0x1F;
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SetWriteHandler(0x8000, 0xFFFF, MMC1_writeReg);
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if (clearRegs) MMC1_control =0x0C;
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sync();
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}
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#undef MMC1_reg
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#undef MMC1_control
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#undef MMC1_chr0
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#undef MMC1_chr1
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#undef MMC1_prg
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#undef MMC1_shift
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#undef MMC1_count
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#undef MMC1_filter
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