228 lines
8.2 KiB
C
228 lines
8.2 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2020 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Multicarts based around the ING003C and TEC9719 enhanced MMC3 ASICs.
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ING003C's scanline counter is inverted from MMC3, while TEC9719 is normal.
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Both ASICs natively only support 256 KiB of CHR ROM/RAM; cartridges with more than that re-purpose higher PRG address as CHR address lines. There are two connection variants of this re-purposing.
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Mapper 422: TEC9719, CHR A18=PRG A20, CHR A19=PRG A21
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Mapper 126: TEC9719, CHR A18=PRG A21, CHR A19=PRG A20
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Mapper 534: ING003C, CHR A18=PRG A20, CHR A19=PRG A21
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Cartridges with more than one PRG ROM chip are sometimes not connected to form one continuous address space. Submappers are used to avoid having to repeat data to accomodate them.
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Submapper 0: Normal connection
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Submapper 1: PRG A21 (2 MiB bank) selects between two 1 MiB chips
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Submapper 2: Register bit 6001.2 (undocumented in data sheet) selects between two 1 MiB chips
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Both ASICs invert the register bit that selects PRG A21 (6000.5), hence "EXPREGS[0] ^0x20".
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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static uint8 reverseCHR_A18_A19;
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static uint8 invertC000;
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static uint8 SL0;
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static uint8 submapper;
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static uint8 getMMC3Bank(int bank) {
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if (~bank &1 && MMC3_cmd &0x40) bank ^=2;
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return bank &2? 0xFE | bank &1: DRegBuf[6 | bank &1];
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}
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static void wrapPRG(uint32 A, uint8 V) {
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int prgAND = EXPREGS[0] &0x40? 0x0F: 0x1F; /* 128 KiB or 256 KiB inner PRG bank selection */
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int prgOR =(EXPREGS[0] <<4 &0x70 | (EXPREGS[0] ^0x20) <<3 &0x180) &~prgAND; /* Outer PRG bank */
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if (submapper ==1) prgOR =prgOR &0x7F | prgOR >>1 &0x80; /* Submapper 1 uses PRG A21 as a chip select between two 1 MiB chips */
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if (submapper ==2) prgOR =prgOR &0x7F | EXPREGS[1] <<5 &0x80; /* Submapper 2 uses 6001.2 (not documented in datasheet) as a chip select between two 1 MiB chips */
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for (A =0; A <4; A++) {
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/* In UNROM-like mode (CT3=1, CT2=1, CT0=1), MMC3 sees A13=0 and A14=CPU A14 during reads, making register 6 apply from $8000-$BFFF, and the fixed bank from $C000-$FFFF.
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In NROM-128, NROM-256, ANROM and UNROM modes (CT0=1), MMC3 sees A13=0 and A14=0, making register 6 apply from $8000-$FFFF. */
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V =getMMC3Bank(A &((EXPREGS[3] &0x0D) ==0x0D? 2: EXPREGS[3] &0x01? 0: 3));
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/* UNROM and ANROM modes mean that MMC3 register 6 selects 16 and 32 KiB rather than 8 KiB banks. */
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if (EXPREGS[3] &0x08) switch(EXPREGS[3] &0x03) {
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case 0: V =V &3 | V <<1 &~3; break; /* PRG A14 appears twice */
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case 1: V =A &3 | V <<1 &~1; break; /* 16 KiB mode, bit 0 OR'd with CPU A14 */
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case 2: V =V &3 | V <<2 &~3; break; /* PRG A13 and PRG A14 appear twice */
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case 3: V =A &3 | V <<2 &~3; break; /* 32 KiB mode */
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} else
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if (EXPREGS[3] &0x01) { /* regular NROM modes */
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V =A &1 | V &~1;
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if (EXPREGS[3] &0x02) V =A &2 | V &~2; /* NROM-256 */
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}
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setprg8(0x8000 +A*0x2000, V &prgAND | prgOR &~prgAND);
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}
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mwrap(A000B); /* After 8000 write */
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}
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static void wrapCHR(uint32 A, uint8 V) {
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int chrAND = EXPREGS[0] &0x80? 0x7F: 0xFF; /* 128 KiB or 256 KiB innter CHR bank selection */
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int chrOR; /* outer CHR bank */
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if (reverseCHR_A18_A19) /* Mapper 126 swaps CHR A18 and A19 */
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chrOR =(EXPREGS[0] <<4 &0x080 | (EXPREGS[0] ^0x20) <<3 &0x100 | EXPREGS[0] <<5 &0x200) &~chrAND;
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else
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chrOR =((EXPREGS[0] ^0x20) <<4 &0x380 | EXPREGS[0] <<8 &0x400) &~chrAND;
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if (EXPREGS[3] &0x10) /* CNROM mode: 8 KiB inner CHR bank comes from outer bank register #2 */
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setchr8(EXPREGS[2] &(chrAND >>3) | (chrOR &~chrAND) >>3);
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else /* MMC3 CHR mode */
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setchr1(A, (V & chrAND) | chrOR);
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}
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static void wrapMirroring(uint8 V) {
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A000B =V;
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if (EXPREGS[3] &0x20) { /* ANROM mirroring */
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if (DRegBuf[6] &0x10)
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setmirror(MI_1);
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else
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setmirror(MI_0);
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} else
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if (EXPREGS[1] &0x02) { /* Extended MMC3 mirroring */
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switch(A000B &3) {
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case 0: setmirror(MI_V); break;
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case 1: setmirror(MI_H); break;
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case 2: setmirror(MI_0); break;
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case 3: setmirror(MI_1); break;
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}
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} else /* Normal MMC3 mirroring */
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setmirror(A000B &1? MI_H: MI_V);
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}
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static DECLFW(writeWRAM) {
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CartBW(A, V);
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if ((A &3) ==2) { /* CNROM Bank (D0-D3), Bank Enable (D4-D6) and Bank Enable Lock (D7) */
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int latchMask =0xFF &~(EXPREGS[2] &0x80? 0xF0: 0x00) &~(EXPREGS [2] >>3 &0x0E);
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EXPREGS[2] =EXPREGS[2] &~latchMask | V &latchMask;
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FixMMC3CHR(MMC3_cmd);
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} else
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if (~EXPREGS[3] &0x80) {
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/* Lock bit clear: Update any outer bank register */
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EXPREGS[A &3] =V;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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mwrap(A000B); /* After 6001 or 6003 write */
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}
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}
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static DECLFW(MMC3_CMDWriteA) { /* In mmc3.c, MMC3_cmd is updated *after* FixMMC3PRG is called, but we need MMC3_cmd in wrapPRG, so work around this problem until the MMC3 core is properly rewritten to actually make sense. */
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if ((A &0xE001) ==0x8000) {
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MMC3_cmd =V;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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} else
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MMC3_CMDWrite(A, V);
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}
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static DECLFW(writeCart) {
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if ((EXPREGS[3] &0x09) ==0x09) /* UNROM and ANROM modes treat all writes to $8000-$FFFF as if they were going to $8000-$9FFF */
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MMC3_CMDWriteA(0x8000 | (EXPREGS[3] &0x08? 1: A) &1, V); /* A0 substitution only looks at bit 3 of register 3 */
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else
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if (A >=0xC000)
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MMC3_IRQWrite(A, V ^(invertC000? 0xFF: 0x00)); /* Mapper 534 inverts the MMC3 scanline counter reload value */
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else
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MMC3_CMDWriteA(A, V);
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}
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static DECLFR(readPRG) {
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if (EXPREGS[1] &1) A =A &~1 | SL0 &1; /* Replace A0 with SL0 input */
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return CartBR(A);
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}
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static void reset(void) {
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SL0++; /* Soft-resetting cycles through SL0 settings */
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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MMC3RegReset();
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}
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static void power(void) {
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SL0 =0;
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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GenMMC3Power();
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SetWriteHandler(0x6000, 0x7FFF, writeWRAM);
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SetWriteHandler(0x8000, 0xFFFF, writeCart);
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SetReadHandler(0x8000, 0xFFFF, readPRG);
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}
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static void init(CartInfo *info) {
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GenMMC3_Init(info, 512, 256, 8, info->battery);
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cwrap =wrapCHR;
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pwrap =wrapPRG;
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mwrap =wrapMirroring;
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submapper =info->submapper;
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info->Power = power;
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info->Reset = reset;
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AddExState(EXPREGS, 4, 0, "EXPR");
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AddExState(&SL0, 1, 0, "DPSW");
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}
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void Mapper126_Init(CartInfo *info) {
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if (info->CRC32 ==0xEAD80031 || info->CRC32 ==0x6FCBC309) { /* Old dumps: Invert CHR A18 */
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int i, a, b;
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for (i =0; i <0x40000; i++) {
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a =VROM[0x00000 +i]; b =VROM[0x40000 +i];
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VROM[0x00000 +i] =b; VROM[0x40000 +i] =a;
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a =VROM[0x80000 +i]; b =VROM[0xC0000 +i];
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VROM[0x80000 +i] =b; VROM[0xC0000 +i] =a;
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}
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}
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reverseCHR_A18_A19 = 1;
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invertC000 = 0;
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init(info);
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}
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void Mapper422_Init(CartInfo *info) {
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if (info->CRC32 ==0x6D61FE21 || info->CRC32 ==0x3FF46175 || info->CRC32 ==0xA3FF9D9B || info->CRC32 ==0x2BDD0FC2 || info->CRC32 ==0x5789017D || info->CRC32 ==0x46A01871 || info->CRC32 ==0x2466B80A) {
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/* Old dumps: Invert CHR A19 */
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int i, a, b;
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for (i =0; i <0x80000; i++) {
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a =VROM[0x00000 +i]; b =VROM[0x80000 +i];
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VROM[0x00000 +i] =b; VROM[0x80000 +i] =a;
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}
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}
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reverseCHR_A18_A19 = 0;
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invertC000 = 0;
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init(info);
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}
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void Mapper534_Init(CartInfo *info) {
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if (info->CRC32 ==0x871CFD16) {
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/* Old dump: Invert PRG A20 */
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int i, a, b;
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for (i =0; i <0x100000; i++) {
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a =ROM[0x000000 +i]; b =ROM[0x100000 +i];
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ROM[0x000000 +i] =b; ROM[0x100000 +i] =a;
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}
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} else
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if (info->CRC32 ==0xB2724618 || info->CRC32 ==0x42A9219D) {
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/* Old dumps: Invert PRG A21 */
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int i, a, b;
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for (i =0; i <0x200000; i++) {
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a =ROM[0x000000 +i]; b =ROM[0x200000 +i];
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ROM[0x000000 +i] =b; ROM[0x200000 +i] =a;
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}
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}
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reverseCHR_A18_A19 = 0;
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invertC000 = 1;
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init(info);
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}
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