b09a060ae6
* Wii: Fix uninitialized save state size causing load state problems - Issue origially from Wii and possibly affects similar devices where retroarch and the core are one program. The problem was that the serialize size was not reset when you change game, causing the last serialized size to be carried over to the next game loaded causing save state issues due to change in size. Initializing this variable during retro_init() seems enough for most of the games. - In this same observation, also initialized some variables in a similar way. - also exluded a variable used for sound state that was added for smooth sound after load state which causes similar loading issues as well. - default sample rate has been lowered to 32K as well as to minimize some stuttering for these devices, while maintaining 48K sample rate for others. - Some comments are added to modified section as necessary. * Add workaround for save state issue in Wii with expansion audio - Some mappers are not loading states as well. Seems to affect those that are using expansion audio. some of these mappers(bandai, mmc5, namco106), the state variables has to be expanded so that it will load states fine with big endian while others (vrc6, vrc7 sunsoft), some variables that were added for smoother audio during load state has been removed. - This does not guarantee though that other mappers might not have similar incompatibilities after loading a state but so far, some of the most common roms in each mapper has been tested to load fine. * FDS: Expand state variables for big endian compatibility * FDS: Change OSD label from Disk 0 to Disk 1... when switching disks - Minor osd label change that now shows Disk 1 of (# of disks) instead of just Disk 0 Side nth.
401 lines
8.5 KiB
C
401 lines
8.5 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2009 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* VRC-6
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*
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*/
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#include "mapinc.h"
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static uint8 is26;
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static uint8 prg[2], chr[8], mirr;
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static uint8 IRQLatch, IRQa, IRQd;
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static int32 IRQCount, CycleCount;
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static uint8 *WRAM = NULL;
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static uint32 WRAMSIZE;
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static SFORMAT StateRegs[] =
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{
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{ prg, 2, "PRG" },
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{ chr, 8, "CHR" },
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{ &mirr, 1, "MIRR" },
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{ &IRQa, 1, "IRQA" },
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{ &IRQd, 1, "IRQD" },
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{ &IRQLatch, 1, "IRQL" },
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{ &IRQCount, 4, "IRQC" },
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{ &CycleCount, 4, "CYCC" },
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{ 0 }
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};
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static void(*sfun[3]) (void);
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static uint8 vpsg1[8];
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static uint8 vpsg2[4];
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static int32 cvbc[3];
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static int32 vcount[3];
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static int32 dcount[3];
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static int32 phaseacc;
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static SFORMAT SStateRegs[] =
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{
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{ vpsg1, 8, "PSG1" },
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{ vpsg2, 4, "PSG2" },
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/* Ignoring these sound state files for Wii since it causes states unable to load */
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#ifndef GEKKO
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/* rw - 2018-11-28 Added */
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{ &cvbc[0], 4 | FCEUSTATE_RLSB, "BC01" },
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{ &cvbc[1], 4 | FCEUSTATE_RLSB, "BC02" },
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{ &cvbc[2], 4 | FCEUSTATE_RLSB, "BC03" },
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{ &dcount[0], 4 | FCEUSTATE_RLSB, "DCT0" },
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{ &dcount[1], 4 | FCEUSTATE_RLSB, "DCT1" },
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{ &dcount[2], 4 | FCEUSTATE_RLSB, "DCT2" },
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{ &vcount[0], 4 | FCEUSTATE_RLSB, "VCT0" },
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{ &vcount[1], 4 | FCEUSTATE_RLSB, "VCT1" },
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{ &vcount[2], 4 | FCEUSTATE_RLSB, "VCT2" },
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{ &phaseacc, 4 | FCEUSTATE_RLSB, "ACCU" },
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#endif
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{ 0 }
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};
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static void Sync(void) {
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uint8 i;
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if (is26)
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setprg8r(0x10, 0x6000, 0);
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setprg16(0x8000, prg[0]);
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setprg8(0xc000, prg[1]);
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setprg8(0xe000, ~0);
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for (i = 0; i < 8; i++)
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setchr1(i << 10, chr[i]);
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switch (mirr & 3) {
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case 0: setmirror(MI_V); break;
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case 1: setmirror(MI_H); break;
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case 2: setmirror(MI_0); break;
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case 3: setmirror(MI_1); break;
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}
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}
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static DECLFW(VRC6SW) {
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A &= 0xF003;
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if (A >= 0x9000 && A <= 0x9002) {
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vpsg1[A & 3] = V;
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if (sfun[0]) sfun[0]();
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} else if (A >= 0xA000 && A <= 0xA002) {
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vpsg1[4 | (A & 3)] = V;
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if (sfun[1]) sfun[1]();
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} else if (A >= 0xB000 && A <= 0xB002) {
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vpsg2[A & 3] = V;
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if (sfun[2]) sfun[2]();
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}
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}
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static DECLFW(VRC6Write) {
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if (is26)
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A = (A & 0xFFFC) | ((A >> 1) & 1) | ((A << 1) & 2);
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if (A >= 0x9000 && A <= 0xB002) {
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VRC6SW(A, V);
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return;
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}
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switch (A & 0xF003) {
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case 0x8000: prg[0] = V; Sync(); break;
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case 0xB003: mirr = (V >> 2) & 3; Sync(); break;
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case 0xC000: prg[1] = V; Sync(); break;
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case 0xD000: chr[0] = V; Sync(); break;
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case 0xD001: chr[1] = V; Sync(); break;
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case 0xD002: chr[2] = V; Sync(); break;
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case 0xD003: chr[3] = V; Sync(); break;
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case 0xE000: chr[4] = V; Sync(); break;
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case 0xE001: chr[5] = V; Sync(); break;
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case 0xE002: chr[6] = V; Sync(); break;
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case 0xE003: chr[7] = V; Sync(); break;
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case 0xF000: IRQLatch = V; X6502_IRQEnd(FCEU_IQEXT); break;
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case 0xF001:
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IRQa = V & 2;
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IRQd = V & 1;
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if (V & 2)
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IRQCount = IRQLatch;
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CycleCount = 0;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xF002:
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IRQa = IRQd;
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X6502_IRQEnd(FCEU_IQEXT);
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}
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}
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static void VRC6Power(void) {
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Sync();
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetWriteHandler(0x6000, 0x7FFF, CartBW);
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SetWriteHandler(0x8000, 0xFFFF, VRC6Write);
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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}
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static void VRC6IRQHook(int a) {
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if (IRQa) {
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CycleCount += a * 3;
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while (CycleCount >= 341) {
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CycleCount -= 341;
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IRQCount++;
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if (IRQCount == 0x100) {
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IRQCount = IRQLatch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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}
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static void VRC6Close(void) {
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if (WRAM)
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FCEU_gfree(WRAM);
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WRAM = NULL;
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}
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static void StateRestore(int version) {
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Sync();
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}
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/* VRC6 Sound */
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static void DoSQV1(void);
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static void DoSQV2(void);
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static void DoSawV(void);
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static INLINE void DoSQV(int x) {
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int32 V;
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int32 amp = (((vpsg1[x << 2] & 15) << 8) * 6 / 8) >> 4;
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int32 start, end;
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start = cvbc[x];
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end = (SOUNDTS << 16) / soundtsinc;
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if (end <= start) return;
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cvbc[x] = end;
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if (vpsg1[(x << 2) | 0x2] & 0x80) {
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if (vpsg1[x << 2] & 0x80) {
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for (V = start; V < end; V++)
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Wave[V >> 4] += amp;
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} else {
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int32 thresh = (vpsg1[x << 2] >> 4) & 7;
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int32 freq = ((vpsg1[(x << 2) | 0x1] | ((vpsg1[(x << 2) | 0x2] & 15) << 8)) + 1) << 17;
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int32 dc = dcount[x];
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int32 vc = vcount[x];
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for (V = start; V < end; V++) {
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if (dc > thresh)
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Wave[V >> 4] += amp;
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vc -= nesincsize;
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while (vc <= 0) {
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vc += freq;
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dc = (dc + 1) & 15;
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}
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}
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vcount[x] = vc;
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dcount[x] = dc;
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}
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}
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}
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static void DoSQV1(void) {
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DoSQV(0);
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}
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static void DoSQV2(void) {
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DoSQV(1);
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}
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static void DoSawV(void) {
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int V;
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int32 start, end;
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start = cvbc[2];
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end = (SOUNDTS << 16) / soundtsinc;
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if (end <= start) return;
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cvbc[2] = end;
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if (vpsg2[2] & 0x80) {
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uint32 freq3;
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static uint32 duff = 0;
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freq3 = (vpsg2[1] + ((vpsg2[2] & 15) << 8) + 1);
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for (V = start; V < end; V++) {
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vcount[2] -= nesincsize;
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if (vcount[2] <= 0) {
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int32 t;
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rea:
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t = freq3;
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t <<= 18;
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vcount[2] += t;
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phaseacc += vpsg2[0] & 0x3f;
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dcount[2]++;
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if (dcount[2] == 7) {
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dcount[2] = 0;
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phaseacc = 0;
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}
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if (vcount[2] <= 0)
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goto rea;
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duff = (((phaseacc >> 3) & 0x1f) << 4) * 6 / 8;
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}
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Wave[V >> 4] += duff;
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}
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}
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}
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static INLINE void DoSQVHQ(int x) {
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int32 V;
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int32 amp = ((vpsg1[x << 2] & 15) << 8) * 6 / 8;
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if (vpsg1[(x << 2) | 0x2] & 0x80) {
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if (vpsg1[x << 2] & 0x80) {
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for (V = cvbc[x]; V < (int)SOUNDTS; V++)
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WaveHi[V] += amp;
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} else {
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int32 thresh = (vpsg1[x << 2] >> 4) & 7;
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int32 dc = dcount[x];
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int32 vc = vcount[x];
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for (V = cvbc[x]; V < (int)SOUNDTS; V++) {
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if (dc > thresh)
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WaveHi[V] += amp;
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vc--;
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if (vc <= 0) {
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vc = (vpsg1[(x << 2) | 0x1] | ((vpsg1[(x << 2) | 0x2] & 15) << 8)) + 1;
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dc = (dc + 1) & 15;
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}
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}
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dcount[x] = dc;
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vcount[x] = vc;
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}
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}
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cvbc[x] = SOUNDTS;
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}
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static void DoSQV1HQ(void) {
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DoSQVHQ(0);
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}
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static void DoSQV2HQ(void) {
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DoSQVHQ(1);
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}
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static void DoSawVHQ(void) {
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int32 V;
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if (vpsg2[2] & 0x80) {
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for (V = cvbc[2]; V < (int)SOUNDTS; V++) {
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WaveHi[V] += (((phaseacc >> 3) & 0x1f) << 8) * 6 / 8;
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vcount[2]--;
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if (vcount[2] <= 0) {
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vcount[2] = (vpsg2[1] + ((vpsg2[2] & 15) << 8) + 1) << 1;
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phaseacc += vpsg2[0] & 0x3f;
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dcount[2]++;
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if (dcount[2] == 7) {
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dcount[2] = 0;
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phaseacc = 0;
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}
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}
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}
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}
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cvbc[2] = SOUNDTS;
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}
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void VRC6Sound(int Count) {
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int x;
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DoSQV1();
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DoSQV2();
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DoSawV();
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for (x = 0; x < 3; x++)
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cvbc[x] = Count;
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}
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void VRC6SoundHQ(void) {
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DoSQV1HQ();
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DoSQV2HQ();
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DoSawVHQ();
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}
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void VRC6SyncHQ(int32 ts) {
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int x;
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for (x = 0; x < 3; x++) cvbc[x] = ts;
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}
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static void VRC6_ESI(void) {
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GameExpSound.RChange = VRC6_ESI;
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GameExpSound.Fill = VRC6Sound;
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GameExpSound.HiFill = VRC6SoundHQ;
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GameExpSound.HiSync = VRC6SyncHQ;
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phaseacc = 0;
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memset(cvbc, 0, sizeof(cvbc));
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memset(vcount, 0, sizeof(vcount));
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memset(dcount, 0, sizeof(dcount));
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if (FSettings.SndRate) {
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if (FSettings.soundq >= 1) {
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sfun[0] = DoSQV1HQ;
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sfun[1] = DoSQV2HQ;
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sfun[2] = DoSawVHQ;
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} else {
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sfun[0] = DoSQV1;
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sfun[1] = DoSQV2;
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sfun[2] = DoSawV;
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}
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} else
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memset(sfun, 0, sizeof(sfun));
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}
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/* VRC6 Sound */
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void Mapper24_Init(CartInfo *info) {
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is26 = 0;
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info->Power = VRC6Power;
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MapIRQHook = VRC6IRQHook;
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VRC6_ESI();
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GameStateRestore = StateRestore;
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AddExState(&StateRegs, ~0, 0, 0);
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AddExState(&SStateRegs, ~0, 0, 0);
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}
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void Mapper26_Init(CartInfo *info) {
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is26 = 1;
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info->Power = VRC6Power;
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info->Close = VRC6Close;
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MapIRQHook = VRC6IRQHook;
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VRC6_ESI();
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GameStateRestore = StateRestore;
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WRAMSIZE = 8192;
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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if (info->battery) {
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info->SaveGame[0] = WRAM;
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info->SaveGameLen[0] = WRAMSIZE;
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}
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AddExState(&StateRegs, ~0, 0, 0);
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AddExState(&SStateRegs, ~0, 0, 0);
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}
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void NSFVRC6_Init(void) {
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VRC6_ESI();
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SetWriteHandler(0x8000, 0xbfff, VRC6SW);
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AddExState(&SStateRegs, ~0, 0, 0);
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}
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