6359a0b36e
Audit pass 5 - five distinct cleanups bundled into one omnibus.
1. Element-stride byte-swapping for savestate fields (state.h, state.c,
fceu-endian.{h,c})
The SFORMAT 's' field was previously {bit 31 = RLSB, bits 0..30 =
byte size}. RLSB triggers FlipByteOrder() on MSB hosts, which
reverses the entire entry buffer end-to-end. That is correct for a
single primitive (size <= 8 bytes) but wrong for an array of
multi-byte primitives - reversing the whole buffer would swap
element 0 with element N-1 and reverse their bytes too, scrambling
the data.
The previous workaround was either splitting an N-element array
into N separate single-primitive entries with distinct chunk IDs
(n106 PlayIndex split into IDX0..IDX7) or skipping the entry
entirely on big-endian hosts (the GEKKO #ifndef in vrc6.c / vrc7.c).
Both approaches mean BE saves are not portable to LE and vice
versa, and force the same workaround at every new array site.
This pass adds proper stride support:
* SFORMAT 's' encoding is now {bit 31 = RLSB, bits 24..30 =
stride in bytes (0 = legacy/unset), bits 0..23 = byte size}.
16 MiB max size, well above any actual savestate field.
* FCEUSTATE_RLSB_ARRAY(stride) macro for the new pattern.
* FlipByteOrderStrided() byte-swaps each element of an array
independently. Round-trip identity verified: [01 00 00 00 ...]
-> [00 00 00 01 ...] -> [01 00 00 00 ...].
* state.c's SubWrite / ReadStateChunk / CheckS use new helpers
sf_size() / sf_stride() / sf_flip() that mask the size out of
the new bit layout and dispatch to the strided variant when
stride < size.
Backwards compatible: legacy single-primitive entries (size == 1,
2, 4, 8) leave the stride bits at zero, which sf_stride() reads
as "stride equals size" and falls through to FlipByteOrder() as
before. No on-disk format change. Existing single-primitive RLSB
sites are unchanged.
The infrastructure is now in place so any future SFORMAT entry
that is an array of multi-byte primitives can be expressed as a
single entry (e.g. "{ buf, sizeof(buf) | FCEUSTATE_RLSB_ARRAY(4),
"BUF." }") without splitting or skipping. The existing PlayIndex
split and GEKKO #ifndefs are intentionally left untouched -
migrating them would alter the on-disk savestate format and is a
separate decision.
2. iNES1-vs-iNES2 sizing helpers (cart.h)
Twelve sites across the codebase encoded the same conditional:
info->iNES2 ? (info->PRGRamSize + info->PRGRamSaveSize) : default
Sometimes for PRGRAM, sometimes for CHRRAM, sometimes in bytes,
sometimes after dividing by 1024. The pattern is verbose and easy
to write inconsistently.
Added two inline helpers in cart.h:
- CartInfo_PRGRAM_bytes(info, default_bytes)
- CartInfo_CHRRAM_bytes(info, default_bytes)
Migrated 9 of the 13 sites: cartram.c (2), 162.c, 163.c, 134.c,
399.c, 478.c, 480.c, 484.c. The remaining 4 are non-helper-fitting
variants (164.c special masking, 2 cartram SaveGameLen sites with
different fallback semantics, mmc3.c Boogerman submapper detection).
3. -Wundef enabled permanently (Makefile.libretro)
Zero warnings out of the box - no #if-on-undefined-macro footguns
in the codebase. Now part of WARNING_DEFINES alongside the existing
-Wsign-compare.
4. -Wmissing-prototypes enabled permanently (Makefile.libretro)
Started at 198 warnings, cleared all of them:
* Mass-static-ified ~96 functions across 75 files that were
defined non-static but only used within their own translation
unit. (See static_prototype_fixer.py in the development notes.)
* K&R-style empty-parens prototypes "()" replaced with explicit
"(void)" across all asic_*.{c,h} files - GCC treats "()" as
"any args" and refuses to match it against a separate K&R
definition.
* Added missing forward declarations to public headers:
- fds.h (FDSLoad)
- nsf.h (NSFLoad)
- ines.h (iNESLoad)
- unif.h (UNIFLoad)
- latch.h (LatchHardReset, K&R fix)
- eeprom_93Cx6.h (eeprom_93Cx6_read, K&R fix)
Each header gained an "#include "file.h"" where needed.
* fds_apu.c now includes its own fds_apu.h header (was missing).
* fds_apu.h: removed unused FDSSoundRead declaration (the function
is internal-static).
* cartram.h: removed unused CartRAM_close declaration (the function
is internal-static).
* input.h: added a centralised block of FCEU_Init* prototypes
(Zapper, Mouse, Powerpad, Arkanoid, VirtualBoy, FKB, SuborKB,
PEC586KB, HS, Mahjong, FamilyTrainerA/B, OekaKids, TopRider,
BarcodeWorld, BattleBox, QuizKing, FTrainerA/B, SpaceShadow,
LCDCompZapper, ArkanoidFC) plus FCEU_ZapperSetTolerance. These
were previously declared as "extern" inside src/input.c.
* Static-ified FP_FASTAPASS callbacks in 106.c, 65.c, 67.c,
asic_h3001.c, asic_vrc3.c (those with no external callers);
left non-static for those that have header decls or are
referenced from sibling .c files (asic_mmc1, asic_vrc6,
asic_vrc7, flashrom).
* For a small set of cross-file functions where adding a header
was disproportionate to the value (MMC5_hb, NSFMMC5_Close,
GetKeyboard, FCEU_GetJoyJoy), placed a forward declaration
immediately above the definition. This satisfies
-Wmissing-prototypes (which checks for any prior declaration
in scope) without churning the public-header layout.
5. -Wshadow partial cleanup (not enabled permanently)
Fixed five real shadows that were either bugs or actively
misleading:
* src/boards/476.c: removed an inner "int i" that shadowed the
outer loop counter.
* src/boards/mmc5.c MMC5_hb: parameter "scanline" renamed to
"sl_param" (was shadowing the global "scanline").
* src/boards/n106.c DoNamcoSound: parameter "Wave" renamed to
"WaveBuf" (was shadowing the global Wave audio buffer); also
updated the forward declaration and the matching parameter
on sound.h's NeoFill function pointer typedef.
* src/boards/vrc7.c UpdateOPLNEO: same Wave -> WaveBuf rename.
* src/ntsc/nes_ntsc_impl.h: renamed an inner loop counter "n"
that shadowed an outer "n".
* src/drivers/libretro/libretro.c FCEUD_RegionOverride: local
"pal" renamed to "is_pal" (was shadowing the typedef "pal" from
palette.h).
* src/palette.c FCEUI_SetPaletteArray: parameter "pal" renamed
to "data" (same shadow); driver.h declaration updated to match.
-Wshadow itself is NOT enabled permanently because the remaining
warnings are deliberate parameter naming conventions (XBuf in
draw functions, X in cpu hooks) and third-party blargg ntsc code.
In addition, four files were touched as part of an MSVC-build fix
that came up mid-pass: src/fds.c, src/nsf.c, src/ines.c, and
src/drivers/libretro/libretro_dipswitch.c had snprintf() calls
introduced in pass 4 that fail to link on pre-MSVC2015 toolchains
when STATIC_LINKING=1 (the libretro-common compat_snprintf.c shim
isn't compiled in those configurations). Replaced each snprintf with
either sprintf-into-bounded-buffer (the format strings have known
maximum output) or strlcpy/strlcat for the dipswitch key-build case.
All output is still bounded; truncation happens via strl*'s normal
truncation semantics where applicable.
All added code is C89-clean (top-of-block declarations only, no
mixed decls, no // comments, INLINE macro from fceu-types.h instead
of bare "inline"). Builds clean under -std=gnu11 with -Wno-write-
strings -Wsign-compare -Wundef -Wmissing-prototypes; zero errors,
zero warnings.
Determinism audit (audit_determinism.py): no rand/time/long
double/threads issues introduced.
803 lines
20 KiB
C
803 lines
20 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2002 Xodnizel
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* Copyright (C) 2005 CaH4e3
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* Copyright (C) 2019 Libretro Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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void (*sync)(void);
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static uint8_t allowExtendedMirroring;
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static uint8_t mode[4];
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static uint8_t* WRAM = NULL;
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static uint32_t WRAMSIZE;
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static uint8_t irqControl;
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static uint8_t irqEnabled;
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static uint8_t irqPrescaler;
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static uint8_t irqCounter;
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static uint8_t irqXor;
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static uint32_t lastPPUAddress;
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static uint8_t prg[4];
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static uint16_t chr[8];
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static uint16_t nt[4];
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static uint8_t latch[2];
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static uint8_t mul[2];
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static uint8_t adder;
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static uint8_t test;
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static uint8_t dipSwitch;
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static uint8_t submapper;
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static uint8_t cpuWriteHandlersSet;
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static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
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static SFORMAT JYASIC_stateRegs[] = {
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{ &irqControl, 1, "IRQM" },
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{ &irqPrescaler, 1, "IRQP" },
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{ &irqCounter, 1, "IRQC" },
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{ &irqXor, 1, "IRQX" },
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{ &irqEnabled, 1, "IRQA" },
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{ mul, 2, "MUL" },
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{ &test, 1, "REGI" },
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{ mode , 4, "TKCO" },
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{ prg, 4, "PRGB" },
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{ latch, 2, "CLTC" },
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{ chr, 8*2, "CHRB" },
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{ &nt[0], 2 | FCEUSTATE_RLSB, "NMS0" },
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{ &nt[1], 2 | FCEUSTATE_RLSB, "NMS1" },
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{ &nt[2], 2 | FCEUSTATE_RLSB, "NMS2" },
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{ &nt[3], 2 | FCEUSTATE_RLSB, "NMS3" },
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{ &dipSwitch, 1, "TEKR" },
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{ &adder, 1, "ADDE" },
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{ 0 }
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};
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static uint8_t rev (uint8_t val)
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{
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return ((val <<6) &0x40) | ((val <<4) &0x20) | ((val <<2) &0x10) | (val &0x08) | ((val >>2) &0x04) | ((val >>4) &0x02) | ((val >>6) &0x01);
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}
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static void syncPRG (int AND, int OR)
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{
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uint8_t prgLast =mode[0] &0x04? prg[3]: 0xFF;
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uint8_t prg6000 =0;
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switch (mode[0] &0x03)
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{
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case 0:
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setprg32(0x8000, prgLast &AND >>2 |OR >>2);
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prg6000 =prg[3] <<2 |3;
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break;
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case 1:
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setprg16(0x8000, prg[1] &AND >>1 |OR >>1);
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setprg16(0xC000, prgLast &AND >>1 |OR >>1);
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prg6000 =prg[3] <<1 |1;
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break;
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case 2:
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setprg8(0x8000, prg[0] &AND |OR);
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setprg8(0xA000, prg[1] &AND |OR);
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setprg8(0xC000, prg[2] &AND |OR);
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setprg8(0xE000, prgLast &AND |OR);
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prg6000 =prg[3];
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break;
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case 3:
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setprg8(0x8000, rev(prg[0]) &AND |OR);
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setprg8(0xA000, rev(prg[1]) &AND |OR);
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setprg8(0xC000, rev(prg[2]) &AND |OR);
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setprg8(0xE000, rev( prgLast) &AND |OR);
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prg6000 =rev(prg[3]);
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break;
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}
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if (mode[0] &0x80) /* Map ROM */
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setprg8 (0x6000, prg6000 &AND |OR);
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else
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if (WRAMSIZE) /* Otherwise map WRAM if it exists */
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setprg8r(0x10, 0x6000, 0);
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}
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static void syncCHR (int AND, int OR)
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{
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/* MMC4 mode[0] with 4 KiB CHR mode[0] */
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08)
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{
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int chrBank;
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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}
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else
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{
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int chrBank;
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switch(mode[0] &0x18)
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{
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case 0x00: /* 8 KiB CHR mode[0] */
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setchr8(chr[0] &AND >>3 | OR >>3);
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break;
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case 0x08: /* 4 KiB CHR mode[0] */
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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break;
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case 0x10:
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for (chrBank =0; chrBank <8; chrBank +=2)
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setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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break;
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case 0x18:
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for (chrBank =0; chrBank <8; chrBank +=1)
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setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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break;
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}
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}
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PPUCHRRAM = (mode[2] & 0x40) ? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
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}
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static void syncNT (int AND, int OR)
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{
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if (mode[0] &0x20 || mode[1] &0x08)
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{
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/* ROM nametables or extended mirroring */
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/* First, set normal CIRAM pages using extended registers ... */
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setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
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if (mode[0] &0x20)
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{
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int ntBank;
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for (ntBank =0; ntBank <4; ntBank++)
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{
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/* Then replace with ROM nametables if such are generally enabled */
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
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/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
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if (vromHere)
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setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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}
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}
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}
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else
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switch (mode[1] &0x03)
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{
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/* Regularly mirrored CIRAM */
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case 0:
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setmirror(MI_V);
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break;
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case 1:
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setmirror(MI_H);
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break;
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case 2:
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setmirror(MI_0);
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break;
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case 3:
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setmirror(MI_1);
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break;
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}
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}
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static void clockIRQ (void)
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{
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uint8_t mask =irqControl &0x04? 0x07: 0xFF;
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if (irqEnabled)
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switch (irqControl &0xC0)
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{
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case 0x40: {
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uint8_t newp = (irqPrescaler + 1) & mask;
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irqPrescaler = (irqPrescaler & ~mask) | newp;
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if (newp == 0x00 && (irqControl &0x08? irqCounter: ++irqCounter) ==0x00)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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}
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case 0x80: {
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uint8_t newp = (irqPrescaler - 1) & mask;
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irqPrescaler = (irqPrescaler & ~mask) | newp;
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if (newp == mask && (irqControl &0x08? irqCounter: --irqCounter) ==0xFF)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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}
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}
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}
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static DECLFW(trapCPUWrite)
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{
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if ((irqControl &0x03) ==0x03)
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clockIRQ(); /* Clock IRQ counter on CPU writes */
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cpuWriteHandlers[A](A, V);
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}
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32_t A)
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{
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if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A)
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{
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int i;
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for (i =0; i <2; i++)
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clockIRQ(); /* Clock IRQ counter on PPU "reads" */
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}
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0))
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{
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/* If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ... */
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latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); /* ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index. */
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sync();
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}
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lastPPUAddress =A;
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}
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static void ppuScanline(void)
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{
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if ((irqControl &0x03) ==0x01)
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{
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int i;
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for (i =0; i <8; i++)
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clockIRQ(); /* Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that. */
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}
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}
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static void FP_FASTAPASS(1) cpuCycle(int a)
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{
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if ((irqControl &0x03) ==0x00)
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while (a--)
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clockIRQ(); /* Clock IRQ counter on M2 cycles */
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}
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static DECLFR(readALU_DIP)
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{
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if ((A &0x3FF) ==0 && A !=0x5800) /* 5000, 5400, 5C00: read solder pad setting */
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return dipSwitch | X.DB &0x3F;
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if (A &0x800)
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switch (A &3)
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{
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/* 5800-5FFF: read ALU */
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case 0:
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return (mul[0] *mul[1]) &0xFF;
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case 1:
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return (mul[0] *mul[1]) >>8;
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case 2:
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return adder;
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case 3:
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return test;
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}
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/* all others */
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return X.DB;
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}
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static DECLFW(writeALU)
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{
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switch (A &3)
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{
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case 0:
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mul[0] =V;
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break;
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case 1:
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mul[1] =V;
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break;
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case 2:
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adder +=V;
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break;
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case 3:
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test = V;
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adder = 0;
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break;
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}
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}
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static DECLFW(writePRG)
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{
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prg[A &3] = V;
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sync();
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}
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static DECLFW(writeCHRLow)
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{
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chr[A &7] =chr[A &7] &0xFF00 | V;
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sync();
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}
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static DECLFW(writeCHRHigh)
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{
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chr[A &7] =chr[A &7] &0x00FF | V <<8;
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sync();
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}
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static DECLFW(writeNT)
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{
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if (~A &4)
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nt[A &3] =nt[A &3] &0xFF00 | V;
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else
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nt[A &3] =nt[A &3] &0x00FF | V <<8;
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sync();
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}
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static DECLFW(writeIRQ)
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{
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switch (A &7)
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{
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case 0:
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irqEnabled =!!(V &1);
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if (!irqEnabled)
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{
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irqPrescaler =0;
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X6502_IRQEnd(FCEU_IQEXT);
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}
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break;
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case 1:
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irqControl =V;
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break;
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case 2:
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irqEnabled =0;
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irqPrescaler =0;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3:
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irqEnabled =1;
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break;
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case 4:
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irqPrescaler =V ^irqXor;
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break;
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case 5:
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irqCounter =V ^irqXor;
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|
break;
|
|
case 6:
|
|
irqXor =V;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static DECLFW(writeMode)
|
|
{
|
|
switch (A &3)
|
|
{
|
|
case 0:
|
|
mode[0] =V;
|
|
if (!allowExtendedMirroring)
|
|
mode[0] &=~0x20;
|
|
break;
|
|
case 1:
|
|
mode[1] =V;
|
|
if (!allowExtendedMirroring)
|
|
mode[1] &=~0x08;
|
|
break;
|
|
case 2:
|
|
mode[2] =V;
|
|
break;
|
|
case 3:
|
|
mode[3] =V;
|
|
break;
|
|
}
|
|
sync();
|
|
}
|
|
|
|
static void JYASIC_restoreWriteHandlers(void)
|
|
{
|
|
int i;
|
|
if (cpuWriteHandlersSet)
|
|
{
|
|
for (i =0; i <0x10000; i++) SetWriteHandler(i, i, cpuWriteHandlers[i]);
|
|
cpuWriteHandlersSet =0;
|
|
}
|
|
}
|
|
|
|
static void JYASIC_power(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
SetWriteHandler(0x5000, 0x5FFF, writeALU);
|
|
SetWriteHandler(0x6000, 0x7fff, CartBW);
|
|
SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
|
|
SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
|
|
SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
|
|
SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
|
|
SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
|
|
SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
|
|
|
|
JYASIC_restoreWriteHandlers();
|
|
for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
|
|
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
|
|
cpuWriteHandlersSet =1;
|
|
|
|
SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
|
|
SetReadHandler(0x6000, 0xFFFF, CartBR);
|
|
|
|
mul[0] = mul[1] = adder = test = dipSwitch = 0;
|
|
mode[0] = mode[1] = mode[2] = mode[3] = 0;
|
|
irqControl =irqEnabled = irqPrescaler =irqCounter = irqXor = lastPPUAddress = 0;
|
|
memset(prg, 0, sizeof(prg));
|
|
memset(chr, 0, sizeof(chr));
|
|
memset(nt, 0, sizeof(nt));
|
|
latch[0] =0;
|
|
latch[1] =4;
|
|
|
|
sync();
|
|
}
|
|
|
|
static void JYASIC_reset (void)
|
|
{
|
|
dipSwitch = (dipSwitch +0x40) &0xC0;
|
|
}
|
|
|
|
static void JYASIC_close (void)
|
|
{
|
|
if (WRAM)
|
|
FCEU_gfree(WRAM);
|
|
WRAM = NULL;
|
|
}
|
|
|
|
static void JYASIC_restore (int version)
|
|
{
|
|
sync();
|
|
}
|
|
|
|
static void JYASIC_init (CartInfo *info)
|
|
{
|
|
cpuWriteHandlersSet =0;
|
|
info->Reset = JYASIC_reset;
|
|
info->Power = JYASIC_power;
|
|
info->Close = JYASIC_close;
|
|
PPU_hook = trapPPUAddressChange;
|
|
MapIRQHook = cpuCycle;
|
|
GameHBIRQHook2 = ppuScanline;
|
|
AddExState(JYASIC_stateRegs, ~0, 0, 0);
|
|
GameStateRestore = JYASIC_restore;
|
|
|
|
/* WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size */
|
|
if (info->iNES2)
|
|
WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize;
|
|
else
|
|
WRAMSIZE =info->mapper ==35? 8192: 0;
|
|
|
|
if (WRAMSIZE)
|
|
{
|
|
WRAM = (uint8_t*)FCEU_gmalloc(WRAMSIZE);
|
|
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
|
|
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
|
|
}
|
|
}
|
|
|
|
static void syncSingleCart (void)
|
|
{
|
|
syncPRG(0x3F, mode[3] <<5 &~0x3F);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
|
syncNT (0x1FF, mode[3] <<6 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
}
|
|
}
|
|
void Mapper35_Init(CartInfo *info)
|
|
{
|
|
/* Basically mapper 90/209/211 with WRAM */
|
|
allowExtendedMirroring =1;
|
|
sync =syncSingleCart;
|
|
JYASIC_init(info);
|
|
}
|
|
void Mapper90_Init(CartInfo *info)
|
|
{
|
|
/* Single cart, extended mirroring and ROM nametables disabled */
|
|
allowExtendedMirroring =0;
|
|
sync =syncSingleCart;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void Mapper209_Init(CartInfo *info)
|
|
{
|
|
/* Single cart, extended mirroring and ROM nametables enabled */
|
|
allowExtendedMirroring =1;
|
|
sync =syncSingleCart;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void Mapper211_Init(CartInfo *info)
|
|
{
|
|
/* Duplicate of mapper 209 */
|
|
allowExtendedMirroring =1;
|
|
sync =syncSingleCart;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync281 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<5);
|
|
syncCHR(0xFF, mode[3] <<8);
|
|
syncNT (0xFF, mode[3] <<8);
|
|
}
|
|
|
|
void Mapper281_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync281;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync282 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
|
syncNT (0x1FF, mode[3] <<6 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper282_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync282;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync295 (void)
|
|
{
|
|
syncPRG(0x0F, mode[3] <<4);
|
|
syncCHR(0x7F, mode[3] <<7);
|
|
syncNT (0x7F, mode[3] <<7);
|
|
}
|
|
|
|
void Mapper295_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync295;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync358 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper358_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync358;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync386 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper386_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync386;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync387(void)
|
|
{
|
|
syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper387_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync387;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync388 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<3 &0x60);
|
|
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<8 &0x200);
|
|
syncNT (0x1FF, mode[3] <<8 &0x200);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
|
}
|
|
}
|
|
|
|
void Mapper388_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =0;
|
|
sync =sync388;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync397 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
syncCHR(0x7F, mode[3] <<7);
|
|
syncNT (0x7F, mode[3] <<7);
|
|
}
|
|
|
|
void Mapper397_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync397;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync421 (void)
|
|
{
|
|
if (mode[3] &0x04)
|
|
syncPRG(0x3F, mode[3] <<4 &~0x3F);
|
|
else
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
syncCHR(0x1FF, mode[3] <<8 &0x300);
|
|
syncNT (0x1FF, mode[3] <<8 &0x300);
|
|
}
|
|
|
|
void Mapper421_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync421;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */
|
|
static uint8_t HSK007Reg[4];
|
|
static void sync394 (void) /* Called when J.Y. ASIC is active */
|
|
{
|
|
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x060;
|
|
int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<6 &0x100 | HSK007Reg[1] <<8 &0x200;
|
|
syncPRG(0x1F, prgOR);
|
|
syncCHR(0xFF, chrOR);
|
|
syncNT (0xFF, chrOR);
|
|
}
|
|
static void Mapper394_PWrap(uint32_t A, uint8_t V)
|
|
{
|
|
int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
|
|
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x060;
|
|
if (HSK007Reg[1] &0x08)
|
|
setprg8(A, V &prgAND | prgOR &~prgAND);
|
|
else
|
|
if (A ==0x8000)
|
|
setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2);
|
|
|
|
}
|
|
static void Mapper394_CWrap(uint32_t A, uint8_t V)
|
|
{
|
|
int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
|
|
int chrOR =submapper ==1? (HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x200 | HSK007Reg[1] <<6 &0x100): (HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x300);
|
|
setchr1(A, V &chrAND | chrOR &~chrAND);
|
|
}
|
|
static DECLFW(Mapper394_Write)
|
|
{
|
|
uint8_t oldMode =HSK007Reg[1];
|
|
A &=3;
|
|
HSK007Reg[A] =V;
|
|
if (A ==1)
|
|
{
|
|
if (~oldMode &0x10 && V &0x10) JYASIC_power();
|
|
if ( oldMode &0x10 && ~V &0x10)
|
|
{
|
|
JYASIC_restoreWriteHandlers();
|
|
GenMMC3Power();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (HSK007Reg[1] &0x10)
|
|
sync();
|
|
else
|
|
{
|
|
FixMMC3PRG(MMC3_cmd);
|
|
FixMMC3CHR(MMC3_cmd);
|
|
}
|
|
|
|
}
|
|
}
|
|
static void Mapper394_restore (int version)
|
|
{
|
|
int i;
|
|
JYASIC_restoreWriteHandlers();
|
|
if (HSK007Reg[1] &0x10)
|
|
{
|
|
SetWriteHandler(0x5000, 0x5FFF, writeALU);
|
|
SetWriteHandler(0x6000, 0x7fff, CartBW);
|
|
SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
|
|
SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
|
|
SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
|
|
SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
|
|
SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
|
|
SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
|
|
|
|
for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
|
|
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
|
|
cpuWriteHandlersSet =1;
|
|
|
|
SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
|
|
SetReadHandler(0x6000, 0xFFFF, CartBR);
|
|
sync();
|
|
}
|
|
else
|
|
{
|
|
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
|
|
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
|
|
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
|
FixMMC3PRG(MMC3_cmd);
|
|
FixMMC3CHR(MMC3_cmd);
|
|
}
|
|
}
|
|
static void Mapper394_power(void)
|
|
{
|
|
HSK007Reg[0] =0x00;
|
|
HSK007Reg[1] =0x0F;
|
|
HSK007Reg[2] =0x00;
|
|
HSK007Reg[3] =0x90;
|
|
irqEnabled =0;
|
|
GenMMC3Power();
|
|
SetWriteHandler(0x5000, 0x5FFF, Mapper394_Write);
|
|
}
|
|
|
|
void Mapper394_Init(CartInfo *info)
|
|
{
|
|
submapper =info->submapper;
|
|
allowExtendedMirroring =1;
|
|
sync =sync394;
|
|
JYASIC_init(info);
|
|
GenMMC3_Init(info, 128, 128, 0, 0);
|
|
pwrap =Mapper394_PWrap;
|
|
cwrap =Mapper394_CWrap;
|
|
info->Reset = Mapper394_power;
|
|
info->Power = Mapper394_power;
|
|
AddExState(HSK007Reg, 4, 0, "HSK ");
|
|
GameStateRestore = Mapper394_restore;
|
|
}
|