798 lines
19 KiB
C
798 lines
19 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2002 Xodnizel
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* Copyright (C) 2005 CaH4e3
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* Copyright (C) 2019 Libretro Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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void (*sync)(void);
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static uint8 allowExtendedMirroring;
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static uint8 mode[4];
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static uint8* WRAM = NULL;
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static uint32 WRAMSIZE;
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static uint8 irqControl;
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static uint8 irqEnabled;
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static uint8 irqPrescaler;
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static uint8 irqCounter;
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static uint8 irqXor;
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static uint32 lastPPUAddress;
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static uint8 prg[4];
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static uint16 chr[8];
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static uint16 nt[4];
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static uint8 latch[2];
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static uint8 mul[2];
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static uint8 adder;
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static uint8 test;
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static uint8 dipSwitch;
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static uint8 cpuWriteHandlersSet;
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static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
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static SFORMAT JYASIC_stateRegs[] = {
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{ &irqControl, 1, "IRQM" },
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{ &irqPrescaler, 1, "IRQP" },
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{ &irqCounter, 1, "IRQC" },
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{ &irqXor, 1, "IRQX" },
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{ &irqEnabled, 1, "IRQA" },
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{ mul, 2, "MUL" },
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{ &test, 1, "REGI" },
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{ mode , 4, "TKCO" },
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{ prg, 4, "PRGB" },
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{ latch, 2, "CLTC" },
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{ chr, 8*2, "CHRB" },
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{ &nt[0], 2 | FCEUSTATE_RLSB, "NMS0" },
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{ &nt[1], 2 | FCEUSTATE_RLSB, "NMS1" },
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{ &nt[2], 2 | FCEUSTATE_RLSB, "NMS2" },
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{ &nt[3], 2 | FCEUSTATE_RLSB, "NMS3" },
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{ &dipSwitch, 1, "TEKR" },
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{ &adder, 1, "ADDE" },
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{ 0 }
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};
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static uint8 rev (uint8_t val)
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{
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return ((val <<6) &0x40) | ((val <<4) &0x20) | ((val <<2) &0x10) | (val &0x08) | ((val >>2) &0x04) | ((val >>4) &0x02) | ((val >>6) &0x01);
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}
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static void syncPRG (int AND, int OR)
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{
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uint8_t prgLast =mode[0] &0x04? prg[3]: 0xFF;
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uint8_t prg6000 =0;
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switch (mode[0] &0x03)
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{
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case 0:
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setprg32(0x8000, prgLast &AND >>2 |OR >>2);
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prg6000 =prg[3] <<2 |3;
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break;
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case 1:
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setprg16(0x8000, prg[1] &AND >>1 |OR >>1);
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setprg16(0xC000, prgLast &AND >>1 |OR >>1);
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prg6000 =prg[3] <<1 |1;
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break;
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case 2:
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setprg8(0x8000, prg[0] &AND |OR);
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setprg8(0xA000, prg[1] &AND |OR);
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setprg8(0xC000, prg[2] &AND |OR);
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setprg8(0xE000, prgLast &AND |OR);
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prg6000 =prg[3];
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break;
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case 3:
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setprg8(0x8000, rev(prg[0]) &AND |OR);
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setprg8(0xA000, rev(prg[1]) &AND |OR);
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setprg8(0xC000, rev(prg[2]) &AND |OR);
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setprg8(0xE000, rev( prgLast) &AND |OR);
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prg6000 =rev(prg[3]);
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break;
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}
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if (mode[0] &0x80) /* Map ROM */
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setprg8 (0x6000, prg6000 &AND |OR);
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else
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if (WRAMSIZE) /* Otherwise map WRAM if it exists */
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setprg8r(0x10, 0x6000, 0);
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}
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static void syncCHR (int AND, int OR)
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{
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/* MMC4 mode[0] with 4 KiB CHR mode[0] */
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08)
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{
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int chrBank;
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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}
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else
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{
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int chrBank;
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switch(mode[0] &0x18)
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{
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case 0x00: /* 8 KiB CHR mode[0] */
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setchr8(chr[0] &AND >>3 | OR >>3);
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break;
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case 0x08: /* 4 KiB CHR mode[0] */
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for (chrBank =0; chrBank <8; chrBank +=4)
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setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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break;
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case 0x10:
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for (chrBank =0; chrBank <8; chrBank +=2)
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setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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break;
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case 0x18:
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for (chrBank =0; chrBank <8; chrBank +=1)
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setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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break;
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}
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}
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PPUCHRRAM = (mode[2] & 0x40) ? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
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}
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static void syncNT (int AND, int OR)
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{
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if (mode[0] &0x20 || mode[1] &0x08)
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{
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/* ROM nametables or extended mirroring */
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/* First, set normal CIRAM pages using extended registers ... */
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setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
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if (mode[0] &0x20)
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{
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int ntBank;
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for (ntBank =0; ntBank <4; ntBank++)
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{
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/* Then replace with ROM nametables if such are generally enabled */
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
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/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
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if (vromHere)
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setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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}
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}
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}
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else
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switch (mode[1] &0x03)
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{
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/* Regularly mirrored CIRAM */
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case 0:
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setmirror(MI_V);
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break;
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case 1:
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setmirror(MI_H);
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break;
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case 2:
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setmirror(MI_0);
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break;
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case 3:
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setmirror(MI_1);
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break;
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}
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}
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static void clockIRQ (void)
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{
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uint8_t mask =irqControl &0x04? 0x07: 0xFF;
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if (irqEnabled)
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switch (irqControl &0xC0)
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{
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case 0x40:
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irqPrescaler =(irqPrescaler &~mask) | (++irqPrescaler &mask);
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if ((irqPrescaler &mask) ==0x00 && (irqControl &0x08? irqCounter: ++irqCounter) ==0x00)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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case 0x80:
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irqPrescaler =(irqPrescaler &~mask) | (--irqPrescaler &mask);
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if ((irqPrescaler &mask) ==mask && (irqControl &0x08? irqCounter: --irqCounter) ==0xFF)
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X6502_IRQBegin(FCEU_IQEXT);
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break;
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}
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}
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static DECLFW(trapCPUWrite)
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{
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if ((irqControl &0x03) ==0x03)
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clockIRQ(); /* Clock IRQ counter on CPU writes */
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cpuWriteHandlers[A](A, V);
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}
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A)
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{
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if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A)
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{
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int i;
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for (i =0; i <2; i++)
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clockIRQ(); /* Clock IRQ counter on PPU "reads" */
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}
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0))
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{
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/* If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ... */
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latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); /* ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index. */
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sync();
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}
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lastPPUAddress =A;
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}
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static void ppuScanline(void)
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{
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if ((irqControl &0x03) ==0x01)
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{
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int i;
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for (i =0; i <8; i++)
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clockIRQ(); /* Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that. */
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}
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}
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static void FP_FASTAPASS(1) cpuCycle(int a)
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{
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if ((irqControl &0x03) ==0x00)
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while (a--)
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clockIRQ(); /* Clock IRQ counter on M2 cycles */
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}
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static DECLFR(readALU_DIP)
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{
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if ((A &0x3FF) ==0 && A !=0x5800) /* 5000, 5400, 5C00: read solder pad setting */
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return dipSwitch | X.DB &0x3F;
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if (A &0x800)
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switch (A &3)
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{
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/* 5800-5FFF: read ALU */
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case 0:
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return (mul[0] *mul[1]) &0xFF;
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case 1:
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return (mul[0] *mul[1]) >>8;
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case 2:
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return adder;
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case 3:
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return test;
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}
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/* all others */
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return X.DB;
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}
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static DECLFW(writeALU)
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{
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switch (A &3)
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{
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case 0:
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mul[0] =V;
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break;
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case 1:
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mul[1] =V;
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break;
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case 2:
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adder +=V;
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break;
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case 3:
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test = V;
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adder = 0;
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break;
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}
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}
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static DECLFW(writePRG)
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{
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prg[A &3] = V;
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sync();
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}
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static DECLFW(writeCHRLow)
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{
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chr[A &7] =chr[A &7] &0xFF00 | V;
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sync();
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}
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static DECLFW(writeCHRHigh)
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{
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chr[A &7] =chr[A &7] &0x00FF | V <<8;
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sync();
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}
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static DECLFW(writeNT)
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{
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if (~A &4)
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nt[A &3] =nt[A &3] &0xFF00 | V;
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else
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nt[A &3] =nt[A &3] &0x00FF | V <<8;
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sync();
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}
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static DECLFW(writeIRQ)
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{
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switch (A &7)
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{
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case 0:
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irqEnabled =!!(V &1);
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if (!irqEnabled)
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{
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irqPrescaler =0;
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X6502_IRQEnd(FCEU_IQEXT);
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}
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break;
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case 1:
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irqControl =V;
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break;
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case 2:
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irqEnabled =0;
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irqPrescaler =0;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3:
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irqEnabled =1;
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break;
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case 4:
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irqPrescaler =V ^irqXor;
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break;
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case 5:
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irqCounter =V ^irqXor;
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break;
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case 6:
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irqXor =V;
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break;
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}
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}
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static DECLFW(writeMode)
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{
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switch (A &3)
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{
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case 0:
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mode[0] =V;
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if (!allowExtendedMirroring)
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mode[0] &=~0x20;
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break;
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case 1:
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mode[1] =V;
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if (!allowExtendedMirroring)
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mode[1] &=~0x08;
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break;
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case 2:
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mode[2] =V;
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break;
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case 3:
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mode[3] =V;
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break;
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}
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sync();
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}
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static void JYASIC_restoreWriteHandlers(void)
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{
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int i;
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if (cpuWriteHandlersSet)
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{
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for (i =0; i <0x10000; i++) SetWriteHandler(i, i, cpuWriteHandlers[i]);
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cpuWriteHandlersSet =0;
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}
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}
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static void JYASIC_power(void)
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{
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unsigned int i;
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SetWriteHandler(0x5000, 0x5FFF, writeALU);
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SetWriteHandler(0x6000, 0x7fff, CartBW);
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SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
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SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
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SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
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SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
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SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
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SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
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JYASIC_restoreWriteHandlers();
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for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
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SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
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cpuWriteHandlersSet =1;
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SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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mul[0] = mul[1] = adder = test = dipSwitch = 0;
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mode[0] = mode[1] = mode[2] = mode[3] = 0;
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irqControl =irqEnabled = irqPrescaler =irqCounter = irqXor = lastPPUAddress = 0;
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memset(prg, 0, sizeof(prg));
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memset(chr, 0, sizeof(chr));
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memset(nt, 0, sizeof(nt));
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latch[0] =0;
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latch[1] =4;
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sync();
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}
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static void JYASIC_reset (void)
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{
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dipSwitch = (dipSwitch +0x40) &0xC0;
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}
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static void JYASIC_close (void)
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{
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if (WRAM)
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FCEU_gfree(WRAM);
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WRAM = NULL;
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}
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static void JYASIC_restore (int version)
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{
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sync();
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}
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void JYASIC_init (CartInfo *info)
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{
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cpuWriteHandlersSet =0;
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info->Reset = JYASIC_reset;
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info->Power = JYASIC_power;
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info->Close = JYASIC_close;
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PPU_hook = trapPPUAddressChange;
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MapIRQHook = cpuCycle;
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GameHBIRQHook2 = ppuScanline;
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AddExState(JYASIC_stateRegs, ~0, 0, 0);
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GameStateRestore = JYASIC_restore;
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/* WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size */
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if (info->iNES2)
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WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize;
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else
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WRAMSIZE =info->mapper ==35? 8192: 0;
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if (WRAMSIZE)
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{
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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}
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}
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static void syncSingleCart (void)
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{
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syncPRG(0x3F, mode[3] <<5 &~0x3F);
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if (mode[3] &0x20)
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{
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syncCHR(0x1FF, mode[3] <<6 &0x600);
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syncNT (0x1FF, mode[3] <<6 &0x600);
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}
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else
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{
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syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
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syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
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}
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}
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void Mapper35_Init(CartInfo *info)
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{
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/* Basically mapper 90/209/211 with WRAM */
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allowExtendedMirroring =1;
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sync =syncSingleCart;
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JYASIC_init(info);
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}
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void Mapper90_Init(CartInfo *info)
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{
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/* Single cart, extended mirroring and ROM nametables disabled */
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allowExtendedMirroring =0;
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sync =syncSingleCart;
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JYASIC_init(info);
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}
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void Mapper209_Init(CartInfo *info)
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{
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/* Single cart, extended mirroring and ROM nametables enabled */
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allowExtendedMirroring =1;
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sync =syncSingleCart;
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JYASIC_init(info);
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}
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void Mapper211_Init(CartInfo *info)
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{
|
|
/* Duplicate of mapper 209 */
|
|
allowExtendedMirroring =1;
|
|
sync =syncSingleCart;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync281 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<5);
|
|
syncCHR(0xFF, mode[3] <<8);
|
|
syncNT (0xFF, mode[3] <<8);
|
|
}
|
|
|
|
void Mapper281_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync281;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
static void sync282 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
|
syncNT (0x1FF, mode[3] <<6 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper282_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync282;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync295 (void)
|
|
{
|
|
syncPRG(0x0F, mode[3] <<4);
|
|
syncCHR(0x7F, mode[3] <<7);
|
|
syncNT (0x7F, mode[3] <<7);
|
|
}
|
|
|
|
void Mapper295_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync295;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync358 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper358_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync358;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync386 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper386_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync386;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync387(void)
|
|
{
|
|
syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20);
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
|
}
|
|
}
|
|
|
|
void Mapper387_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync387;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync388 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<3 &0x60);
|
|
|
|
if (mode[3] &0x20)
|
|
{
|
|
syncCHR(0x1FF, mode[3] <<8 &0x200);
|
|
syncNT (0x1FF, mode[3] <<8 &0x200);
|
|
}
|
|
else
|
|
{
|
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
|
}
|
|
}
|
|
|
|
void Mapper388_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =0;
|
|
sync =sync388;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync397 (void)
|
|
{
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
syncCHR(0x7F, mode[3] <<7);
|
|
syncNT (0x7F, mode[3] <<7);
|
|
}
|
|
|
|
void Mapper397_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync397;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
void sync421 (void)
|
|
{
|
|
if (mode[3] &0x04)
|
|
syncPRG(0x3F, mode[3] <<4 &~0x3F);
|
|
else
|
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
|
syncCHR(0x1FF, mode[3] <<8 &0x300);
|
|
syncNT (0x1FF, mode[3] <<8 &0x300);
|
|
}
|
|
|
|
void Mapper421_Init(CartInfo *info)
|
|
{
|
|
/* Multicart */
|
|
allowExtendedMirroring =1;
|
|
sync =sync421;
|
|
JYASIC_init(info);
|
|
}
|
|
|
|
/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */
|
|
static uint8 HSK007Reg[4];
|
|
void sync394 (void) /* Called when J.Y. ASIC is active */
|
|
{
|
|
int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
|
|
int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
|
|
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
|
|
int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
|
|
syncPRG(0x1F, prgOR);
|
|
syncCHR(0xFF, chrOR);
|
|
syncNT (0xFF, chrOR);
|
|
}
|
|
static void Mapper394_PWrap(uint32 A, uint8 V)
|
|
{
|
|
int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F;
|
|
int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020;
|
|
if (HSK007Reg[1] &0x08)
|
|
setprg8(A, V &prgAND | prgOR &~prgAND);
|
|
else
|
|
if (A ==0x8000)
|
|
setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2);
|
|
|
|
}
|
|
static void Mapper394_CWrap(uint32 A, uint8 V)
|
|
{
|
|
int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F;
|
|
int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100;
|
|
setchr1(A, V &chrAND | chrOR &~chrAND);
|
|
}
|
|
static DECLFW(Mapper394_Write)
|
|
{
|
|
uint8 oldMode =HSK007Reg[1];
|
|
A &=3;
|
|
HSK007Reg[A] =V;
|
|
if (A ==1)
|
|
{
|
|
if (~oldMode &0x10 && V &0x10) JYASIC_power();
|
|
if ( oldMode &0x10 && ~V &0x10)
|
|
{
|
|
JYASIC_restoreWriteHandlers();
|
|
GenMMC3Power();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (HSK007Reg[1] &0x10)
|
|
sync();
|
|
else
|
|
{
|
|
FixMMC3PRG(MMC3_cmd);
|
|
FixMMC3CHR(MMC3_cmd);
|
|
}
|
|
|
|
}
|
|
}
|
|
static void Mapper394_restore (int version)
|
|
{
|
|
int i;
|
|
JYASIC_restoreWriteHandlers();
|
|
if (HSK007Reg[1] &0x10)
|
|
{
|
|
SetWriteHandler(0x5000, 0x5FFF, writeALU);
|
|
SetWriteHandler(0x6000, 0x7fff, CartBW);
|
|
SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
|
|
SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
|
|
SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
|
|
SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
|
|
SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
|
|
SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
|
|
|
|
for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
|
|
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
|
|
cpuWriteHandlersSet =1;
|
|
|
|
SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
|
|
SetReadHandler(0x6000, 0xFFFF, CartBR);
|
|
sync();
|
|
}
|
|
else
|
|
{
|
|
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
|
|
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
|
|
SetReadHandler(0x8000, 0xFFFF, CartBR);
|
|
FixMMC3PRG(MMC3_cmd);
|
|
FixMMC3CHR(MMC3_cmd);
|
|
}
|
|
}
|
|
static void Mapper394_power(void)
|
|
{
|
|
HSK007Reg[0] =0x00;
|
|
HSK007Reg[1] =0x0F;
|
|
HSK007Reg[2] =0x00;
|
|
HSK007Reg[3] =0x10;
|
|
GenMMC3Power();
|
|
SetWriteHandler(0x5000, 0x5FFF, Mapper394_Write);
|
|
}
|
|
|
|
void Mapper394_Init(CartInfo *info)
|
|
{
|
|
allowExtendedMirroring =1;
|
|
sync =sync394;
|
|
JYASIC_init(info);
|
|
GenMMC3_Init(info, 128, 128, 0, 0);
|
|
pwrap =Mapper394_PWrap;
|
|
cwrap =Mapper394_CWrap;
|
|
info->Reset = Mapper394_power;
|
|
info->Power = Mapper394_power;
|
|
AddExState(HSK007Reg, 4, 0, "HSK ");
|
|
GameStateRestore = Mapper394_restore;
|
|
}
|