171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2007 CaH4e3
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* Copyright (C) 2019 Libretro Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* FDS Conversion
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*
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*/
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/* added 2019-5-23
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* - Mapper 56 - UNL KS202
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* FDS Conversion: Super Mario Bros. 3 (Pirate, Alt)
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* similar to M142 but use WRAM instead? $D000 additional IRQ trigger
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* - fix IRQ counter, noticeable in status bars of both SMB2J(KS7032) and SMB3J(KS202)
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*/
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#include "mapinc.h"
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static uint8 reg[8], creg[8], mirr, cmd, IRQa = 0, isirqused = 0;
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static int32 IRQCount, IRQLatch;
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static uint8 KS7032;
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static uint8 *WRAM = NULL;
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static uint32 WRAMSIZE;
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static SFORMAT StateRegsKS7032[] =
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{
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{ &cmd, 1, "CMD" },
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{ reg, 8, "REGS" },
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{ &IRQa, 1, "IRQA" },
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{ &IRQCount, 4 | FCEUSTATE_RLSB, "IRQC" },
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{ 0 }
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};
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static SFORMAT StateRegsKS202[] =
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{
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{ creg, 8, "CREG" },
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{ &mirr, 1, "MIRR" },
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{ 0 }
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};
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static void Sync(void) {
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setprg8(0x8000, reg[0]);
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setprg8(0xA000, reg[1]);
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setprg8(0xC000, reg[2]);
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setprg8(0xE000, ~0);
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setchr8(0);
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if (KS7032)
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setprg8(0x6000, reg[3]);
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else {
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setprg8r(0x10, 0x6000, 0);
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setchr1(0x0000, creg[0]);
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setchr1(0x0400, creg[1]);
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setchr1(0x0800, creg[2]);
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setchr1(0x0C00, creg[3]);
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setchr1(0x1000, creg[4]);
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setchr1(0x1400, creg[5]);
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setchr1(0x1800, creg[6]);
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setchr1(0x1C00, creg[7]);
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setmirror(mirr);
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}
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}
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static DECLFW(UNLKS7032Write) {
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/* FCEU_printf("bs %04x %02x\n",A,V); */
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switch (A & 0xF000) {
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/* case 0x8FFF: reg[4]=V; Sync(); break; */
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case 0x8000: IRQLatch = (IRQLatch & 0xFFF0) | (V & 0x0F); break;
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case 0x9000: IRQLatch = (IRQLatch & 0xFF0F) | ((V & 0x0F) << 4); break;
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case 0xA000: IRQLatch = (IRQLatch & 0xF0FF) | ((V & 0x0F) << 8); break;
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case 0xB000: IRQLatch = (IRQLatch & 0x0FFF) | (V << 12); break;
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case 0xC000:
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IRQa = (V & 0xF);
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if (IRQa)
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IRQCount = IRQLatch;
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X6502_IRQEnd(FCEU_IQEXT); break;
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case 0xD000: X6502_IRQEnd(FCEU_IQEXT); break;
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case 0xE000: cmd = V & 7; break;
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case 0xF000: {
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uint8 bank = (cmd - 1);
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if (bank < 3)
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reg[bank] = reg[bank] & 0x10 | V & 0x0F;
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else if (bank < 4)
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reg[bank] = V;
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Sync();
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switch (A & 0xFC00) {
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case 0xF000:
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A &= 3;
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if (A < 3)
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reg[bank] = reg[bank] & 0x0F | V & 0x10;
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Sync();
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break;
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case 0xF800:
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mirr = (V & 1);
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Sync();
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break;
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case 0xFC00:
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creg[A & 7] = V;
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Sync();
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break;
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}
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}
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break;
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}
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}
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static void FP_FASTAPASS(1) UNLSMB2JIRQHook(int a) {
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if (IRQa) {
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IRQCount += a;
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if (IRQCount >= 0xFFFF) {
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IRQCount = IRQLatch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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static void UNLKS7032Power(void) {
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Sync();
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SetReadHandler(0x6000, 0x7FFF, CartBR);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x4020, 0xFFFF, UNLKS7032Write);
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if (!KS7032) {
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SetWriteHandler(0x6000, 0x7FFF, CartBW);
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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}
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}
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static void StateRestore(int version) {
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Sync();
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}
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void UNLKS7032_Init(CartInfo *info) {
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KS7032 = 1;
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info->Power = UNLKS7032Power;
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MapIRQHook = UNLSMB2JIRQHook;
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GameStateRestore = StateRestore;
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AddExState(&StateRegsKS7032, ~0, 0, 0);
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}
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void UNLKS202_Init(CartInfo *info) {
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KS7032 = 0;
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info->Power = UNLKS7032Power;
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MapIRQHook = UNLSMB2JIRQHook;
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GameStateRestore = StateRestore;
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AddExState(&StateRegsKS7032, ~0, 0, 0);
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AddExState(&StateRegsKS202, ~0, 0, 0);
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WRAMSIZE = 8192;
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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if (info->battery) {
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info->SaveGame[0] = WRAM;
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info->SaveGameLen[0] = WRAMSIZE;
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}
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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}
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