423 lines
12 KiB
C
423 lines
12 KiB
C
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2022 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "asic_h3001.h"
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#include "asic_latch.h"
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#include "asic_mmc1.h"
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#include "asic_mmc2and4.h"
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#include "asic_mmc3.h"
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#include "asic_pt8154.h"
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#include "asic_qj.h"
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#include "asic_tc3294.h"
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#include "asic_vrc1.h"
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#include "asic_vrc2and4.h"
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#include "asic_vrc3.h"
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#include "asic_vrc6.h"
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#include "asic_vrc7.h"
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#include "flashrom.h"
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#include "cartram.h"
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static uint8 submapper;
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static uint8 reg[8];
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static void (*mapperSync)(int, int, int, int) = NULL;
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static void applyMode (uint8);
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static void sync () {
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int prgAND = reg[3] ^ (submapper == 2? 0x00: 0xFF);
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int prgOR = reg[1] | reg[2] <<8;
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int chrAND = reg[4] <<2 &0xE0 ^0xFF;
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int chrOR = reg[6];
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SetupCartCHRMapping(0, CHRptr[0], CHRsize[0], !(reg[5] &0x04));
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if (mapperSync) mapperSync(prgAND, prgOR, chrAND, chrOR);
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}
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static void sync_152 (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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chrAND >>=3;
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prgOR >>=1;
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chrOR >>=3;
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setprg16(0x8000, Latch_data >>4 &prgAND | prgOR &~prgAND);
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setprg16(0xC000, prgOR | prgAND);
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setchr8(Latch_data &chrAND | chrOR &~chrAND);
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setmirror(Latch_data &0x80? MI_1: MI_0);
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}
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static void sync_AxROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=2;
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prgOR >>=2;
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setprg32(0x8000, Latch_data &prgAND | prgOR &~prgAND);
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setchr8(chrOR);
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setmirror(Latch_data &0x10? MI_1: MI_0);
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}
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static void sync_BNROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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setprg8(0x8000, (Latch_data <<2 |0) &prgAND |prgOR);
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setprg8(0xA000, (Latch_data <<2 |1) &prgAND |prgOR);
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setprg8(0xC000, (Latch_data <<2 |2) &prgAND |prgOR);
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setprg8(0xE000, (Latch_data <<2 |3) &prgAND |prgOR);
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setchr8(chrOR);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_CNROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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chrAND >>=3;
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chrOR >>=3;
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setprg8(0x8000, 0 &prgAND |prgOR);
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setprg8(0xA000, 1 &prgAND |prgOR);
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setprg8(0xC000, 2 &prgAND |prgOR);
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setprg8(0xE000, 3 &prgAND |prgOR);
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setchr8(Latch_data &(reg[4] &1? 7: 3));
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_CNROM_Konami (int prgAND, int prgOR, int chrAND, int chrOR) {
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chrAND >>=3;
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chrOR >>=3;
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setprg8(0x8000, 0 &prgAND |prgOR);
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setprg8(0xA000, 1 &prgAND |prgOR);
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setprg8(0xC000, 2 &prgAND |prgOR);
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setprg8(0xE000, 3 &prgAND |prgOR);
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setchr8(Latch_data <<1 &2 | Latch_data >>1 &1);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_GNROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=2;
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chrAND >>=3;
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prgOR >>=2;
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chrOR >>=3;
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setprg32(0x8000, Latch_data >>4 &prgAND | prgOR &~prgAND);
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setchr8(Latch_data &3);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_H3001 (int prgAND, int prgOR, int chrAND, int chrOR) {
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H3001_syncPRG(prgAND, prgOR &~prgAND);
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H3001_syncCHR(chrAND, chrOR &~chrAND);
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H3001_syncMirror();
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}
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static void sync_PNROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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MMC2_syncPRG(prgAND, prgOR &~prgAND);
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MMC24_syncCHR(chrAND, chrOR &~chrAND);
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MMC24_syncMirror();
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}
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static void sync_SKROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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chrAND >>=2;
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prgOR >>=1;
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chrOR >>=2;
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MMC1_syncWRAM(reg[5]);
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MMC1_syncPRG(prgAND, prgOR &~prgAND);
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MMC1_syncCHR(chrAND, chrOR &~chrAND);
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MMC1_syncMirror();
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}
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static void sync_SNROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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chrAND >>=2;
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prgOR >>=1;
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chrOR >>=2;
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MMC1_syncWRAM(reg[5]);
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MMC1_syncPRG(prgAND, prgOR &~prgAND);
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MMC1_syncCHR(chrAND, chrOR &~chrAND);
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MMC1_syncMirror();
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}
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static void sync_SUROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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chrAND =chrAND >>2 &0x0F; /* The highest CHR bit switches 256 KiB PRG banks, so don't use that as a CHR bank bit. */
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prgOR >>=1;
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chrOR >>=2;
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MMC1_syncWRAM(reg[5]);
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MMC1_syncPRG(prgAND, prgOR &~prgAND);
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MMC1_syncCHR(chrAND, chrOR &~chrAND);
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MMC1_syncMirror();
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}
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static void sync_PT8154 (int prgAND, int prgOR, int chrAND, int chrOR) {
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PT8154_syncPRG(prgAND, prgOR &~prgAND);
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PT8154_syncCHR(chrAND, chrOR &~chrAND);
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PT8154_syncMirror();
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}
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static void sync_QJ (int prgAND, int prgOR, int chrAND, int chrOR) {
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QJ_syncPRG(prgAND, prgOR &~prgAND);
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QJ_syncCHR(chrAND, chrOR &~chrAND);
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QJ_syncMirror();
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}
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static void sync_TC3294 (int prgAND, int prgOR, int chrAND, int chrOR) {
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TC3294_syncWRAM(reg[5]);
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TC3294_syncPRG(prgAND, prgOR &~prgAND);
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setchr8(0);
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TC3294_syncMirror();
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}
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static void sync_TxROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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MMC3_syncWRAM(reg[5]);
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MMC3_syncPRG(prgAND, prgOR &~prgAND);
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MMC3_syncCHR(chrAND, chrOR &~chrAND);
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MMC3_syncMirror();
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}
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static void sync_TxSROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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MMC3_syncWRAM(reg[5]);
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MMC3_syncPRG(prgAND, prgOR &~prgAND);
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MMC3_syncCHR(chrAND &0x7F, chrOR &~chrAND);
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setmirror(MMC3_getCHRBank(0) &0x80? MI_1: MI_0);
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}
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static void sync_UxROM (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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prgOR >>=1;
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setprg16(0x8000, Latch_data &prgAND | prgOR &~prgAND);
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setprg16(0xC000, prgOR | prgAND);
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setchr8(chrOR);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_VRC1 (int prgAND, int prgOR, int chrAND, int chrOR) {
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VRC1_syncPRG(prgAND, prgOR &~prgAND);
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VRC1_syncCHR(chrAND, chrOR &~chrAND);
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VRC1_syncMirror();
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}
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static void sync_VRC3 (int prgAND, int prgOR, int chrAND, int chrOR) {
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prgAND >>=1;
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prgOR >>=1;
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VRC3_syncWRAM(reg[5]);
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VRC3_syncPRG(prgAND, prgOR &~prgAND);
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VRC3_syncCHR(chrAND, chrOR &~chrAND);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static void sync_VRC4 (int prgAND, int prgOR, int chrAND, int chrOR) {
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VRC24_syncWRAM(reg[5]);
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VRC24_syncPRG(prgAND, prgOR &~prgAND);
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VRC24_syncCHR(chrAND, chrOR &~chrAND);
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VRC24_syncMirror();
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}
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static void sync_VRC6 (int prgAND, int prgOR, int chrAND, int chrOR) {
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VRC6_syncWRAM(reg[5]);
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VRC6_syncPRG(prgAND, prgOR &~prgAND);
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VRC6_syncCHR(chrAND, chrOR &~chrAND);
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VRC6_syncMirror();
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}
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static void sync_VRC7 (int prgAND, int prgOR, int chrAND, int chrOR) {
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VRC7_syncWRAM(reg[5]);
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VRC7_syncPRG(prgAND, prgOR &~prgAND);
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VRC7_syncCHR(chrAND, chrOR &~chrAND);
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VRC7_syncMirror();
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}
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static void sync_supervisor (int prgAND, int prgOR, int chrAND, int chrOR) {
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setprg8(0x8000, prgOR);
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setprg8(0xA000, prgOR +1);
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setprg8(0xC000, submapper == 3? 0x1E: 0x3E);
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setprg8(0xE000, submapper == 3? 0x1F: 0x3F);
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setchr8(chrOR);
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setmirror(reg[4] &0x01? MI_V: MI_H);
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}
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static DECLFW (writeFlash) {
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flashrom_write(A &0x1FFF | (Page[A >>11] +A -PRGptr[0]) &~0x1FFF, V);
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}
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static int SUROM_getPRGBank (uint8 bank) {
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return MMC1_getPRGBank(bank) | MMC1_getCHRBank(0) &0x10;
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}
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static int Mapper22_getCHRBank (uint8 bank) {
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return VRC24_getCHRBank(bank &7) >>1;
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}
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static DECLFW (writeReg) {
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reg[A &7] = V;
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if ((A &7) == 0)
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applyMode(1);
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else
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sync();
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}
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static void applyMode (uint8 clear) {
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if (reg[0] &0x80) {
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SetWriteHandler(0x5000, 0x5FFF, CartBW);
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switch(submapper <<8 | reg[0] &0x1F) {
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case 0x000: case 0x100: case 0x200:
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mapperSync = sync_UxROM;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x001: case 0x105: case 0x205:
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mapperSync = sync_SKROM;
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MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, NULL, NULL, NULL, NULL);
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break;
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case 0x002: case 0x102: case 0x202: /* NROM or BNROM */
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mapperSync = sync_BNROM;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x003: case 0x103: case 0x203:
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mapperSync = sync_CNROM;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x004: case 0x101: case 0x201: case 0x209: /* MMC3 or Namco 118 */
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mapperSync = sync_TxROM;
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MMC3_activate(clear, sync, MMC3_TYPE_SHARP, NULL, NULL, NULL, NULL);
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if (clear) MMC3_writeReg(0xA000, reg[4] &0x04? 0: 1);
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break;
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case 0x10E: case 0x20E: /* MMC3 with single-screen mirroring. 239-in-1's Goal! Two has a screen where MMC3 scanline counter emulation fails. */
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mapperSync = sync_TxSROM;
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MMC3_activate(clear, sync, MMC3_TYPE_SHARP, NULL, NULL, NULL, NULL);
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break;
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case 0x006:
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mapperSync = sync_VRC4;
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VRC4_activate(clear, sync, 0x42, 0x84, 1, NULL, NULL, NULL, NULL, NULL);
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break;
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case 0x007: case 0x112: case 0x212:
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mapperSync = sync_VRC4;
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VRC2_activate(clear, sync, 0x02, 0x01, NULL, Mapper22_getCHRBank, NULL, NULL);
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break;
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case 0x008: case 0x118: case 0x218:
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mapperSync = sync_VRC4;
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VRC4_activate(clear, sync, 0x05, 0x0A, 1, NULL, NULL, NULL, NULL, NULL);
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break;
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case 0x009: case 0x110:
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mapperSync = sync_VRC6;
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VRC6_activate(clear, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
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break;
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case 0x00A: case 0x115: case 0x215:
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mapperSync = sync_VRC4;
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VRC4_activate(clear, sync, 0x0A, 0x05, 1, NULL, NULL, NULL, NULL, NULL);
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break;
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case 0x00B:
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mapperSync = sync_VRC6;
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VRC6_activate(clear, sync, 0x02, 0x01, NULL, NULL, NULL, NULL);
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break;
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case 0x00C:
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mapperSync = sync_VRC3;
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VRC3_activate(clear, sync);
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break;
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case 0x00D:
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mapperSync = sync_VRC7;
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VRC7_activate(clear, sync, 0x18);
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break;
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case 0x00E:
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mapperSync = sync_CNROM_Konami;
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Latch_activate(clear, sync, 0x6000, 0x7FFF, NULL);
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break;
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case 0x104: case 0x204:
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mapperSync = sync_AxROM;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x106: case 0x206:
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mapperSync = sync_SNROM;
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MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, NULL, NULL, NULL, NULL);
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break;
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case 0x107: case 0x208:
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mapperSync = sync_SUROM;
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MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, SUROM_getPRGBank, NULL, NULL, NULL);
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break;
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case 0x108:
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mapperSync = sync_GNROM;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x109:
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mapperSync = sync_PNROM;
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MMC24_activate(clear, sync);
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break;
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case 0x10A: case 0x20A:
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mapperSync = sync_TxROM;
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MMC3_activate(clear, sync, MMC3_TYPE_MMC6, NULL, NULL, NULL, NULL);
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break;
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case 0x10B: case 0x20B:
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mapperSync = sync_152;
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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break;
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case 0x10F:
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mapperSync = sync_PT8154;
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PT8154_activate(clear, sync);
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break;
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case 0x119:
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mapperSync = sync_QJ;
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QJ_activate(clear, sync);
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break;
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case 0x11A: case 0x21A:
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mapperSync = sync_VRC1;
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VRC1_activate(clear, sync);
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break;
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case 0x301:
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mapperSync = sync_H3001;
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H3001_activate(clear, sync);
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break;
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case 0x401:
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mapperSync = sync_TC3294;
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TC3294_activate(clear, sync);
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break;
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default:
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break;
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}
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} else {
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SetWriteHandler(0x5000, 0x5FFF, writeReg);
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SetReadHandler(0x8000, 0xFFFF, flashrom_read);
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SetWriteHandler(0x8000, 0xFFFF, writeFlash);
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mapperSync = sync_supervisor;
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PPU_hook = NULL;
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MapIRQHook = flashrom_cpuCycle;
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GameHBIRQHook = NULL;
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sync();
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}
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}
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static void power () {
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reg[0] = reg[1] = reg[2] = reg[3] = reg[4] = reg[5] = reg[6] = reg[7] = 0;
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applyMode(1);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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}
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static void stateRestore (int version) {
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applyMode(0);
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}
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void Mapper446_Init (CartInfo *info) {
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submapper =info->submapper;
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H3001_addExState();
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Latch_addExState();
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MMC1_addExState();
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MMC24_addExState();
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MMC3_addExState();
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VRC1_addExState();
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VRC24_addExState();
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VRC3_addExState();
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VRC6_addExState();
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VRC7_addExState();
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QJ_addExState();
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PT8154_addExState();
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TC3294_addExState();
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WRAM_init(info, 32);
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flashrom_init (0x01, 0x7E, 131072, 0xAAA, 0x555, 0xFFF);
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info->Reset =power;
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info->Power =power;
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GameStateRestore =stateRestore;
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AddExState(reg, 8, 0, "REGS");
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}
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