diff --git a/src/boards/AbG1l.c b/src/boards/AbG1l.c new file mode 100644 index 0000000..7305336 --- /dev/null +++ b/src/boards/AbG1l.c @@ -0,0 +1,156 @@ +/* FCE Ultra - NES/Famicom Emulator + * + * Copyright notice for this file: + * + * Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + * + * + */ + +#include "mapinc.h" + +static uint8 regs[4]; +static uint8 hrd_flag; +static void(*Sync)(void); + +static SFORMAT StateRegs[] = +{ + { &hrd_flag, 1, "FLAG" }, + { regs, 4, "REGS" }, + { 0 } +}; + +static void SyncAbG1l(void) { + + if (regs[1] & 0x10) + setprg32(0x8000,(regs[1] & 0xC0) >> 6); + else + { + setprg16(0x8000, (regs[1] & 0xE0) >> 5); + setprg16(0xC000, (regs[1] & 0xE0) >> 5); + } + + setchr8(regs[1]); + setmirror((regs[1] & 0x8) ? 0 : 1); + +} + +static DECLFW(AbG1lWriteHi) { + regs[0] = V; + setchr8(((regs[2] & 0xC0) >> 7) << 2 | (regs[0] & 0x03)); + Sync(); +} + +static DECLFW(AbG1lWriteLo) { + regs[A & 0x03] = V; + Sync(); +} + +static DECLFR(AbG1lReadLo) { + return hrd_flag; +} + +static void AbG1lPower(void) { + hrd_flag = 0; + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + + Sync(); + SetWriteHandler(0x8000, 0xFFFF, AbG1lWriteHi); + SetWriteHandler(0x6001, 0x6002, AbG1lWriteLo); + SetReadHandler(0x6000, 0x7FFF, AbG1lReadLo); + SetReadHandler(0x8000, 0xFFFF, CartBR); +} + +static void StateRestore(int version) { + Sync(); +} + +static void AbG1lReset(void) { + hrd_flag++; + hrd_flag &= 3; + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + + Sync(); +} + +void AbG1l_Init(CartInfo *info) { + + Sync = SyncAbG1l; + + hrd_flag = 0; + + Sync(); + + info->Power = AbG1lPower; + info->Reset = AbG1lReset; + AddExState(&StateRegs, ~0, 0, 0); + GameStateRestore = StateRestore; +} + + +static void SyncWellNoDG450(void) { + + if (regs[1] & 0x10) + setprg32(0x8000, (regs[1]) >> 6); + else + { + setprg16(0x8000, (regs[1]) >> 5); + setprg16(0xC000, (regs[1]) >> 5); + } + + setchr8(regs[1] & 0x0F); + setmirror((regs[1] & 0x8) ? 0 : 1); +} + +static void WellNoDG450Power(void) { + hrd_flag = 0; + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + + Sync(); + + SetWriteHandler(0x6001, 0x6002, AbG1lWriteLo); + SetReadHandler(0x6000, 0x7FFF, AbG1lReadLo); + SetReadHandler(0x8000, 0xFFFF, CartBR); +} + +static void WellNoDG450Reset(void) { + hrd_flag++; + hrd_flag &= 3; + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + + Sync(); +} + +void WellNoDG450_Init(CartInfo *info) { + Sync = SyncWellNoDG450; + info->Power = WellNoDG450Power; + info->Reset = WellNoDG450Reset; + AddExState(&StateRegs, ~0, 0, 0); + GameStateRestore = StateRestore; +} diff --git a/src/boards/BS110.c b/src/boards/BS110.c new file mode 100644 index 0000000..b070481 --- /dev/null +++ b/src/boards/BS110.c @@ -0,0 +1,210 @@ +/* FCE Ultra - NES/Famicom Emulator +* +* Copyright notice for this file: +* Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +* +*/ + +#include "mapinc.h" +#include "mmc3.h" + + +extern uint8 *WRAM; +extern uint32 WRAMSIZE; + +//extern uint8 *CHRRAM; +//extern uint32 CHRRAMSIZE; + +uint8 mmc3_reg[8]; +uint8 exRegs[8]; +uint8 pointer; +uint8 locked; +uint8 readDIP; +uint16 prgAND; +uint16 chrAND; +uint16 prgOR; +uint16 chrOR; +uint8 nrom; +uint8 nrom128; +uint8 dipswitch; + + +static SFORMAT BS110_StateRegs[] = +{ + { exRegs, 8, "REGS" }, + { mmc3_reg, 8, "MMC3R" }, + { &pointer, 1, "POINT" }, + { &readDIP, 1, "RDIP" }, + { &prgAND, 2 | FCEUSTATE_RLSB, "PRGAND" }, + { &chrAND, 2 | FCEUSTATE_RLSB, "CHRAND" }, + { &prgOR, 2 | FCEUSTATE_RLSB, "PRGOR" }, + { &chrOR, 2 | FCEUSTATE_RLSB, "CHROR" }, + { &nrom, 1, "NROM" }, + { &nrom128, 1, "N128" }, + { &dipswitch, 1, "DIP" }, + { 0 } +}; + +int BS110GetPRGBank(int bank) +{ + if (~bank & 1 && (pointer & 0x40)) bank ^= 2; + return bank & 2 ? 0xFE | bank & 1 : mmc3_reg[6 | bank & 1]; +} + +void BS110SyncPRG_GNROM(int A14, int AND, int OR) { + setprg8(0x8000, (BS110GetPRGBank(0) &~A14) &AND | OR); + setprg8(0xA000, (BS110GetPRGBank(1) &~A14) &AND | OR); + setprg8(0xC000, (BS110GetPRGBank(0) | A14) &AND | OR); + setprg8(0xE000, (BS110GetPRGBank(1) | A14) &AND | OR); +} + +static void BS110CW(uint32 A, uint8 V) { + + uint8 block = ((exRegs[1]) & 0x03); + uint8 mask = 0x7F; + setchr1(A, (block << 7) | (V & mask)); + +} + +static void BS110PW(uint32 A, uint8 V) { + if ((exRegs[1] >> 2) & 0x01) + { + uint8 mask = 0x0F; + uint8 block = (exRegs[1] & 3) << 4; + if ((exRegs[1] >> 3) & 0x01) + { + setprg8(0x8000, (BS110GetPRGBank(0)) & mask | block); + setprg8(0xA000, (BS110GetPRGBank(1)) & mask | block); + setprg8(0xC000, (BS110GetPRGBank(0)) & mask | block); + setprg8(0xE000, (BS110GetPRGBank(1)) & mask | block); + } + else + { + + setprg8(0x8000, (BS110GetPRGBank(0)) & mask | block); + setprg8(0xA000, (BS110GetPRGBank(1)) & mask | block); + setprg8(0xC000, (BS110GetPRGBank(0) | 2) & mask | block); + setprg8(0xE000, (BS110GetPRGBank(1) | 2) & mask | block); + } + } + else + { + uint8 mask = 0x0F; + uint8 block = (exRegs[1] & 3) << 4; + setprg8(A, block | (V & mask)); + } +} + + +static DECLFW(BS110WriteHi) { + + A = A & 0xE001; + + if (A < 0xC000) + { + if (A == 0x8000) + pointer = MMC3_cmd ^ V; + if (A == 0x8001) + mmc3_reg[MMC3_cmd & 0x07] = V; + + MMC3_CMDWrite(A, V); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + MMC3_IRQWrite(A, V); + } +} + +static DECLFW(BS110WriteLo) { + + exRegs[1] = A; + exRegs[0] = V; + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + +} +static DECLFR(BS110ReadHi) +{ + if ((A == 0xCB00) && ((exRegs[1] & 0x0F) == 0x08)) + return dipswitch; + else + return CartBR(A); + +} + +static void BS110Power(void) { + dipswitch = 0; + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + int i = 0; + + for (i = 0;i<4;i++) + { + exRegs[i] = 0; + } + + GenMMC3Power(); + SetWriteHandler(0x6000, 0x7FFF, BS110WriteLo); + SetWriteHandler(0x8000, 0xFFFF, BS110WriteHi); + SetReadHandler(0x8000, 0xFFFF, BS110ReadHi); +} + +static void BS110Reset(void) { + + dipswitch++; + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + int i = 0; + + for (i = 0;i<4;i++) + { + exRegs[i] = 0; + } + + MMC3RegReset(); +} +static void BS110Close(void) { + if (WRAM) + FCEU_gfree(WRAM); + WRAM = NULL; +} + +void BS110_Init(CartInfo *info) { + GenMMC3_Init(info, 512, 512, 0, 0); + pwrap = BS110PW; + cwrap = BS110CW; + info->Power = BS110Power; + info->Reset = BS110Reset; + info->Close = BS110Close; + + WRAMSIZE = 8192; + WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE); + SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1); + AddExState(WRAM, WRAMSIZE, 0, "WRAM"); + + //CHRRAMSIZE = 8192; + //CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE); + //SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1); + //AddExState(CHRRAM, CHRRAMSIZE, 0, "CHRR"); + + AddExState(EXPREGS, 3, 0, "EXPR"); + AddExState(BS110_StateRegs, ~0, 0, 0); +} diff --git a/src/boards/Bs5652.c b/src/boards/Bs5652.c new file mode 100644 index 0000000..cba0004 --- /dev/null +++ b/src/boards/Bs5652.c @@ -0,0 +1,260 @@ +/* FCE Ultra - NES/Famicom Emulator + * + * Copyright notice for this file: + * Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + * + * + */ + +#include "mapinc.h" +#include "mmc3.h" +#include "crc32.h" + +extern uint8 *WRAM; +extern uint32 WRAMSIZE; + +//extern uint8 *CHRRAM; +//extern uint32 CHRRAMSIZE; + +uint8 mmc3_reg[8]; +uint8 exRegs[8]; +uint8 pointer; +uint8 locked; +uint8 readDIP; +uint16 prgAND; +uint16 chrAND; +uint16 prgOR; +uint16 chrOR; +uint8 nrom; +uint8 nrom128; +uint8 dipswitch; + + +static SFORMAT BS5652_StateRegs[] = +{ + { exRegs, 8, "REGS" }, + { mmc3_reg, 8, "MMC3R" }, + { &pointer, 1, "POINT" }, + { &readDIP, 1, "RDIP" }, + { &prgAND, 2 | FCEUSTATE_RLSB, "PRGAND" }, + { &chrAND, 2 | FCEUSTATE_RLSB, "CHRAND" }, + { &prgOR, 2 | FCEUSTATE_RLSB, "PRGOR" }, + { &chrOR, 2 | FCEUSTATE_RLSB, "CHROR" }, + { &nrom, 1, "NROM" }, + { &nrom128, 1, "N128" }, + { &dipswitch, 1, "DIP" }, + { 0 } +}; + +void Bs5652AnalyzeReg() +{ + locked = exRegs[0] & 0x80; + readDIP = exRegs[0] & 0x40; + prgAND = exRegs[1] & 0x04 ? 0x0F : 0x1F; + chrAND = exRegs[1] & 0x40 ? 0x7F : 0xFF; + prgOR = (exRegs[1] & 0x03) << 4; + chrOR = (exRegs[1] & 0x30) << 3 ; + nrom = exRegs[0] & 0x08; + nrom128 = exRegs[1] & 0x08; +} + +int Bs5652GetPRGBank(int bank) +{ + if (~bank & 1 && (pointer & 0x40)) bank ^= 2; + return bank & 2 ? 0xFE | bank & 1 : mmc3_reg[6 | bank & 1]; +} + +void Bs5652SyncPRG_GNROM(int A14, int AND, int OR) { + setprg8(0x8000, (Bs5652GetPRGBank(0) &~A14) &AND | OR); + setprg8(0xA000, (Bs5652GetPRGBank(1) &~A14) &AND | OR); + setprg8(0xC000, (Bs5652GetPRGBank(0) | A14) &AND | OR); + setprg8(0xE000, (Bs5652GetPRGBank(1) | A14) &AND | OR); +} + +static void Bs5652CW(uint32 A, uint8 V) { + + if (exRegs[0] & 0x08) + setchr8((exRegs[2] & 0x0F) | (exRegs[4] & 0x03) | (((exRegs[1] >> 4) & 7) << 4)); + else + setchr1(A, (V & chrAND) | chrOR ); +} + +static void Bs5652PW(uint32 A, uint8 V) { + if (nrom) + { + if (exRegs[3] & 0x8)// 20190504 up2 + { + if ((exRegs[1] >> 3) & 0x01) + { + uint8 _bank = ((exRegs[2] >> 1) & 0x07) | ((exRegs[1] & 3) << 3); + setprg16(0x8000, _bank); + setprg16(0xC000, _bank); + + } + else + { + setprg32(0x8000,((exRegs[2] >> 2) & 0x03) | ((exRegs[1] & 3) << 2)); + } + } + else + { + Bs5652SyncPRG_GNROM(nrom128 ? 0 : 2, prgAND, prgOR); + } + + } + else + { + if (((exRegs[1] >> 7) & 0x01)) + { + setprg32(0x8000,((Bs5652GetPRGBank(0) >> 2) & 0x03) | ((exRegs[1] & 3) << 2)); + } + else + setprg8(A, prgOR | (V & prgAND)); + } +} + + +static DECLFW(Bs5652WriteHi) { + + A = A & 0xE001; + + if (A < 0xC000) + { + if(A==0x8000) + pointer = MMC3_cmd ^ V; + if(A==0x8001) + mmc3_reg[MMC3_cmd & 0x07] = V; + + MMC3_CMDWrite(A, V); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + MMC3_IRQWrite(A, V); + } +} + +static DECLFW(Bs5652WriteLo) { + + if (!locked) { + exRegs[A & 3] = V; + Bs5652AnalyzeReg(); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + if ((exRegs[0] & 0x08)) + { + exRegs[4] = V; + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + WRAM[A - 0x6000] = V; + } + } +} +static DECLFR(Bs5652ReadHi) +{ + if (readDIP) + { + return dipswitch; + } + else + return CartBR(A); +} + +static void Bs5652Power(void) { + dipswitch = 0; + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + int i=0; + + for(i=0;i<4;i++) + { + exRegs[i]=0; + } + + Bs5652AnalyzeReg(); + + GenMMC3Power(); + SetWriteHandler(0x6000, 0x7FFF, Bs5652WriteLo); + SetWriteHandler(0x8000, 0xFFFF, Bs5652WriteHi); + SetReadHandler(0x8000, 0xFFFF, Bs5652ReadHi); +} + +static void Bs5652Reset(void) { + + dipswitch++; + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + int i=0; + + for(i=0;i<4;i++) + { + exRegs[i]=0; + } + + Bs5652AnalyzeReg(); + + MMC3RegReset(); +} +static void Bs5652Close(void) { + if (WRAM) + FCEU_gfree(WRAM); + WRAM = NULL; +} + +void Bs5652_Init(CartInfo *info) { + GenMMC3_Init(info, 512, 512, 0, 0); + pwrap = Bs5652PW; + cwrap = Bs5652CW; + info->Power = Bs5652Power; + info->Reset = Bs5652Reset; + info->Close = Bs5652Close; + + WRAMSIZE = 8192; + WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE); + SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1); + AddExState(WRAM, WRAMSIZE, 0, "WRAM"); + + //CHRRAMSIZE = 8192; + //CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE); + //SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1); + //AddExState(CHRRAM, CHRRAMSIZE, 0, "CHRR"); + + uint32 unif_crc = CalcCRC32(0, PRGptr[0], PRGsize[0]); + + if (unif_crc == 0xb97641b5) //Fix my own error, unif CHR 0 error + { + if ((CHRsize[0] == 0x2000) && (CHRsize[1] > 0x2000)) + { + CHRsize[0] = CHRsize[1]; + CHRptr[0] = (uint8*)FCEU_gmalloc(CHRsize[1]); + memcpy(CHRptr[0], CHRptr[1], CHRsize[1]); + SetupCartCHRMapping(0, CHRptr[0], CHRsize[0], 0); + } + } + + AddExState(EXPREGS, 3, 0, "EXPR"); + AddExState(BS5652_StateRegs, ~0, 0, 0); +} diff --git a/src/boards/KG256.c b/src/boards/KG256.c new file mode 100644 index 0000000..6d27740 --- /dev/null +++ b/src/boards/KG256.c @@ -0,0 +1,111 @@ +/* FCE Ultra - NES/Famicom Emulator + * + * Copyright notice for this file: + * + * Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + * + * + */ + +#include "mapinc.h" + +static uint8 regs[4]; + +static SFORMAT StateRegs[] = +{ + { regs, 4, "REGS" }, + { 0 } +}; + +static void Sync(void) { + + int r = 0; + if ((regs[1]) & 0x20) + { + r = 1; + } + if ((regs[1] >> 4) & 0x01) + { + setprg16(0x8000, regs[1] & 0x07 | (r) << 3); + setprg16(0xC000, regs[1] & 0x07 | (r) << 3); + setchr8(regs[0] & 0x07 | (r) << 3); + } + else + { + setprg32(0x8000, (regs[1] >> 1) & 0x03 | (r) << 2); + setchr8(regs[2] & 0x01 | (r) << 3); + } + + uint8 mirr = (((regs[0] >> 4 & 0x1))); + + if (mirr) + setmirror(0); + else + setmirror(1); + +} + +static DECLFW(KG256WriteHi) { + regs[2] = V; + Sync(); +} + +static DECLFW(KG256WriteLo) { + regs[A & 0x03] = V; + Sync(); +} + +static void KG256Power(void) { + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + regs[3] = 0; + + SetWriteHandler(0x8000, 0xFFFF, KG256WriteHi); + SetWriteHandler(0x6000, 0x7FFF, KG256WriteLo); + SetReadHandler(0x8000, 0xFFFF, CartBR); + + Sync(); + +} + +static void StateRestore(int version) { + Sync(); +} + +static void KG256Reset(void) { + + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + + Sync(); +} + +void KG256_Init(CartInfo *info) { + + Sync(); + + info->Power = KG256Power; + info->Reset = KG256Reset; + AddExState(&StateRegs, ~0, 0, 0); + GameStateRestore = StateRestore; +} + + + diff --git a/src/boards/NC7000M.c b/src/boards/NC7000M.c new file mode 100644 index 0000000..af8632d --- /dev/null +++ b/src/boards/NC7000M.c @@ -0,0 +1,198 @@ +/* FCE Ultra - NES/Famicom Emulator + * + * Copyright notice for this file: + * Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + * + * + * + */ + +#include "mapinc.h" +#include "mmc3.h" + + +extern uint8 *WRAM; +extern uint32 WRAMSIZE; + +//extern uint8 *CHRRAM; +//extern uint32 CHRRAMSIZE; + + +uint8 mmc3_reg[8]; +uint8 exRegs[8]; +uint8 pointer; +uint8 locked; +uint8 readDIP; +uint16 prgAND; +uint16 chrAND; +uint16 prgOR; +uint16 chrOR; +uint8 nrom; +uint8 nrom256; +uint16 reg; + + +static SFORMAT NC7000M_StateRegs[] = +{ + { exRegs, 8, "REGS" }, + { mmc3_reg, 8, "MMC3R" }, + { &pointer, 1, "POINT" }, + { &readDIP, 1, "RDIP" }, + { &prgAND, 2 | FCEUSTATE_RLSB, "PRGAND" }, + { &chrAND, 2 | FCEUSTATE_RLSB, "CHRAND" }, + { &prgOR, 2 | FCEUSTATE_RLSB, "PRGOR" }, + { &chrOR, 2 | FCEUSTATE_RLSB, "CHROR" }, + { &nrom, 1, "NROM" }, + { &nrom256, 1, "N256" }, + { ®, 2 | FCEUSTATE_RLSB, "REG" }, + { 0 } +}; + +void NC7000MAnalyzeReg() +{ + locked = (reg & 0x80); + prgAND = (reg & 0x08 ? 0x0F : 0x1F); + chrAND = (reg & 0x40 ? 0x7F : 0xFF); + prgOR = (reg << 4 & 0x30); + chrOR = (reg << 3 & 0x080 | reg & 0x100); + nrom = (reg & 0x20); + nrom256 = (reg & 0x04); +} + +int NC7000MGetPRGBank(int bank) +{ + if (~bank & 1 && (pointer & 0x40)) bank ^= 2; + return bank & 2 ? 0xFE | bank & 1 : mmc3_reg[6 | bank & 1]; +} + +void NC7000MSyncPRG_GNROM(int A14, int AND, int OR) { + setprg8(0x8000, (NC7000MGetPRGBank(0) &~A14) &AND | OR); + setprg8(0xA000, (NC7000MGetPRGBank(1) &~A14) &AND | OR); + setprg8(0xC000, (NC7000MGetPRGBank(0) | A14) &AND | OR); + setprg8(0xE000, (NC7000MGetPRGBank(1) | A14) &AND | OR); +} + +static void NC7000MCW(uint32 A, uint8 V) { + + setchr1(A, (V & chrAND) | (chrOR &~chrAND)); +} + +static void NC7000MPW(uint32 A, uint8 V) { + + if (nrom) + { + NC7000MSyncPRG_GNROM(nrom256 ? 2 : 0, prgAND, prgOR &~prgAND); + } + else + { + setprg8(A, (prgOR &~prgAND) | (V & prgAND)); + } +} + + +static DECLFW(NC7000MWriteHi) { + + A = A & 0xE001; + + if (A < 0xC000) + { + if(A==0x8000) + pointer = MMC3_cmd ^ V; + if(A==0x8001) + mmc3_reg[MMC3_cmd & 0x07] = V; + + MMC3_CMDWrite(A, V); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + MMC3_IRQWrite(A, V); + } +} + +static DECLFW(NC7000MWriteLo) { + + if (!(reg & 0x80)) { + reg = V | A & 0x100; + NC7000MAnalyzeReg(); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + else + { + WRAM[A - 0x6000] = V; + } +} +static DECLFR(NC7000MReadHi) +{ + return CartBR(A); +} + +static void NC7000MPower(void) { + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + + reg = 0x0000; + + NC7000MAnalyzeReg(); + + GenMMC3Power(); + SetWriteHandler(0x6000, 0x7FFF, NC7000MWriteLo); + SetWriteHandler(0x8000, 0xFFFF, NC7000MWriteHi); +} + +static void NC7000MReset(void) { + + mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02; + mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07; + mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01; + + reg = 0x0000; + + NC7000MAnalyzeReg(); + + MMC3RegReset(); +} +static void NC7000MClose(void) { + if (WRAM) + FCEU_gfree(WRAM); + WRAM = NULL; +} + +void NC7000M_Init(CartInfo *info) { + GenMMC3_Init(info, 512, 512, 0, 0); + pwrap = NC7000MPW; + cwrap = NC7000MCW; + info->Power = NC7000MPower; + info->Reset = NC7000MReset; + info->Close = NC7000MClose; + + WRAMSIZE = 8192; + WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE); + SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1); + AddExState(WRAM, WRAMSIZE, 0, "WRAM"); + + //CHRRAMSIZE = 8192; + //CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE); + //SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1); + //AddExState(CHRRAM, CHRRAMSIZE, 0, "CHRR"); + + AddExState(EXPREGS, 3, 0, "EXPR"); + AddExState(NC7000M_StateRegs, ~0, 0, 0); +} diff --git a/src/boards/addrlatch.c b/src/boards/addrlatch.c index 473559e..8e02d7a 100644 --- a/src/boards/addrlatch.c +++ b/src/boards/addrlatch.c @@ -345,8 +345,14 @@ void Mapper212_Init(CartInfo *info) { /*------------------ Map 213 ---------------------------*/ static void M213Sync(void) { + if(latche & 0x40) { + setprg16(0x8000, (latche & 7)); + setprg16(0xC000, (latche & 7)); + } else { setprg32(0x8000, (latche >> 1) & 3); + } setchr8((latche >> 3) & 7); + setmirror(((latche & 1)^((latche >> 6) & 1)) ^ 1); } void Mapper213_Init(CartInfo *info) { @@ -574,3 +580,35 @@ static void BMCSA005ASync(void) { void BMCSA005A_Init(CartInfo *info) { Latch_Init(info, BMCSA005ASync, NULL, 0x0000, 0x8000, 0xFFFF, 0); } + + +//-------------- 831019C J-2282 ------------------------ + +static void J2282Sync(void) { + setchr8(0); + + if ((latche & 0x40)) + { + uint8 bank = (latche >> 0) & 0x1F; + setprg16(0x8000, bank); + setprg16(0xC000, bank); + } + else + { + if (latche & 0x800) + { + setprg8(0x6000, ((latche << 1) & 0x3F) | 3); + } + uint8 bank = (latche >> 1) & 0x1F; + setprg32(0x8000, bank); + } + + if (latche & 0x80) + setmirror(0); + else + setmirror(1); +} + +void J2282_Init(CartInfo *info) { + Latch_Init(info, J2282Sync, NULL, 0x0000, 0x8000, 0xFFFF, 0); +} diff --git a/src/boards/hp898f.c b/src/boards/hp898f.c index 243ffa3..7fbb171 100644 --- a/src/boards/hp898f.c +++ b/src/boards/hp898f.c @@ -2,7 +2,7 @@ * * Copyright notice for this file: * Copyright (C) 2015 CaH4e3 - * + * Copyright (C) 2020 dragon2snow,loong2snow from www.nesbbs.com * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -21,21 +21,43 @@ #include "mapinc.h" static uint8 regs[2]; +static uint8 _submapper = 0; static SFORMAT StateRegs[] = { { regs, 2, "REGS" }, + { &_submapper ,1, "SUBM"}, { 0 } }; +// submapper 1 The code for the original fceux +// submapper 0 new HP898F code by dragon2snow,loong2snow from www.nesbbs.com static void Sync(void) { - uint8 chr = (regs[0] >> 4) & 7; - uint8 prg = (regs[1] >> 3) & 7; - uint8 dec = (regs[1] >> 4) & 4; - setchr8(chr & (~(((regs[0] & 1) << 2) | (regs[0] & 2)))); - setprg16(0x8000,prg & (~dec)); - setprg16(0xC000,prg | dec); - setmirror(regs[1] >> 7); + + if (_submapper == 1) + { + uint8 chr = (regs[0] >> 4) & 7; + uint8 prg = (regs[1] >> 3) & 7; + uint8 dec = (regs[1] >> 4) & 4; + setchr8(chr & (~(((regs[0] & 1) << 2) | (regs[0] & 2)))); + setprg16(0x8000, prg & (~dec)); + setprg16(0xC000, prg | dec); + setmirror(regs[1] >> 7); + } + else + { + if (regs[1] & 0x40) + setprg32(0x8000, regs[1] >> 1); + else { + setprg16(0x8000, regs[1]); + setprg16(0xC000, regs[1]); + } + setchr8((regs[0] >> 4) &~(((regs[0] & 1) ? 4 : 0) | (regs[0] & 2))); + if (regs[1] & 0x80) + setmirror(1); + else + setmirror(0); + } } static DECLFW(HP898FWrite) { @@ -45,11 +67,27 @@ static DECLFW(HP898FWrite) { } } +static DECLFW(HP898FWriteEx) { + switch (A & 4) { + case 0: regs[0] = V; break;//CHR + case 4: regs[1] = (V & 0xC0) | ((V >> 2) & 6) | ((V & 0x20) ? 1 : 0); break;//PRG + } + Sync(); +} static void HP898FPower(void) { regs[0] = regs[1] = 0; Sync(); - SetReadHandler(0x8000, 0xFFFF, CartBR); - SetWriteHandler(0x6000, 0xFFFF, HP898FWrite); + if (_submapper == 1) + { + SetReadHandler(0x8000, 0xFFFF, CartBR); + SetWriteHandler(0x6000, 0xFFFF, HP898FWrite); + } + else + { + SetReadHandler(0x8000, 0xFFFF, CartBR); + SetWriteHandler(0x6000, 0x7FFF, HP898FWriteEx); + SetWriteHandler(0xE000, 0xFFFF, HP898FWriteEx); + } } static void HP898FReset(void) { @@ -62,6 +100,7 @@ static void StateRestore(int version) { } void BMCHP898F_Init(CartInfo *info) { + _submapper = info->submapper; info->Reset = HP898FReset; info->Power = HP898FPower; GameStateRestore = StateRestore; diff --git a/src/boards/super24.c b/src/boards/super24.c index 5805dcc..012d76b 100644 --- a/src/boards/super24.c +++ b/src/boards/super24.c @@ -24,36 +24,78 @@ static uint8 *CHRRAM = NULL; static int masko8[8] = { 63, 31, 15, 1, 3, 0, 0, 0 }; +static uint8 oldversion = 0; +// this mapper is 176 rip mapper. + static void Super24PW(uint32 A, uint8 V) { - uint32 NV = V & masko8[EXPREGS[0] & 7]; - NV |= (EXPREGS[1] << 1); - setprg8r((NV >> 6) & 0xF, A, NV); + if (oldversion == 1) + { + uint32 NV = V & masko8[EXPREGS[0] & 7]; + NV |= (EXPREGS[1] << 1); + setprg8r((NV >> 6) & 0xF, A, NV); + } + else + { + setprg8(A, (EXPREGS[1] << 1) | (V & masko8[EXPREGS[0] & 0x7])); + } + } static void Super24CW(uint32 A, uint8 V) { - if (EXPREGS[0] & 0x20) - setchr1r(0x10, A, V); - else { - uint32 NV = V | (EXPREGS[2] << 3); - setchr1r((NV >> 9) & 0xF, A, NV); + if (oldversion == 1) + { + if (EXPREGS[0] & 0x20) + setchr1r(0x10, A, V); + else { + uint32 NV = V | (EXPREGS[2] << 3); + setchr1r((NV >> 9) & 0xF, A, NV); + } + } + else + { + if (EXPREGS[0] & 0x20) + setchr1r(0x10, A, (EXPREGS[2] << 3) | V); + else + setchr1r(0x00, A, (EXPREGS[2] << 3) | V); } } static DECLFW(Super24Write) { - switch (A) { - case 0x5FF0: - EXPREGS[0] = V; - FixMMC3PRG(MMC3_cmd); - FixMMC3CHR(MMC3_cmd); - break; - case 0x5FF1: - EXPREGS[1] = V; - FixMMC3PRG(MMC3_cmd); - break; - case 0x5FF2: - EXPREGS[2] = V; - FixMMC3CHR(MMC3_cmd); - break; + if (oldversion == 1) + { + switch (A) { + case 0x5FF0: + EXPREGS[0] = V; + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + break; + case 0x5FF1: + EXPREGS[1] = V; + FixMMC3PRG(MMC3_cmd); + break; + case 0x5FF2: + EXPREGS[2] = V; + FixMMC3CHR(MMC3_cmd); + break; + } + } + else + { + switch (A & 0xF003) { + case 0x5000: + EXPREGS[0] = V; + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + break; + case 0x5001: + EXPREGS[1] = V; + FixMMC3PRG(MMC3_cmd); + break; + case 0x5002: + EXPREGS[2] = V; + FixMMC3CHR(MMC3_cmd); + break; + } } } @@ -80,7 +122,37 @@ static void Super24Close(void) { } void Super24_Init(CartInfo *info) { - GenMMC3_Init(info, 128, 256, 0, 0); + + if (oldversion == 0) + { + uint32 _PRGsize = 0; + uint32 _CHRsize = 0; + int i = 0; + for (i = 0;i < 4;i++) + { + _PRGsize += PRGsize[i]; + _CHRsize += CHRsize[i]; + } + uint8* _CHRptr = (uint8*)FCEU_gmalloc(_CHRsize); + uint32 _CHROffset = 0; + for (i = 0;i < 4;i++) + { + memcpy(&_CHRptr[_CHROffset], CHRptr[i], CHRsize[i]); + _CHROffset += CHRsize[i]; + } + + uint8* _PRGptr = (uint8*)FCEU_gmalloc(_PRGsize); + uint32 _PRGOffset = 0; + for (i = 0;i < 4;i++) + { + memcpy(&_PRGptr[_PRGOffset], PRGptr[i], PRGsize[i]); + _PRGOffset += PRGsize[i]; + } + SetupCartCHRMapping(0, _CHRptr, _CHRsize, 0); + SetupCartPRGMapping(0, _PRGptr, _PRGsize, 0); + } + + GenMMC3_Init(info, 512, 512, 0, 0); info->Power = Super24Power; info->Reset = Super24Reset; info->Close = Super24Close; diff --git a/src/boards/vrc2and4.c b/src/boards/vrc2and4.c index 9749d48..b945b50 100644 --- a/src/boards/vrc2and4.c +++ b/src/boards/vrc2and4.c @@ -27,7 +27,7 @@ static uint8 isPirate, is22; static uint16 IRQCount; static uint8 IRQLatch, IRQa; -static uint8 prgreg[2], chrreg[8]; +static uint8 prgreg[4], chrreg[8]; static uint16 chrhi[8]; static uint8 regcmd, irqcmd, mirr, big_bank; static uint16 acount = 0; @@ -35,16 +35,29 @@ static uint16 acount = 0; static uint8 *WRAM = NULL; static uint32 WRAMSIZE; +static uint8 *_CHRptr = NULL;//for 400k+128K Contra J +static uint32 _CHRsize; + +static uint8 prgMask = 0x1F; + static SFORMAT StateRegs[] = { - { prgreg, 2, "PREG" }, + { prgreg, 4, "PREG" }, { chrreg, 8, "CREG" }, - { chrhi, 16, "CRGH" }, + { &chrhi[0], 2 | FCEUSTATE_RLSB, "CRH0" }, + { &chrhi[1], 2 | FCEUSTATE_RLSB, "CRH1" }, + { &chrhi[2], 2 | FCEUSTATE_RLSB, "CRH2" }, + { &chrhi[3], 2 | FCEUSTATE_RLSB, "CRH3" }, + { &chrhi[4], 2 | FCEUSTATE_RLSB, "CRH4" }, + { &chrhi[5], 2 | FCEUSTATE_RLSB, "CRH5" }, + { &chrhi[6], 2 | FCEUSTATE_RLSB, "CRH6" }, + { &chrhi[7], 2 | FCEUSTATE_RLSB, "CRH7" }, { ®cmd, 1, "CMDR" }, { &irqcmd, 1, "CMDI" }, { &mirr, 1, "MIRR" }, + { &prgMask, 1, "MAK" }, { &big_bank, 1, "BIGB" }, - { &IRQCount, 2, "IRQC" }, + { &IRQCount, 2 | FCEUSTATE_RLSB, "IRQC" }, { &IRQLatch, 1, "IRQL" }, { &IRQa, 1, "IRQA" }, { 0 } @@ -53,13 +66,13 @@ static SFORMAT StateRegs[] = static void Sync(void) { if (regcmd & 2) { setprg8(0xC000, prgreg[0] | big_bank); - setprg8(0x8000, ((~1) & 0x1F) | big_bank); + setprg8(0x8000, ((prgreg[2]) & prgMask) | big_bank); } else { setprg8(0x8000, prgreg[0] | big_bank); - setprg8(0xC000, ((~1) & 0x1F) | big_bank); + setprg8(0xC000, ((prgreg[2]) & prgMask) | big_bank); } setprg8(0xA000, prgreg[1] | big_bank); - setprg8(0xE000, ((~0) & 0x1F) | big_bank); + setprg8(0xE000, ((prgreg[3]) & prgMask) | big_bank); if (UNIFchrrama) setchr8(0); else { @@ -95,7 +108,7 @@ static DECLFW(VRC24Write) { case 0x8002: case 0x8003: if (!isPirate) { - prgreg[0] = V & 0x1F; + prgreg[0] = V & prgMask; Sync(); } break; @@ -104,10 +117,12 @@ static DECLFW(VRC24Write) { case 0xA002: case 0xA003: if (!isPirate) - prgreg[1] = V & 0x1F; + { + prgreg[1] = V & prgMask; + } else { - prgreg[0] = (V & 0x1F) << 1; - prgreg[1] = ((V & 0x1F) << 1) | 1; + prgreg[0] = (V & prgMask) << 1; + prgreg[1] = ((V & prgMask) << 1) | 1; } Sync(); break; @@ -174,6 +189,12 @@ static void M22Power(void) { static void M23Power(void) { big_bank = 0x20; + + if((prgreg[2] == 0x30) && (prgreg[3]== 0x31)) + { + big_bank = 0x00; + } + VRC24PowerCommon(M23Write); } @@ -207,6 +228,10 @@ static void VRC24Close(void) { if (WRAM) FCEU_gfree(WRAM); WRAM = NULL; + + if (_CHRptr) + FCEU_gfree(_CHRptr); + _CHRptr = NULL; } void Mapper22_Init(CartInfo *info) { @@ -222,6 +247,23 @@ void VRC24_Init(CartInfo *info) { info->Close = VRC24Close; MapIRQHook = VRC24IRQHook; GameStateRestore = StateRestore; + prgMask = 0x1F; + prgreg[2] = ~1; + prgreg[3] = ~0; + + if (info->CRC32 == 0xa20ad5d6)//400K PRG+ 128K CHR + { + prgreg[2] = 0x30; + prgreg[3] = 0x31; + prgMask = 0x3F; + big_bank = 0x00; + _CHRsize = 128 * 1024; + _CHRptr = (uint8*)FCEU_gmalloc(128*1024); + memcpy(&_CHRptr[112 * 1024], CHRptr[0], 16 * 1024); + memcpy(&_CHRptr[0], &PRGptr[0][400 * 1024], 112 * 1024); + SetupCartCHRMapping(0, _CHRptr, _CHRsize, 0); + AddExState(_CHRptr, _CHRsize, 0, "_CHR"); + } WRAMSIZE = 8192; WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE); diff --git a/src/ines.c b/src/ines.c index 781f4d3..d505a74 100644 --- a/src/ines.c +++ b/src/ines.c @@ -528,7 +528,8 @@ static BMAPPINGLocal bmap[] = { /* {(uint8_t*)"", 131, Mapper131_Init}, */ {(uint8_t*)"TXC/MGENIUS 22111", 132, UNL22211_Init}, {(uint8_t*)"SA72008", 133, SA72008_Init}, - {(uint8_t*)"MMC3 BMC PIRATE", 134, Mapper134_Init}, + //{(uint8_t*)"MMC3 BMC PIRATE", 134, Mapper134_Init}, + {(uint8_t*)"MMC3 BMC PIRATE", 134, Bs5652_Init}, /* {(uint8_t*)"", 135, Mapper135_Init}, */ {(uint8_t*)"TCU02", 136, TCU02_Init}, {(uint8_t*)"S8259D", 137, S8259D_Init}, @@ -727,6 +728,8 @@ static BMAPPINGLocal bmap[] = { {(uint8_t*)"G-146", 349, BMCG146_Init }, {(uint8_t*)"891227", 350, BMC891227_Init }, {(uint8_t*)"3D-BLOCK", 355, UNL3DBlock_Init }, + {(uint8_t*)"NC7000M", 391, NC7000M_Init }, + {(uint8_t*)"831019C J-2282", 402, J2282_Init }, {(uint8_t*)"SA-9602B", 513, SA9602B_Init }, {(uint8_t*)"DANCE2000", 518, UNLD2000_Init }, {(uint8_t*)"EH8813A", 519, UNLEH8813A_Init }, diff --git a/src/ines.h b/src/ines.h index 2b29b29..0121528 100644 --- a/src/ines.h +++ b/src/ines.h @@ -239,4 +239,8 @@ void Mapper255_Init(CartInfo *); void GN45_Init(CartInfo *info); /* m361, m366 */ void Mapper281_Init(CartInfo *); +void Bs5652_Init(CartInfo *); +void NC7000M_Init(CartInfo *); +void J2282_Init(CartInfo *); + #endif diff --git a/src/ppu.c b/src/ppu.c index f01162b..ee96d1f 100644 --- a/src/ppu.c +++ b/src/ppu.c @@ -90,8 +90,8 @@ static void makeppulut(void) { } } -static int ppudead = 1; -static int kook = 0; +static uint8 ppudead = 1; +static uint8 kook = 0; int fceuindbg = 0; int MMC5Hack = 0, PEC586Hack = 0; diff --git a/src/unif.c b/src/unif.c index 51502a4..61dcea1 100644 --- a/src/unif.c +++ b/src/unif.c @@ -426,10 +426,12 @@ static BMAPPING bmap[] = { { "8237A", 215, UNL8237A_Init, 0 }, { "830118C", 348, BMC830118C_Init, 0 }, { "A65AS", 285, BMCA65AS_Init, 0 }, + { "AB-G1L", NO_INES, AbG1l_Init, 0 }, { "AC08", NO_INES, AC08_Init, 0 }, /* Mapper 42.. but not.. Used for Green Beret */ { "ANROM", 7, ANROM_Init, 0 }, { "AX5705", 530, UNLAX5705_Init, 0 }, { "BB", 108, UNLBB_Init, 0 }, + { "BS-110",NO_INES, BS110_Init, 0 }, { "BS-5", 286, BMCBS5_Init, 0 }, { "CC-21", 27, UNLCC21_Init, 0 }, { "CITYFIGHT", 266, UNLCITYFIGHT_Init, 0 }, @@ -517,7 +519,7 @@ static BMAPPING bmap[] = { { "Sachen-8259C", 139, S8259C_Init, 0 }, { "Sachen-8259D", 137, S8259D_Init, 0 }, { "Super24in1SC03", 176, Super24_Init, 0 }, - { "Super24in1SC03", 176, Super24_Init, 0 }, + { "SUPER24IN1SC03", 176, Super24_Init, 0 }, { "SuperHIK8in1", 45, Mapper45_Init, 0 }, { "Supervision16in1", 53, Supervision16_Init, 0 }, { "T-227-1", NO_INES, BMCT2271_Init, 0 }, @@ -545,6 +547,7 @@ static BMAPPING bmap[] = { { "UNROM-512-32", 30, UNROM512_Init, BMCFLAG_32KCHRR }, { "UOROM", 2, UNROM_Init, 0 }, { "VRC7", 85, UNLVRC7_Init, 0 }, + { "WELL-NO-DG450",NO_INES, WellNoDG450_Init, 0 }, { "YOKO", 264, UNLYOKO_Init, 0 }, { "COOLBOY", 268, COOLBOY_Init, BMCFLAG_256KCHRR }, { "158B", 258, UNL158B_Init, 0 }, @@ -595,7 +598,8 @@ static BMAPPING bmap[] = { { "K-3033", 322, BMCK3033_Init, 0 }, { "830134C", 315, BMC830134C_Init, 0 }, { "GN-26", 344, BMCGN26_Init, 0 }, - { "T4A54A", 134, Mapper134_Init, 0 }, + { "KG256", NO_INES,KG256_Init, 0 }, + { "T4A54A", 134, Mapper134_Init, 0 }, #ifdef COPYFAMI { "COPYFAMI_MMC3", NO_INES, MapperCopyFamiMMC3_Init, 0 }, diff --git a/src/unif.h b/src/unif.h index 661fff3..b7dce10 100644 --- a/src/unif.h +++ b/src/unif.h @@ -192,6 +192,11 @@ void BMCK3033_Init(CartInfo *info); /* mm22 */ void BMC830134C_Init(CartInfo *info); /* m315 */ void BMCGN26_Init(CartInfo *info); /* m344 */ +void BS110_Init(CartInfo *info); +void WellNoDG450_Init(CartInfo *info); +void AbG1l_Init(CartInfo *info); +void KG256_Init(CartInfo *info); + #ifdef COPYFAMI void MapperCopyFamiMMC3_Init(CartInfo *info); void MapperCopyFami_Init(CartInfo *info);