Mapper 445: use the modularized ASIC cores.
This commit is contained in:
NewRisingSun
244
src/boards/445.c
244
src/boards/445.c
@@ -19,242 +19,100 @@
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*/
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#include "mapinc.h"
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#include "asic_latch.h"
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#include "asic_mmc3.h"
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#include "asic_vrc2and4.h"
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static uint8 reg[5], dip; /* Fourth register is the CNROM latch */
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static uint8 MMC3_reg[8], MMC3_index, MMC3_mirroring, MMC3_wram, MMC3_reload, MMC3_count, MMC3_irq;
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static uint8 VRC4_prg[2];
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static uint8 VRC4_mirroring;
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static uint8 VRC4_misc;
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static uint16 VRC4_chr[8];
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static uint8 VRCIRQ_latch;
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static uint8 VRCIRQ_mode;
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static uint8 VRCIRQ_count;
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static signed short int VRCIRQ_cycles;
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static uint8 *PRGCHR =NULL;
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static uint8 reg[4];
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static uint8 dip;
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static SFORMAT stateRegs[] = {
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{ reg, 5, "REGS" },
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{ &dip, 1, "DIPS" },
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{ MMC3_reg, 1, "MMC3" },
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{ &MMC3_index, 1, "M3IX" },
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{ &MMC3_mirroring, 1, "M3MI" },
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{ &MMC3_wram, 1, "M3WR" },
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{ &MMC3_reload, 1, "M3RL" },
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{ &MMC3_count, 1, "M3CN" },
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{ &MMC3_irq, 1, "M3IQ" },
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{ VRC4_prg, 2, "V4PR" },
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{ &VRC4_mirroring, 1, "V4MI" },
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{ &VRC4_misc, 1, "V4MS" },
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{ VRC4_chr, 16, "V4CH" },
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{ &VRCIRQ_latch, 1, "VILA" },
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{ &VRCIRQ_mode, 1, "VIMO" },
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{ &VRCIRQ_count, 1, "VICO" },
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{ &VRCIRQ_cycles, 2, "VICY" },
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{ reg, 4, "REGS" },
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{ &dip, 1, "DIPS" },
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{ 0 }
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};
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static void sync () {
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int chrAND;
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int chrOR;
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/*/ 5003.0-2: PRG size (1 MiB->8 KiB, although 1 MiB and 512 KiB are not connected and so function as 256 KiB) and mode (>=64 KiB: MMC3, <64 KiB: NROM-256/128/64) */
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int prgAND =0x7F >>(reg[2] &7) &0x1F;
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int prgAND = 0x7F >>(reg[2] &7) &0x1F; /* 5003.0-2: PRG size (1 MiB->8 KiB, although 1 MiB and 512 KiB are not connected and so function as 256 KiB) and mode (>=64 KiB: MMC3, <64 KiB: NROM-256/128/64) */
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int chrAND = 0x3FF >>(reg[2] >>3 &7) &0xFF; /* 5003.3-5: CHR size (1 MiB->8 KiB, though 1 MiB and 512 KiB are not reachable with inner bank registers and so function as 256 KiB) and mode (>=64 KiB: MMC3, <64 KiB: (C)NROM-256/128/64) */
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int prgOR = reg[0] &~prgAND;
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int chrOR = reg[1] <<3 &~chrAND;
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if (prgAND &0x04) {
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if (reg[3] &0x10) {
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setprg8(0x8000 ^(VRC4_misc <<13 &0x4000), VRC4_prg[0] &prgAND | reg[0] &~prgAND);
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setprg8(0xA000, VRC4_prg[1] &prgAND | reg[0] &~prgAND);
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setprg8(0xC000 ^(VRC4_misc <<13 &0x4000), 0xFE &prgAND | reg[0] &~prgAND);
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setprg8(0xE000, 0xFF &prgAND | reg[0] &~prgAND);
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} else {
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setprg8(0x8000 ^(MMC3_index <<8 &0x4000), MMC3_reg[6] &prgAND | reg[0] &~prgAND);
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setprg8(0xA000, MMC3_reg[7] &prgAND | reg[0] &~prgAND);
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setprg8(0xC000 ^(MMC3_index <<8 &0x4000), 0xFE &prgAND | reg[0] &~prgAND);
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setprg8(0xE000, 0xFF &prgAND | reg[0] &~prgAND);
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}
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if (reg[3] &0x10)
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VRC24_syncPRG(prgAND, prgOR);
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else
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MMC3_syncPRG(prgAND, prgOR);
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} else {
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setprg8(0x8000, 0 &prgAND | reg[0] &~prgAND);
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setprg8(0xA000, 1 &prgAND | reg[0] &~prgAND);
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setprg8(0xC000, 2 &prgAND | reg[0] &~prgAND);
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setprg8(0xE000, 3 &prgAND | reg[0] &~prgAND);
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setprg8(0x8000, 0 &prgAND | prgOR);
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setprg8(0xA000, 1 &prgAND | prgOR);
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setprg8(0xC000, 2 &prgAND | prgOR);
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setprg8(0xE000, 3 &prgAND | prgOR);
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}
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/* // 5003.3-5: CHR size (1 MiB->8 KiB, though 1 MiB and 512 KiB are not reachable with inner bank registers and so function as 256 KiB) and mode (>=64 KiB: MMC3, <64 KiB: (C)NROM-256/128/64) */
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chrAND =0x3FF >>(reg[2] >>3 &7) &0xFF;
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if (chrAND &0x20) {
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if (reg[3] &0x10) {
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setchr1(0x0000, VRC4_chr[0] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0400, VRC4_chr[1] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0800, VRC4_chr[2] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0C00, VRC4_chr[3] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1000, VRC4_chr[4] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1400, VRC4_chr[5] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1800, VRC4_chr[6] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1C00, VRC4_chr[7] &chrAND | (reg[1] <<3) &~chrAND);
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} else {
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setchr1(0x0000 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] &0xFE)&chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0400 ^(MMC3_index <<5 &0x1000),(MMC3_reg[0] |0x01)&chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0800 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] &0xFE)&chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x0C00 ^(MMC3_index <<5 &0x1000),(MMC3_reg[1] |0x01)&chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1000 ^(MMC3_index <<5 &0x1000), MMC3_reg[2] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1400 ^(MMC3_index <<5 &0x1000), MMC3_reg[3] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1800 ^(MMC3_index <<5 &0x1000), MMC3_reg[4] &chrAND | (reg[1] <<3) &~chrAND);
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setchr1(0x1C00 ^(MMC3_index <<5 &0x1000), MMC3_reg[5] &chrAND | (reg[1] <<3) &~chrAND);
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}
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if (reg[3] &0x10)
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VRC24_syncCHR(chrAND, chrOR);
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else
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MMC3_syncCHR(chrAND, chrOR);
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} else {
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chrAND >>=3;
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setchr8(reg[4] &chrAND | reg[1] &~chrAND);
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chrAND >>= 3;
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chrOR >>= 3;
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setchr8(Latch_data &chrAND | chrOR);
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}
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if (reg[3] &0x10)
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setmirror(VRC4_mirroring &3 ^(VRC4_mirroring &2? 0: 1));
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VRC24_syncMirror();
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else
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setmirror(MMC3_mirroring &1 ^1);
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SetReadHandler(0x8000, 0xFFFF, reg[0] &0xC0 && (reg[0] &0xC0) ==dip? NULL: CartBR);
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MMC3_syncMirror();
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SetReadHandler(0x8000, 0xFFFF, reg[0] &0xC0 && (reg[0] &0xC0) == dip? NULL: CartBR);
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}
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static DECLFW(writeCNROM) {
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reg[4] =V;
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sync();
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}
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static DECLFW(writeMMC3) {
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switch(A &0xE001) {
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case 0x8000: MMC3_index =V; sync(); break;
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case 0x8001: MMC3_reg[MMC3_index &7] =V; sync(); break;
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case 0xA000: MMC3_mirroring =V; sync(); break;
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case 0xA001: MMC3_wram =V; sync(); break;
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case 0xC000: MMC3_reload =V; break;
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case 0xC001: MMC3_count =0; break;
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case 0xE000: MMC3_irq =0; X6502_IRQEnd(FCEU_IQEXT); break;
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case 0xE001: MMC3_irq =1; break;
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}
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}
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static DECLFW(writeVRC4) {
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uint8 index;
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if (reg[3] &1)
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A =(A &0xA? 1: 0) | (A &0x5? 2: 0) | A &0xF000;
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static void applyMode(uint8 clear) {
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if ((reg[2] >>3 &7) >= 5)
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Latch_activate(clear, sync, 0x8000, 0xFFFF, NULL);
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else
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A =(A &0x5? 1: 0) | (A &0xA? 2: 0) | A &0xF000;
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switch (A &0xF000) {
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case 0x8000: case 0xA000:
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VRC4_prg[A >>13 &1] =V;
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sync();
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break;
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case 0x9000:
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if (~A &2)
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VRC4_mirroring =V;
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if (reg[3] &0x10) {
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if (reg[3] &0x01)
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VRC4_activate(clear, sync, 0x0A, 0x05, 1, NULL, NULL, NULL, NULL, NULL);
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else
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if (~A &1)
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VRC4_misc =V;
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sync();
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break;
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case 0xF000:
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switch (A &3) {
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case 0: VRCIRQ_latch =VRCIRQ_latch &0xF0 | V &0x0F; break;
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case 1: VRCIRQ_latch =VRCIRQ_latch &0x0F | V <<4; break;
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case 2: VRCIRQ_mode =V;
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if (VRCIRQ_mode &0x02) {
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VRCIRQ_count =VRCIRQ_latch;
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VRCIRQ_cycles =341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3: VRCIRQ_mode =VRCIRQ_mode &~0x02 | VRCIRQ_mode <<1 &0x02;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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break;
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default:
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index =(A -0xB000) >>11 &~1 | A >>1 &1;
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if (A &1)
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VRC4_chr[index] =VRC4_chr[index] & 0x0F | V <<4;
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else
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VRC4_chr[index] =VRC4_chr[index] &~0x0F | V &0x0F;
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sync();
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break;
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}
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}
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static void FP_FASTAPASS(1) cpuCycle(int a) {
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if ((reg[0] &3) ==3) while (a--) { /* VRC4 mode */
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if (VRCIRQ_mode &0x02 && (VRCIRQ_mode &0x04 || (VRCIRQ_cycles -=3) <=0)) {
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if (~VRCIRQ_mode &0x04) VRCIRQ_cycles +=341;
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if (!++VRCIRQ_count) {
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VRCIRQ_count =VRCIRQ_latch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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}
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static void horizontalBlanking(void) {
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if (~reg[0] &2) { /* MMC3 mode */
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MMC3_count =!MMC3_count? MMC3_reload: --MMC3_count;
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if (!MMC3_count && MMC3_irq) X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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static void applyMode() {
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if ((reg[2] >>3 &7) >=5)
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SetWriteHandler(0x8000, 0xFFFF, writeCNROM);
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else
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if (reg[3] &0x10)
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SetWriteHandler(0x8000, 0xFFFF, writeVRC4);
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else
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SetWriteHandler(0x8000, 0xFFFF, writeMMC3);
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VRC4_activate(clear, sync, 0x05, 0x0A, 1, NULL, NULL, NULL, NULL, NULL);
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} else
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MMC3_activate(clear, sync, MMC3_TYPE_SHARP, NULL, NULL, NULL, NULL);
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}
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static void Mapper445_restore (int version) {
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applyMode();
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applyMode(0);
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sync();
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}
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static DECLFW(writeReg) {
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if (~reg[3] &0x20) {
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reg[A &3] =V;
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if ((A &3) ==3) applyMode();
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reg[A &3] = V;
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if ((A &3) == 3) applyMode(1);
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sync();
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}
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}
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static void Mapper445_power(void) {
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int i;
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for (i =0; i <4; i++) reg[i] =0;
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for (i =0; i <8; i++) MMC3_reg[i] =0;
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for (i =0; i <2; i++) VRC4_prg[i] =0;
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for (i =0; i <8; i++) VRC4_chr[i] =0;
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MMC3_index =MMC3_mirroring =MMC3_wram =MMC3_reload =MMC3_count =MMC3_irq =0;
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VRC4_mirroring =VRC4_misc =VRCIRQ_latch =VRCIRQ_mode =VRCIRQ_count =VRCIRQ_cycles =0;
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reg[0] = reg[1] = reg[2] = reg[3] = 0;
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dip =0;
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetWriteHandler(0x5000, 0x5FFF, writeReg);
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applyMode();
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sync();
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applyMode(1);
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}
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static void Mapper445_reset (void) {
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int i;
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for (i =0; i <5; i++) reg[i] =0;
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dip +=0x40;
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applyMode();
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sync();
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}
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static void Mapper445_close(void) {
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if (PRGCHR) FCEU_gfree(PRGCHR);
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PRGCHR =NULL;
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reg[0] = reg[1] = reg[2] = reg[3] = 0;
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dip += 0x40;
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applyMode(1);
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}
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void Mapper445_Init (CartInfo *info) {
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Latch_addExState();
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MMC3_addExState();
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VRC24_addExState();
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info->Reset = Mapper445_reset;
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info->Power = Mapper445_power;
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info->Close = Mapper445_close;
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MapIRQHook = cpuCycle;
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GameHBIRQHook = horizontalBlanking;
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GameStateRestore = Mapper445_restore;
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AddExState(stateRegs, ~0, 0, 0);
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AddExState(stateRegs, ~0, 0, 0);
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}
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