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Overall cleanup.

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This commit is contained in:
NewRisingSun
2025-09-12 21:59:27 +02:00
parent 19e357c040
commit db279aa338
86 changed files with 476 additions and 476 deletions
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12
src/boards/183.c
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@@ -23,7 +23,7 @@
static uint8 prg; static uint8 prg;
static SFORMAT Mapper183_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &prg, 1, "PRG6" }, { &prg, 1, "PRG6" },
{ 0 } { 0 }
}; };
@@ -35,18 +35,18 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(Mapper183_writePRG) { static DECLFW (writePRG) {
prg =A &0xFF; prg =A &0xFF;
sync(); sync();
} }
void Mapper183_power(void) { static void power(void) {
prg =0; prg =0;
VRC24_power(); VRC24_power();
} }
void Mapper183_Init (CartInfo *info) { void Mapper183_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, CartBR, Mapper183_writePRG, NULL); VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, CartBR, writePRG, NULL);
AddExState(Mapper183_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
info->Power =Mapper183_power; info->Power =power;
} }

22
src/boards/222.c
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@@ -27,7 +27,7 @@ static uint8 counter1;
static uint8 counter2; static uint8 counter2;
static uint8 prescaler; static uint8 prescaler;
static SFORMAT Mapper222_stateRegs[] ={ static SFORMAT stateRegs[] = {
{ &clockMode, 1, "CLKM" }, { &clockMode, 1, "CLKM" },
{ &pending, 1, "PEND" }, { &pending, 1, "PEND" },
{ &counter1, 1, "CNT1" }, { &counter1, 1, "CNT1" },
@@ -42,18 +42,18 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(Mapper222_nibblizeCHR) { static DECLFW (nibblizeCHR) {
if (~A &1) { if (~A &1) {
VRC24_writeReg(A, V); VRC24_writeReg(A, V);
VRC24_writeReg(A |1, V >>4); VRC24_writeReg(A |1, V >>4);
} }
} }
DECLFW(Mapper222_writeIRQ) { static DECLFW (writeIRQ) {
switch(A &3) { switch(A &3) {
case 0: clockMode = 0; case 0: clockMode = 0;
break; break;
case 1: pending =false; case 1: pending = 0;
if (!clockMode) { if (!clockMode) {
counter1 = V &0xF; counter1 = V &0xF;
counter2 = V >>4; counter2 = V >>4;
@@ -64,7 +64,7 @@ DECLFW(Mapper222_writeIRQ) {
} }
} }
void FP_FASTAPASS(1) Mapper222_cpuCycle(int a) { static void FP_FASTAPASS(1) cpuCycle (int a) {
while (a--) { while (a--) {
uint8 previousPrescaler = prescaler; uint8 previousPrescaler = prescaler;
if (pending) if (pending)
@@ -83,16 +83,16 @@ void FP_FASTAPASS(1) Mapper222_cpuCycle(int a) {
} }
} }
void Mapper222_power(void) { static void power (void) {
clockMode = pending = counter1 = counter2 = prescaler = 0; clockMode = pending = counter1 = counter2 = prescaler = 0;
VRC24_power(); VRC24_power();
SetWriteHandler(0xB000, 0xEFFF, Mapper222_nibblizeCHR); SetWriteHandler(0xB000, 0xEFFF, nibblizeCHR);
SetWriteHandler(0xF000, 0xFFFF, Mapper222_writeIRQ); SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
} }
void Mapper222_Init (CartInfo *info) { void Mapper222_Init (CartInfo *info) {
VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL); VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
AddExState(Mapper222_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
info->Power =Mapper222_power; info->Power =power;
MapIRQHook =Mapper222_cpuCycle; MapIRQHook = cpuCycle;
} }

4
src/boards/252_253.c
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@@ -54,7 +54,7 @@ static DECLFW(Mapper252_253_interceptPPUWrite) {
writePPU(A, V); writePPU(A, V);
} }
void Mapper252_power (void) { static void Mapper252_power (void) {
mask = 0xFE; mask = 0xFE;
compare = 0x06; compare = 0x06;
VRC24_power(); VRC24_power();
@@ -62,7 +62,7 @@ void Mapper252_power (void) {
SetWriteHandler(0x2007, 0x2007, Mapper252_253_interceptPPUWrite); SetWriteHandler(0x2007, 0x2007, Mapper252_253_interceptPPUWrite);
} }
void Mapper253_power (void) { static void Mapper253_power (void) {
mask = 0xFE; /* There are two board revisions, the earlier one with a non-switchable mask/compare FE/04 and a later switchable one that starts with FC/28 */ mask = 0xFE; /* There are two board revisions, the earlier one with a non-switchable mask/compare FE/04 and a later switchable one that starts with FC/28 */
compare = 0x04; compare = 0x04;
VRC24_power(); VRC24_power();

16
src/boards/266.c
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@@ -23,7 +23,7 @@
static uint8 prg; static uint8 prg;
static SFORMAT UNLCITYFIGHT_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &prg, 1, "PRG8" }, { &prg, 1, "PRG8" },
{ 0 } { 0 }
}; };
@@ -34,7 +34,7 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(UNLCITYFIGHT_externalSelect) { static DECLFW (externalSelect) {
if (A &0x800) if (A &0x800)
(GetWriteHandler(0x4011))(0x4011, V <<3 &0x78); (GetWriteHandler(0x4011))(0x4011, V <<3 &0x78);
else { else {
@@ -43,18 +43,18 @@ DECLFW(UNLCITYFIGHT_externalSelect) {
} }
} }
DECLFW(UNLCITYFIGHT_unscrambleAddress) { static DECLFW (unscrambleAddress) {
VRC24_writeReg(A &~0x6000 | A <<1 &0x4000 | A >>1 &0x2000, V); VRC24_writeReg(A &~0x6000 | A <<1 &0x4000 | A >>1 &0x2000, V);
} }
void UNLCITYFIGHT_power(void) { static void power (void) {
prg =0; prg =0;
VRC24_power(); VRC24_power();
SetWriteHandler(0x8000, 0xFFFF, UNLCITYFIGHT_unscrambleAddress); SetWriteHandler(0x8000, 0xFFFF, unscrambleAddress);
} }
void UNLCITYFIGHT_Init (CartInfo *info) { void UNLCITYFIGHT_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, UNLCITYFIGHT_externalSelect); VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, externalSelect);
AddExState(UNLCITYFIGHT_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
info->Power =UNLCITYFIGHT_power; info->Power =power;
} }

16
src/boards/308.c
View File

@@ -25,7 +25,7 @@ static uint8 irqEnabled;
static uint16 irqCounterLow; static uint16 irqCounterLow;
static uint8 irqCounterHigh; static uint8 irqCounterHigh;
static SFORMAT UNLTH21311_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &irqEnabled, 1, "IRQE" }, { &irqEnabled, 1, "IRQE" },
{ &irqCounterLow, 2 | FCEUSTATE_RLSB, "CNTL" }, { &irqCounterLow, 2 | FCEUSTATE_RLSB, "CNTL" },
{ &irqCounterHigh, 1, "CNTH" }, { &irqCounterHigh, 1, "CNTH" },
@@ -38,7 +38,7 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(UNLTH21311_writeIRQ) { static DECLFW (writeIRQ) {
switch(A &3) { switch(A &3) {
case 0: X6502_IRQEnd(FCEU_IQEXT); case 0: X6502_IRQEnd(FCEU_IQEXT);
irqEnabled =0; irqEnabled =0;
@@ -51,22 +51,22 @@ DECLFW(UNLTH21311_writeIRQ) {
} }
} }
void FP_FASTAPASS(1) UNLTH21311_cpuCycle(int a) { static void FP_FASTAPASS(1) cpuCycle (int a) {
while (a--) if (irqEnabled) { while (a--) if (irqEnabled) {
if ((++irqCounterLow &4095) ==2048) irqCounterHigh--; if ((++irqCounterLow &4095) ==2048) irqCounterHigh--;
if (!irqCounterHigh && (irqCounterLow &4095) <2048) X6502_IRQBegin(FCEU_IQEXT); if (!irqCounterHigh && (irqCounterLow &4095) <2048) X6502_IRQBegin(FCEU_IQEXT);
} }
} }
void UNLTH21311_power(void) { static void power (void) {
irqEnabled =irqCounterLow =irqCounterHigh =0; irqEnabled =irqCounterLow =irqCounterHigh =0;
VRC24_power(); VRC24_power();
SetWriteHandler(0xF000, 0xFFFF, UNLTH21311_writeIRQ); SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
} }
void UNLTH21311_Init (CartInfo *info) { void UNLTH21311_Init (CartInfo *info) {
VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL); VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
AddExState(UNLTH21311_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
info->Power =UNLTH21311_power; info->Power =power;
MapIRQHook =UNLTH21311_cpuCycle; MapIRQHook =cpuCycle;
} }

19
src/boards/351.c
View File

@@ -107,7 +107,7 @@ static void applyMode (uint8 clear) {
MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, NULL, NULL, NULL, NULL); MMC1_activate(clear, sync, MMC1_TYPE_MMC1B, NULL, NULL, NULL, NULL);
} }
static void Mapper351_restore (int version) { static void restore (int version) {
applyMode(0); applyMode(0);
sync(); sync();
} }
@@ -125,7 +125,7 @@ static DECLFW(writeFDSMirroring) {
MMC3_writeReg(0xA000, V >>3 &1); MMC3_writeReg(0xA000, V >>3 &1);
} }
static void Mapper351_power(void) { static void power (void) {
reg[0] = reg[1] = reg[2] = reg[3] = 0; reg[0] = reg[1] = reg[2] = reg[3] = 0;
dip = 0; dip = 0;
SetReadHandler(0x5000, 0x5FFF, readDIP); SetReadHandler(0x5000, 0x5FFF, readDIP);
@@ -135,13 +135,13 @@ static void Mapper351_power(void) {
applyMode(1); applyMode(1);
} }
static void Mapper351_reset (void) { static void reset (void) {
reg[0] = reg[1] = reg[2] = reg[3] = 0; reg[0] = reg[1] = reg[2] = reg[3] = 0;
dip++; dip++;
applyMode(1); applyMode(1);
} }
static void Mapper351_close(void) { static void close (void) {
if (CHRRAM) FCEU_gfree(CHRRAM); if (CHRRAM) FCEU_gfree(CHRRAM);
if (PRGCHR) FCEU_gfree(PRGCHR); if (PRGCHR) FCEU_gfree(PRGCHR);
CHRRAM = NULL; CHRRAM = NULL;
@@ -153,20 +153,21 @@ void Mapper351_Init (CartInfo *info) {
MMC1_addExState(); MMC1_addExState();
MMC3_addExState(); MMC3_addExState();
VRC24_addExState(); VRC24_addExState();
info->Reset = Mapper351_reset; info->Reset = reset;
info->Power = Mapper351_power; info->Power = power;
info->Close = Mapper351_close; info->Close = close;
GameStateRestore = Mapper351_restore; GameStateRestore = restore;
AddExState(stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
/* When CHR-RAM is enabled, CHR-ROM becomes part of PRG-ROM address space. */ /* When CHR-RAM is enabled, CHR-ROM becomes part of PRG-ROM address space. */
prgMask_CHRROM = prgMask_CHRRAM = PRGsize[0] /8192 -1; prgMask_CHRROM = prgMask_CHRRAM = PRGsize[0] /8192 -1;
if (CHRRAMSIZE) { if (CHRRAMSIZE) {
uint8* newROM;
CHRRAM = (uint8 *)FCEU_gmalloc(CHRRAMSIZE); CHRRAM = (uint8 *)FCEU_gmalloc(CHRRAMSIZE);
SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1); SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1);
AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM"); AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM");
prgMask_CHRRAM = (PRGsize[0] +CHRsize[0]) /8192 -1; prgMask_CHRRAM = (PRGsize[0] +CHRsize[0]) /8192 -1;
uint8* newROM = (uint8*)FCEU_gmalloc(PRGsize[0] +CHRsize[0]); newROM = (uint8*)FCEU_gmalloc(PRGsize[0] +CHRsize[0]);
memcpy(newROM, ROM, info->PRGRomSize); memcpy(newROM, ROM, info->PRGRomSize);
memcpy(newROM +PRGsize[0], VROM, info->CHRRomSize); memcpy(newROM +PRGsize[0], VROM, info->CHRRomSize);
FCEU_gfree(ROM); FCEU_gfree(ROM);

14
src/boards/362.c
View File

@@ -23,7 +23,7 @@
static uint8 game; static uint8 game;
static SFORMAT Mapper362_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &game, 1, "GAME" }, { &game, 1, "GAME" },
{ 0 } { 0 }
}; };
@@ -40,21 +40,21 @@ static void sync () {
} }
} }
void Mapper362_power(void) { static void power (void) {
game =0; game =0;
VRC24_power(); VRC24_power();
} }
void Mapper362_reset(void) { static void reset (void) {
game ^=1; game ^=1;
sync(); VRC24_clear();
} }
void Mapper362_Init (CartInfo *info) { void Mapper362_Init (CartInfo *info) {
VRC4_init(info, sync, 0x01, 0x02, 0, NULL, NULL, NULL, NULL, NULL); VRC4_init(info, sync, 0x01, 0x02, 0, NULL, NULL, NULL, NULL, NULL);
info->Power =Mapper362_power; info->Power = power;
if (PRGsize[0] >512*1024) { if (PRGsize[0] >512*1024) {
info->Reset =Mapper362_reset; info->Reset = reset;
AddExState(Mapper362_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }
} }

18
src/boards/384.c
View File

@@ -24,7 +24,7 @@
static uint8 reg; static uint8 reg;
static SFORMAT Mapper384_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &reg, 1, "EXP0" }, { &reg, 1, "EXP0" },
{ 0 } { 0 }
}; };
@@ -36,7 +36,7 @@ static void sync () {
VRC24_syncWRAM(0); VRC24_syncWRAM(0);
} }
DECLFW(Mapper384_writeReg) { static DECLFW (writeReg) {
if (A &0x800 && ~reg &0x08) { if (A &0x800 && ~reg &0x08) {
reg =V; reg =V;
sync(); sync();
@@ -44,20 +44,20 @@ DECLFW(Mapper384_writeReg) {
CartBW(A, V); CartBW(A, V);
} }
void Mapper384_power(void) { static void power (void) {
reg =0; reg =0;
VRC24_power(); VRC24_power();
} }
void Mapper384_reset(void) { static void reset (void) {
reg =0; reg =0;
sync(); VRC24_clear();
} }
void Mapper384_Init (CartInfo *info) { void Mapper384_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, Mapper384_writeReg, NULL); VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, writeReg, NULL);
WRAM_init(info, 2); WRAM_init(info, 2);
info->Power =Mapper384_power; info->Power =power;
info->Reset =Mapper384_reset; info->Reset =reset;
AddExState(Mapper384_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }

18
src/boards/398.c
View File

@@ -23,7 +23,7 @@
static uint8 reg; static uint8 reg;
static SFORMAT Mapper398_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &reg, 1, "EXP0" }, { &reg, 1, "EXP0" },
{ 0 } { 0 }
}; };
@@ -39,25 +39,25 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(Mapper398_writeReg) { static DECLFW (writeReg) {
reg =A &0xFF; reg =A &0xFF;
VRC24_writeReg(A, V); VRC24_writeReg(A, V);
} }
void Mapper398_power(void) { static void power (void) {
reg = 0xC0; reg = 0xC0;
VRC24_power(); VRC24_power();
SetWriteHandler(0x8000, 0xFFFF, Mapper398_writeReg); SetWriteHandler(0x8000, 0xFFFF, writeReg);
} }
void Mapper398_reset(void) { static void reset (void) {
reg = 0xC0; reg = 0xC0;
sync(); VRC24_clear();
} }
void Mapper398_Init (CartInfo *info) { void Mapper398_Init (CartInfo *info) {
VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL); VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL);
info->Power =Mapper398_power; info->Power = power;
info->Reset =Mapper398_reset; info->Reset = reset;
AddExState(Mapper398_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }

2
src/boards/432.c
View File

@@ -69,7 +69,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg[0] = reg[1] = 0; reg[0] = reg[1] = 0;
++pad; ++pad;
sync(); MMC3_clear();
} }
static void power () { static void power () {

22
src/boards/447.c
View File

@@ -25,7 +25,7 @@
static uint8 reg; static uint8 reg;
static uint8 dip; static uint8 dip;
static SFORMAT Mapper447_stateRegs[] ={ static SFORMAT stateRegs[] = {
{ &reg, 1, "EXP0" }, { &reg, 1, "EXP0" },
{ &dip, 1, "DIPS" }, { &dip, 1, "DIPS" },
{ 0 } { 0 }
@@ -38,7 +38,7 @@ static void sync () {
VRC24_syncWRAM(0); VRC24_syncWRAM(0);
} }
static int Mapper447_getPRGBank(uint8 bank) { static int getPRGBank (uint8 bank) {
if (reg &4) { if (reg &4) {
if (~reg &2) if (~reg &2)
return VRC24_getPRGBank(bank &1) &~2 | bank &2; return VRC24_getPRGBank(bank &1) &~2 | bank &2;
@@ -48,11 +48,11 @@ static int Mapper447_getPRGBank(uint8 bank) {
return VRC24_getPRGBank(bank); return VRC24_getPRGBank(bank);
} }
DECLFR(Mapper447_readPRG) { static DECLFR (readPRG) {
return CartBR(reg &8? (A &~3 | dip &3): A); return CartBR(reg &8? (A &~3 | dip &3): A);
} }
DECLFW(Mapper447_writeReg) { static DECLFW (writeReg) {
if (~reg &1) { if (~reg &1) {
reg = A &0xFF; reg = A &0xFF;
sync(); sync();
@@ -60,23 +60,23 @@ DECLFW(Mapper447_writeReg) {
CartBW(A, V); CartBW(A, V);
} }
void Mapper447_power(void) { static void power (void) {
reg = 0; reg = 0;
dip = 0; dip = 0;
VRC24_power(); VRC24_power();
SetReadHandler(0x8000, 0xFFFF, Mapper447_readPRG); SetReadHandler(0x8000, 0xFFFF, readPRG);
} }
void Mapper447_reset(void) { static void reset (void) {
reg = 0; reg = 0;
dip++; dip++;
sync(); sync();
} }
void Mapper447_Init (CartInfo *info) { void Mapper447_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 0, Mapper447_getPRGBank, NULL, NULL, Mapper447_writeReg, NULL ); VRC4_init(info, sync, 0x04, 0x08, 0, getPRGBank, NULL, NULL, writeReg, NULL );
WRAM_init(info, 2); WRAM_init(info, 2);
info->Power =Mapper447_power; info->Power = power;
info->Reset =Mapper447_reset; info->Reset = reset;
AddExState(Mapper447_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }

22
src/boards/448.c
View File

@@ -24,7 +24,7 @@
static uint8 reg; static uint8 reg;
static SFORMAT Mapper448_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &reg, 1, "EXP0" }, { &reg, 1, "EXP0" },
{ 0 } { 0 }
}; };
@@ -46,31 +46,31 @@ static void sync () {
setchr8(0); setchr8(0);
} }
DECLFW(Mapper448_writeReg) { static DECLFW (writeReg) {
reg =A &0xFF; reg =A &0xFF;
sync(); sync();
CartBW(A, V); CartBW(A, V);
} }
DECLFW(Mapper448_writePRG) { static DECLFW (writePRG) {
VRC24_writeReg(reg &8? 0x8000: A, V); VRC24_writeReg(reg &8? 0x8000: A, V);
} }
void Mapper448_power(void) { static void power (void) {
reg =0; reg =0;
VRC24_power(); VRC24_power();
SetWriteHandler(0x8000, 0xFFFF, Mapper448_writePRG); SetWriteHandler(0x8000, 0xFFFF, writePRG);
} }
void Mapper448_reset(void) { static void reset (void) {
reg =0; reg =0;
sync(); VRC24_clear();
} }
void Mapper448_Init (CartInfo *info) { void Mapper448_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, Mapper448_writeReg, NULL); VRC4_init(info, sync, 0x04, 0x08, 0, NULL, NULL, NULL, writeReg, NULL);
WRAM_init(info, 2); WRAM_init(info, 2);
info->Power =Mapper448_power; info->Power =power;
info->Reset =Mapper448_reset; info->Reset =reset;
AddExState(Mapper448_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }

3
src/boards/449.c
View File

@@ -75,8 +75,7 @@ static void power () {
static void reset () { static void reset () {
pad++; pad++;
padSelect = 0; padSelect = 0;
Latch_address = 0; Latch_clear();
sync();
} }
void Mapper449_Init (CartInfo *info) { void Mapper449_Init (CartInfo *info) {

6
src/boards/450.c
View File

@@ -27,12 +27,12 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
void Mapper450_reset(void) { static void reset(void) {
VRC2_pins = 0; VRC2_pins = 0;
sync(); VRC24_clear();
} }
void Mapper450_Init (CartInfo *info) { void Mapper450_Init (CartInfo *info) {
VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL); VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
info->Reset =Mapper450_reset; info->Reset = reset;
} }

2
src/boards/458.c
View File

@@ -1,7 +1,7 @@
/* FCEUmm - NES/Famicom Emulator /* FCEUmm - NES/Famicom Emulator
* *
* Copyright notice for this file: * Copyright notice for this file:
* Copyright (C) 2020 * Copyright (C) 2025 NewRisingSun
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by

15
src/boards/460.c
View File

@@ -22,11 +22,11 @@
#include "mapinc.h" #include "mapinc.h"
#include "asic_mmc3.h" #include "asic_mmc3.h"
#include "cartram.h"
static uint8 submapper; static uint8 submapper;
static uint8 reg; static uint8 reg;
static uint8 pad; static uint8 pad;
static uint8 *CHRRAM = NULL;
static DECLFR (readPad) { static DECLFR (readPad) {
return CartBR(A &~3 | pad &3); return CartBR(A &~3 | pad &3);
@@ -74,23 +74,12 @@ static void power () {
MMC3_power(); MMC3_power();
} }
static void close () {
if (CHRRAM) {
FCEU_gfree(CHRRAM);
CHRRAM = NULL;
}
}
void Mapper460_Init (CartInfo *info) { void Mapper460_Init (CartInfo *info) {
submapper = info->submapper; submapper = info->submapper;
MMC3_init(info, sync, MMC3_TYPE_SHARP, getPRGBank, getCHRBank, NULL, writeReg); MMC3_init(info, sync, MMC3_TYPE_SHARP, getPRGBank, getCHRBank, NULL, writeReg);
CHRRAM_init(info, 8);
info->Power = power; info->Power = power;
info->Reset = reset; info->Reset = reset;
info->Close = close;
AddExState(&reg, 1, 0, "EXPR"); AddExState(&reg, 1, 0, "EXPR");
AddExState(&reg, 1, 0, "DIPS"); AddExState(&reg, 1, 0, "DIPS");
CHRRAM = (uint8 *)FCEU_gmalloc(8192);
SetupCartCHRMapping(0x10, CHRRAM, 8192, 1);
AddExState(CHRRAM, 8192, 0, "CRAM");
} }

4
src/boards/468.c
View File

@@ -67,7 +67,7 @@ static const uint16 lut509[512] = { /* Look-up table, used only by Legendary Gam
483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 512, 513, 514, 515, 516, 517 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 512, 513, 514, 515, 516, 517
}; };
void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */ static void setPins(uint8 select, uint8 newClock, uint8 newData) { /* Serial EEPROM */
if (select) if (select)
state = 0; state = 0;
else else
@@ -160,7 +160,7 @@ static void sync_LF36 (int prgOR) {
setmirror(reg[0] &0x04? MI_H: MI_V); setmirror(reg[0] &0x04? MI_H: MI_V);
} }
void FP_FASTAPASS(1) LF36_cpuCycle (int a) { static void FP_FASTAPASS(1) LF36_cpuCycle (int a) {
while (a--) { while (a--) {
if (Custom_reg[1] &1) { if (Custom_reg[1] &1) {
if (!++Custom_reg[2]) ++Custom_reg[3]; if (!++Custom_reg[2]) ++Custom_reg[3];

1
src/boards/483.c
View File

@@ -69,6 +69,7 @@ static void power () {
static void stateRestore (int version) { static void stateRestore (int version) {
applyMode(0); applyMode(0);
} }
void Mapper483_Init (CartInfo *info) { void Mapper483_Init (CartInfo *info) {
AddExState(&game, 1, 0, "GAME"); AddExState(&game, 1, 0, "GAME");
Latch_addExState(); Latch_addExState();

12
src/boards/490.c
View File

@@ -47,18 +47,18 @@ static DECLFW(writeReg) {
sync(); sync();
} }
static void reset() {
reg = 0;
++pad;
sync();
}
static void power () { static void power () {
reg = 0; reg = 0;
pad = 0; pad = 0;
MMC3_power(); MMC3_power();
} }
static void reset () {
reg = 0;
++pad;
MMC3_clear();
}
void Mapper490_Init (CartInfo *info) { void Mapper490_Init (CartInfo *info) {
MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg); MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, writeReg);
info->Power = power; info->Power = power;

2
src/boards/503.c
View File

@@ -50,7 +50,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
++pad; ++pad;
sync(); MMC3_clear();
} }
static void power () { static void power () {

2
src/boards/504.c
View File

@@ -49,7 +49,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
sync(); MMC3_clear();
} }
static void power () { static void power () {

2
src/boards/505.c
View File

@@ -60,6 +60,6 @@ void Mapper505_Init (CartInfo *info) {
MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, readPad, writeReg); MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, readPad, writeReg);
info->Power = power; info->Power = power;
info->Reset = reset; info->Reset = reset;
AddExState(&reg, 2, 0, "EXPR"); AddExState(&reg, 2 | FCEUSTATE_RLSB, 0, "EXPR");
AddExState(&pad, 1, 0, "DIPS"); AddExState(&pad, 1, 0, "DIPS");
} }

2
src/boards/506.c
View File

@@ -42,7 +42,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
sync(); MMC3_clear();
} }
static void power () { static void power () {

16
src/boards/524.c
View File

@@ -24,7 +24,7 @@
static uint8 irqEnabled; static uint8 irqEnabled;
static uint16 irqCounter; static uint16 irqCounter;
static SFORMAT BTL900218_stateRegs[] ={ static SFORMAT stateRegs[] ={
{ &irqEnabled, 1, "IRQE" }, { &irqEnabled, 1, "IRQE" },
{ &irqCounter, 2 | FCEUSTATE_RLSB, "CNTL" }, { &irqCounter, 2 | FCEUSTATE_RLSB, "CNTL" },
{ 0 } { 0 }
@@ -36,7 +36,7 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFW(BTL900218_writeIRQ) { static DECLFW (writeIRQ) {
if (A &8) { if (A &8) {
if (A &4) { if (A &4) {
irqEnabled =0; irqEnabled =0;
@@ -47,19 +47,19 @@ DECLFW(BTL900218_writeIRQ) {
} }
} }
void FP_FASTAPASS(1) BTL900218_cpuCycle(int a) { static void FP_FASTAPASS(1) cpuCycle (int a) {
while (a--) if (irqEnabled && ++irqCounter &1024) X6502_IRQBegin(FCEU_IQEXT); while (a--) if (irqEnabled && ++irqCounter &1024) X6502_IRQBegin(FCEU_IQEXT);
} }
void BTL900218_power(void) { static void power (void) {
irqEnabled =irqCounter =0; irqEnabled =irqCounter =0;
VRC24_power(); VRC24_power();
SetWriteHandler(0xF000, 0xFFFF, BTL900218_writeIRQ); SetWriteHandler(0xF000, 0xFFFF, writeIRQ);
} }
void BTL900218_Init (CartInfo *info) { void BTL900218_Init (CartInfo *info) {
VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL); VRC2_init(info, sync, 0x01, 0x02, NULL, NULL, NULL, NULL);
AddExState(BTL900218_stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
info->Power =BTL900218_power; info->Power =power;
MapIRQHook =BTL900218_cpuCycle; MapIRQHook =cpuCycle;
} }

12
src/boards/529.c
View File

@@ -36,25 +36,25 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
DECLFR(UNLT230_readEEPROM) { static DECLFR (readEEPROM) {
return eeprom_93Cx6_read()? 0x01: 0x00; return eeprom_93Cx6_read()? 0x01: 0x00;
} }
DECLFW(UNLT230_writeEEPROM) { static DECLFW (writeEEPROM) {
eeprom_93Cx6_write(A &0x04, A &0x02, A &0x01); eeprom_93Cx6_write(A &0x04, A &0x02, A &0x01);
} }
void UNLT230_power (void) { static void power (void) {
VRC24_power(); VRC24_power();
eeprom_93Cx6_init(256, 16); eeprom_93Cx6_init(256, 16);
SetReadHandler(0x5000, 0x5FFF, UNLT230_readEEPROM); SetReadHandler(0x5000, 0x5FFF, readEEPROM);
SetWriteHandler(0xF800, 0xFFFF, UNLT230_writeEEPROM); SetWriteHandler(0xF800, 0xFFFF, writeEEPROM);
} }
void UNLT230_Init (CartInfo *info) { void UNLT230_Init (CartInfo *info) {
VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, NULL); VRC4_init(info, sync, 0x04, 0x08, 1, NULL, NULL, NULL, NULL, NULL);
if (info->PRGRamSaveSize) { if (info->PRGRamSaveSize) {
info->Power =UNLT230_power; info->Power =power;
AddExState(stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
eeprom_93Cx6_storage = eeprom_data; eeprom_93Cx6_storage = eeprom_data;
info->battery = 1; info->battery = 1;

14
src/boards/530.c
View File

@@ -27,26 +27,26 @@ static void sync () {
VRC24_syncMirror(); VRC24_syncMirror();
} }
int UNLAX5705_getPRGBank(uint8 bank) { static int getPRGBank (uint8 bank) {
int result =VRC24_getPRGBank(bank); int result =VRC24_getPRGBank(bank);
return result <<2 &0x8 | result >>2 &0x2 | result &~0xA; return result <<2 &0x8 | result >>2 &0x2 | result &~0xA;
} }
int UNLAX5705_getCHRBank(uint8 bank) { static int getCHRBank (uint8 bank) {
int result =VRC24_getCHRBank(bank); int result =VRC24_getCHRBank(bank);
return result <<1 &0x40 | result >>1 &0x20 | result &~0x60; return result <<1 &0x40 | result >>1 &0x20 | result &~0x60;
} }
DECLFW(UNLAX5705_unscrambleAddress) { static DECLFW (unscrambleAddress) {
VRC24_writeReg(A &~0x1000 | A <<9 &0x1000, V); VRC24_writeReg(A &~0x1000 | A <<9 &0x1000, V);
} }
void UNLAX5705_power (void) { static void power (void) {
VRC24_power(); VRC24_power();
SetWriteHandler(0x8000, 0xFFFF, UNLAX5705_unscrambleAddress); SetWriteHandler(0x8000, 0xFFFF, unscrambleAddress);
} }
void UNLAX5705_Init (CartInfo *info) { void UNLAX5705_Init (CartInfo *info) {
VRC4_init(info, sync, 0x01, 0x02, 1, UNLAX5705_getPRGBank, UNLAX5705_getCHRBank, NULL, NULL, NULL); VRC4_init(info, sync, 0x01, 0x02, 1, getPRGBank, getCHRBank, NULL, NULL, NULL);
info->Power =UNLAX5705_power; info->Power =power;
} }

8
src/boards/542.c
View File

@@ -36,7 +36,7 @@ static void sync () {
if (reg &1) setchr1r(0x10, 0x0C00, 1); if (reg &1) setchr1r(0x10, 0x0C00, 1);
} }
DECLFW(Mapper542_writeExtra) { DECLFW (writeExtra) {
if (A &0x800) { if (A &0x800) {
reg =A >>12; reg =A >>12;
sync(); sync();
@@ -45,16 +45,16 @@ DECLFW(Mapper542_writeExtra) {
} }
void Mapper542_power (void) { void power (void) {
reg =0; reg =0;
VRC24_power(); VRC24_power();
SetReadHandler(0x6000, 0x7FFF, CartBR); SetReadHandler(0x6000, 0x7FFF, CartBR);
SetWriteHandler(0xD000, 0xEFFF, Mapper542_writeExtra); SetWriteHandler(0xD000, 0xEFFF, writeExtra);
} }
void Mapper542_Init (CartInfo *info) { void Mapper542_Init (CartInfo *info) {
VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL); VRC4_init(info, sync, 0x01, 0x02, 1, NULL, NULL, NULL, NULL, NULL);
info->Power =Mapper542_power; info->Power =power;
AddExState(stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
SetupCartCHRMapping(0x10, NTARAM, 0x200, 1); SetupCartCHRMapping(0x10, NTARAM, 0x200, 1);
} }

2
src/boards/544.c
View File

@@ -78,7 +78,7 @@ static DECLFW (externalSelect) {
} }
void power (void) { static void power (void) {
mask =0xFC; mask =0xFC;
compare =0x28; compare =0x28;
nt[0] =nt[1] =0xE0; nt[0] =nt[1] =0xE0;

2
src/boards/548.c
View File

@@ -33,7 +33,7 @@ static SFORMAT stateRegs[] ={
{ &reg, 1, "REGM" }, { &reg, 1, "REGM" },
{ &latch, 1, "LATC" }, { &latch, 1, "LATC" },
{ &counting, 1, "IRQA" }, { &counting, 1, "IRQA" },
{ &counter, 2, "IRQC" }, { &counter, 2 | FCEUSTATE_RLSB, "IRQC" },
{ 0 } { 0 }
}; };

2
src/boards/556.c
View File

@@ -31,7 +31,7 @@ static uint8 reg[4];
static uint8 index; static uint8 index;
static SFORMAT StateRegs[] = { static SFORMAT StateRegs[] = {
{ reg, 5, "REGS" }, { reg, 4, "REGS" },
{ &index, 1, "INDX" }, { &index, 1, "INDX" },
{ 0 }, { 0 },
}; };

14
src/boards/559.c
View File

@@ -38,11 +38,11 @@ static void sync () {
setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1); setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
} }
int Mapper559_getPRGBank(uint8 bank) { static int getPRGBank (uint8 bank) {
return bank ==2? prg: VRC24_getPRGBank(bank); return bank ==2? prg: VRC24_getPRGBank(bank);
} }
DECLFW(Mapper559_externalSelect) { static DECLFW (externalSelect) {
if (A &4) if (A &4)
nt[A &3] =V; nt[A &3] =V;
else else
@@ -50,20 +50,20 @@ DECLFW(Mapper559_externalSelect) {
sync(); sync();
} }
DECLFW(Mapper559_nibblizeData) { static DECLFW (nibblizeData) {
VRC24_writeReg(A, V >>(A &0x400? 4: 0)); VRC24_writeReg(A, V >>(A &0x400? 4: 0));
} }
void Mapper559_power (void) { static void power (void) {
nt[0] =nt[1] =0xE0; nt[0] =nt[1] =0xE0;
nt[2] =nt[3] =0xE1; nt[2] =nt[3] =0xE1;
prg =0xFE; prg =0xFE;
VRC24_power(); VRC24_power();
SetWriteHandler(0xB000, 0xFFFF, Mapper559_nibblizeData); SetWriteHandler(0xB000, 0xFFFF, nibblizeData);
} }
void Mapper559_Init (CartInfo *info) { void Mapper559_Init (CartInfo *info) {
VRC4_init(info, sync, 0x400, 0x800, 1, Mapper559_getPRGBank, NULL, NULL, NULL, Mapper559_externalSelect); VRC4_init(info, sync, 0x400, 0x800, 1, getPRGBank, NULL, NULL, NULL, externalSelect);
info->Power =Mapper559_power; info->Power =power;
AddExState(stateRegs, ~0, 0, 0); AddExState(stateRegs, ~0, 0, 0);
} }

2
src/boards/567.c
View File

@@ -55,7 +55,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
sync(); MMC3_clear();
} }
static void power () { static void power () {

2
src/boards/570.c
View File

@@ -42,7 +42,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
sync(); VRC24_clear();
} }
static void power () { static void power () {

2
src/boards/572.c
View File

@@ -44,7 +44,7 @@ static DECLFW(writeReg) {
static void reset () { static void reset () {
reg = 0; reg = 0;
sync(); MMC3_clear();
} }
static void power () { static void power () {

2
src/boards/578.c
View File

@@ -49,7 +49,7 @@ static void power() {
int i; int i;
reg = 0; reg = 0;
MMC3_power(); MMC3_power();
for (int i = 0x8000; i < 0xFFFF; i +=4) SetWriteHandler(i |2, i |3, writeReg); for (i = 0x8000; i < 0xFFFF; i +=4) SetWriteHandler(i |2, i |3, writeReg);
} }
void Mapper578_Init (CartInfo *info) { void Mapper578_Init (CartInfo *info) {

3
src/boards/594.c
View File

@@ -1,7 +1,7 @@
/* FCEUmm - NES/Famicom Emulator /* FCEUmm - NES/Famicom Emulator
* *
* Copyright notice for this file: * Copyright notice for this file:
* Copyright (C) 2020 * Copyright (C) 2025 NewRisingSun
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -24,7 +24,6 @@
#include "asic_mmc3.h" #include "asic_mmc3.h"
#include "fifo.h" #include "fifo.h"
#include "msm6585.h" #include "msm6585.h"
#include <stdio.h>
static uint8 reg[4]; static uint8 reg[4];
static FIFO fifo; static FIFO fifo;

2
src/boards/asic_fme7.c
View File

@@ -84,7 +84,7 @@ void FP_FASTAPASS(1) FME7_cpuCycle (int a) {
} }
} }
static void FME7_clear () { void FME7_clear () {
int i; int i;
for (i = 0; i < 16; i++) FME7_reg[i] = 0; for (i = 0; i < 16; i++) FME7_reg[i] = 0;
FME7_cbSync(); FME7_cbSync();

3
src/boards/asic_fme7.h
View File

@@ -26,9 +26,10 @@ void FME7_syncPRG (int, int);
void FME7_syncCHR (int, int); void FME7_syncCHR (int, int);
void FME7_syncMirror (); void FME7_syncMirror ();
DECLFR (FME7_readWRAM); DECLFR (FME7_readWRAM);
DECLFW(MMC3_writeWRAM); DECLFW (FME7_writeWRAM);
DECLFW (FME7_writeReg); DECLFW (FME7_writeReg);
void FP_FASTAPASS(1) FME7_cpuCycle (int); void FP_FASTAPASS(1) FME7_cpuCycle (int);
void FME7_clear ();
void FME7_activate (uint8, void (*)()); void FME7_activate (uint8, void (*)());
void FME7_addExState (); void FME7_addExState ();
void FME7_restore (int); void FME7_restore (int);

12
src/boards/asic_h3001.c
View File

@@ -33,11 +33,11 @@ static uint16 H3001_count;
static SFORMAT H3001_state[] = { static SFORMAT H3001_state[] = {
{ H3001_prg, 2, "H31P" }, { H3001_prg, 2, "H31P" },
{ H3001_chr, 8, "H31C" }, { H3001_chr, 8, "H31C" },
{&H3001_layout, 4, "H31L" }, {&H3001_layout, 1, "H31L" },
{&H3001_nt, 4, "H31M" }, {&H3001_nt, 1, "H31M" },
{&H3001_irq, 4, "H31N" }, {&H3001_irq, 1, "H31N" },
{&H3001_reload, 2, "H31R" }, {&H3001_reload, 2 | FCEUSTATE_RLSB, "H31R" },
{&H3001_count, 2, "H31T" }, {&H3001_count, 2 | FCEUSTATE_RLSB, "H31T" },
{ 0 } { 0 }
}; };
@@ -114,7 +114,7 @@ void FP_FASTAPASS(1) H3001_cpuCycle (int a) {
} }
} }
static void H3001_clear () { void H3001_clear () {
int i; int i;
for (i = 0; i < 2; i++) H3001_prg[i] = i; for (i = 0; i < 2; i++) H3001_prg[i] = i;
for (i = 0; i < 8; i++) H3001_chr[i] = i; for (i = 0; i < 8; i++) H3001_chr[i] = i;

1
src/boards/asic_h3001.h
View File

@@ -25,6 +25,7 @@ void H3001_syncPRG (int, int);
void H3001_syncCHR (int, int); void H3001_syncCHR (int, int);
void H3001_syncMirror (); void H3001_syncMirror ();
DECLFW (H3001_write); DECLFW (H3001_write);
void H3001_clear ();
void H3001_activate (uint8, void (*)()); void H3001_activate (uint8, void (*)());
void H3001_addExState (); void H3001_addExState ();
void H3001_restore (int); void H3001_restore (int);

2
src/boards/asic_mmc2and4.c
View File

@@ -70,7 +70,7 @@ DECLFW(MMC24_write) {
MMC24_cbSync(); MMC24_cbSync();
} }
static void MMC24_clear () { void MMC24_clear () {
MMC24_reg[0] = 0; MMC24_reg[1] = 0; MMC24_reg[2] = 2; MMC24_reg[3] = 0; MMC24_reg[4] = 0; MMC24_reg[5] = 0; MMC24_reg[0] = 0; MMC24_reg[1] = 0; MMC24_reg[2] = 2; MMC24_reg[3] = 0; MMC24_reg[4] = 0; MMC24_reg[5] = 0;
MMC24_latch[0] = 0; MMC24_latch[1] = 0; MMC24_latch[0] = 0; MMC24_latch[1] = 0;
MMC24_cbSync(); MMC24_cbSync();

1
src/boards/asic_mmc2and4.h
View File

@@ -27,6 +27,7 @@ void MMC4_syncPRG (int, int);
void MMC24_syncCHR (int, int); void MMC24_syncCHR (int, int);
void MMC24_syncMirror (); void MMC24_syncMirror ();
DECLFW (MMC24_write); DECLFW (MMC24_write);
void MMC24_clear ();
void MMC24_power (); void MMC24_power ();
void MMC24_restore (int); void MMC24_restore (int);
void MMC24_addExState (); void MMC24_addExState ();

2
src/boards/asic_pt8154.c
View File

@@ -56,7 +56,7 @@ DECLFW(PT8154_writeWRAM) {
PT8154_cbSync(); PT8154_cbSync();
} }
static void PT8154_clear () { void PT8154_clear () {
PT8154_reg = 0; PT8154_reg = 0;
PT8154_cbSync(); PT8154_cbSync();
} }

1
src/boards/asic_pt8154.h
View File

@@ -26,6 +26,7 @@ void PT8154_syncCHR (int, int);
void PT8154_syncMirror (); void PT8154_syncMirror ();
DECLFW (PT8154_writeExtra); DECLFW (PT8154_writeExtra);
DECLFW (PT8154_writeWRAM); DECLFW (PT8154_writeWRAM);
void PT8154_clear ();
void PT8154_activate (uint8, void (*)()); void PT8154_activate (uint8, void (*)());
void PT8154_addExState (); void PT8154_addExState ();
void PT8154_restore (int); void PT8154_restore (int);

2
src/boards/asic_qj.c
View File

@@ -47,7 +47,7 @@ DECLFW(QJ_writeWRAM) {
QJ_cbSync(); QJ_cbSync();
} }
static void QJ_clear () { void QJ_clear () {
QJ_reg = 0; QJ_reg = 0;
QJ_cbSync(); QJ_cbSync();
} }

1
src/boards/asic_qj.h
View File

@@ -26,6 +26,7 @@ void QJ_syncPRG (int, int);
void QJ_syncCHR (int, int); void QJ_syncCHR (int, int);
void QJ_syncMirror (); void QJ_syncMirror ();
DECLFW (QJ_write); DECLFW (QJ_write);
void QJ_clear ();
void QJ_activate (uint8, void (*)()); void QJ_activate (uint8, void (*)());
void QJ_addExState (); void QJ_addExState ();
void QJ_restore (int); void QJ_restore (int);

8
src/boards/asic_tc3294.c
View File

@@ -52,14 +52,14 @@ void TC3294_syncMirror () {
MMC3_syncMirror(); MMC3_syncMirror();
} }
DECLFW(TC3294_write) { DECLFW(TC3294_writeReg) {
if (~TC3294_reg[3] &0x40) { if (~TC3294_reg[3] &0x40) {
TC3294_reg[TC3294_index++ &3] = V; TC3294_reg[TC3294_index++ &3] = V;
TC3294_cbSync(); TC3294_cbSync();
} }
} }
static void TC3294_clear () { void TC3294_clear () {
TC3294_reg[0] = 0x00; TC3294_reg[1] = 0x00; TC3294_reg[2] = 0x0F; TC3294_reg[3] = 0x00; TC3294_reg[0] = 0x00; TC3294_reg[1] = 0x00; TC3294_reg[2] = 0x0F; TC3294_reg[3] = 0x00;
TC3294_index = 0; TC3294_index = 0;
TC3294_cbSync(); TC3294_cbSync();
@@ -73,7 +73,7 @@ static void TC3294_configure (void (*sync)()) {
} }
void TC3294_activate (uint8 clear, void (*sync)()) { void TC3294_activate (uint8 clear, void (*sync)()) {
MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_write); MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_writeReg);
TC3294_configure(sync); TC3294_configure(sync);
TC3294_setHandlers(); TC3294_setHandlers();
if (clear) if (clear)
@@ -97,7 +97,7 @@ void TC3294_power () {
} }
void TC3294_init (CartInfo *info, void (*sync)()) { void TC3294_init (CartInfo *info, void (*sync)()) {
MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_write); MMC3_init(info, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, TC3294_writeReg);
TC3294_addExState(); TC3294_addExState();
TC3294_configure(sync); TC3294_configure(sync);
info->Power = TC3294_power; info->Power = TC3294_power;

3
src/boards/asic_tc3294.h
View File

@@ -26,7 +26,8 @@ void TC3294_syncWRAM (int);
void TC3294_syncPRG (int, int); void TC3294_syncPRG (int, int);
void TC3294_syncCHR (int, int); void TC3294_syncCHR (int, int);
void TC3294_syncMirror (); void TC3294_syncMirror ();
DECLFW (TC3294_write); DECLFW (TC3294_writeReg);
void TC3294_clear ();
void TC3294_activate (uint8, void (*)()); void TC3294_activate (uint8, void (*)());
void TC3294_addExState (); void TC3294_addExState ();
void TC3294_restore (int); void TC3294_restore (int);

6
src/boards/asic_vrc1.c
View File

@@ -45,19 +45,19 @@ void VRC1_syncMirror () {
setmirror(VRC1_reg[1] &0x01? MI_H: MI_V); setmirror(VRC1_reg[1] &0x01? MI_H: MI_V);
} }
DECLFW(VRC1_write) { DECLFW (VRC1_writeReg) {
VRC1_reg[A >>12 &7] = V; VRC1_reg[A >>12 &7] = V;
VRC1_cbSync(); VRC1_cbSync();
} }
static void VRC1_clear () { void VRC1_clear () {
VRC1_reg[0] = 0x00; VRC1_reg[1] = 0; VRC1_reg[2] = 2; VRC1_reg[3] = 0;VRC1_reg[4] = 0x00; VRC1_reg[5] = 0; VRC1_reg[6] = 2; VRC1_reg[7] = 0; VRC1_reg[0] = 0x00; VRC1_reg[1] = 0; VRC1_reg[2] = 2; VRC1_reg[3] = 0;VRC1_reg[4] = 0x00; VRC1_reg[5] = 0; VRC1_reg[6] = 2; VRC1_reg[7] = 0;
VRC1_cbSync(); VRC1_cbSync();
} }
static void VRC1_setHandlers () { static void VRC1_setHandlers () {
SetReadHandler (0x8000, 0xFFFF, CartBR); SetReadHandler (0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x8000, 0xFFFF, VRC1_write); SetWriteHandler(0x8000, 0xFFFF, VRC1_writeReg);
} }
static void VRC1_configure (void (*sync)()) { static void VRC1_configure (void (*sync)()) {

3
src/boards/asic_vrc1.h
View File

@@ -24,7 +24,8 @@
void VRC1_syncPRG (int, int); void VRC1_syncPRG (int, int);
void VRC1_syncCHR (int, int); void VRC1_syncCHR (int, int);
void VRC1_syncMirror (); void VRC1_syncMirror ();
DECLFW (VRC1_write); DECLFW (VRC1_writeReg);
void VRC1_clear ();
void VRC1_activate (uint8, void (*)()); void VRC1_activate (uint8, void (*)());
void VRC1_addExState (); void VRC1_addExState ();
void VRC1_restore (int); void VRC1_restore (int);

2
src/boards/asic_vrc2and4.c
View File

@@ -194,7 +194,7 @@ void FP_FASTAPASS(1) VRC4_cpuCycle (int a) {
} }
} }
static void VRC24_clear() { void VRC24_clear () {
VRC24_prg[0] = 0; VRC24_prg[1] = 0; VRC24_prg[0] = 0; VRC24_prg[1] = 0;
VRC24_chr[0] = 0; VRC24_chr[1] = 1; VRC24_chr[2] = 2; VRC24_chr[3] = 3; VRC24_chr[4] = 4; VRC24_chr[5] = 5; VRC24_chr[6] = 6; VRC24_chr[7] = 7; VRC24_chr[0] = 0; VRC24_chr[1] = 1; VRC24_chr[2] = 2; VRC24_chr[3] = 3; VRC24_chr[4] = 4; VRC24_chr[5] = 5; VRC24_chr[6] = 6; VRC24_chr[7] = 7;
VRC24_mirroring = VRC2_pins = VRC4_latch = VRC4_mode = VRC4_count = VRC4_cycles = 0; VRC24_mirroring = VRC2_pins = VRC4_latch = VRC4_mode = VRC4_count = VRC4_cycles = 0;

1
src/boards/asic_vrc2and4.h
View File

@@ -38,6 +38,7 @@ DECLFW(VRC24_writeReg);
void FP_FASTAPASS(1) VRC4_cpuCycle(int); void FP_FASTAPASS(1) VRC4_cpuCycle(int);
void VRC24_reconfigure (int, int); void VRC24_reconfigure (int, int);
void VRC24_clear ();
void VRC2_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*))); void VRC2_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)));
void VRC4_activate (uint8, void (*)(), int, int, uint8, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)), DECLFW((*))); void VRC4_activate (uint8, void (*)(), int, int, uint8, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)), DECLFW((*)));
void VRC2_addExState (); void VRC2_addExState ();

2
src/boards/asic_vrc3.c
View File

@@ -81,7 +81,7 @@ void FP_FASTAPASS(1) VRC3_cpuCycle (int a) {
} }
} }
static void VRC3_clear () { void VRC3_clear () {
VRC3_prg = VRC3_irq = VRC3_count = VRC3_reload = 0; VRC3_prg = VRC3_irq = VRC3_count = VRC3_reload = 0;
X6502_IRQEnd(FCEU_IQEXT); X6502_IRQEnd(FCEU_IQEXT);
VRC3_cbSync(); VRC3_cbSync();

1
src/boards/asic_vrc3.h
View File

@@ -25,6 +25,7 @@ void VRC3_syncWRAM (int);
void VRC3_syncPRG (int, int); void VRC3_syncPRG (int, int);
void VRC3_syncCHR (int, int); void VRC3_syncCHR (int, int);
DECLFW (VRC3_write); DECLFW (VRC3_write);
void VRC3_clear ();
void VRC3_activate (uint8, void (*)()); void VRC3_activate (uint8, void (*)());
void VRC3_addExState (); void VRC3_addExState ();
void VRC3_restore (int); void VRC3_restore (int);

2
src/boards/asic_vrc6.c
View File

@@ -151,7 +151,7 @@ void FP_FASTAPASS(1) VRC6_cpuCycle (int a) {
} }
} }
static void VRC6_clear () { void VRC6_clear () {
VRC6_prg[0] = 0; VRC6_prg[1] = 0xFE; VRC6_prg[0] = 0; VRC6_prg[1] = 0xFE;
VRC6_chr[0] = 0; VRC6_chr[1] = 1; VRC6_chr[2] = 2; VRC6_chr[3] = 3; VRC6_chr[4] = 4; VRC6_chr[5] = 5; VRC6_chr[6] = 6; VRC6_chr[7] = 7; VRC6_chr[0] = 0; VRC6_chr[1] = 1; VRC6_chr[2] = 2; VRC6_chr[3] = 3; VRC6_chr[4] = 4; VRC6_chr[5] = 5; VRC6_chr[6] = 6; VRC6_chr[7] = 7;
VRC6_misc = VRC6_latch = VRC6_mode = VRC6_count = VRC6_cycles = 0; VRC6_misc = VRC6_latch = VRC6_mode = VRC6_count = VRC6_cycles = 0;

1
src/boards/asic_vrc6.h
View File

@@ -31,6 +31,7 @@ DECLFR(VRC6_readWRAM);
DECLFW(MMC3_writeWRAM); DECLFW(MMC3_writeWRAM);
DECLFW(VRC6_writeReg); DECLFW(VRC6_writeReg);
void FP_FASTAPASS(1) VRC6_cpuCycle (int); void FP_FASTAPASS(1) VRC6_cpuCycle (int);
void VRC6_clear ();
void VRC6_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*))); void VRC6_activate (uint8, void (*)(), int, int, int (*)(uint8), int (*)(uint8), DECLFR((*)), DECLFW((*)));
void VRC6_addExState (); void VRC6_addExState ();
void VRC6_restore (int); void VRC6_restore (int);

2
src/boards/asic_vrc7.c
View File

@@ -128,7 +128,7 @@ void FP_FASTAPASS(1) VRC7_cpuCycle (int a) {
} }
} }
static void VRC7_clear () { void VRC7_clear () {
VRC7_prg[0] = 0; VRC7_prg[1] = 1; VRC7_prg[2] = 0xFE; VRC7_prg[0] = 0; VRC7_prg[1] = 1; VRC7_prg[2] = 0xFE;
VRC7_chr[0] = 0; VRC7_chr[1] = 1; VRC7_chr[2] = 2; VRC7_chr[3] = 3; VRC7_chr[4] = 4; VRC7_chr[5] = 5; VRC7_chr[6] = 6; VRC7_chr[7] = 7; VRC7_chr[0] = 0; VRC7_chr[1] = 1; VRC7_chr[2] = 2; VRC7_chr[3] = 3; VRC7_chr[4] = 4; VRC7_chr[5] = 5; VRC7_chr[6] = 6; VRC7_chr[7] = 7;
VRC7_misc = VRC7_latch = VRC7_mode = VRC7_count = VRC7_cycles = 0; VRC7_misc = VRC7_latch = VRC7_mode = VRC7_count = VRC7_cycles = 0;

1
src/boards/asic_vrc7.h
View File

@@ -29,6 +29,7 @@ DECLFR(VRC7_readWRAM);
DECLFW(MMC3_writeWRAM); DECLFW(MMC3_writeWRAM);
DECLFW(VRC7_writeReg); DECLFW(VRC7_writeReg);
void FP_FASTAPASS(1) VRC7_cpuCycle (int); void FP_FASTAPASS(1) VRC7_cpuCycle (int);
void VRC7_clear ();
void VRC7_activate (uint8, void (*)(), int); void VRC7_activate (uint8, void (*)(), int);
void VRC7_addExState (); void VRC7_addExState ();
void VRC7_restore (int); void VRC7_restore (int);

2
src/boards/bmck3006.c
View File

@@ -26,7 +26,7 @@
#include "mapinc.h" #include "mapinc.h"
#include "mmc3.h" #include "mmc3.h"
static uint8 submapper; // 0: K-3006, 1: unmarked, 2: TL 8058, 3: K-3091/GN-16 static uint8 submapper; /* 0: K-3006, 1: unmarked, 2: TL 8058, 3: K-3091/GN-16 */
static DECLFR (readPad) { static DECLFR (readPad) {
return CartBR(A &~3 | EXPREGS[2] &3); return CartBR(A &~3 | EXPREGS[2] &3);

8
src/boards/cartram.c
View File

@@ -43,9 +43,9 @@ void CartRAM_init (CartInfo *info, uint8 defaultWRAMSizeKiB, uint8 defaultCHRRAM
WRAMData = (uint8*)FCEU_gmalloc(WRAMSize); WRAMData = (uint8*)FCEU_gmalloc(WRAMSize);
SetupCartPRGMapping(0x10, WRAMData, WRAMSize, 1); SetupCartPRGMapping(0x10, WRAMData, WRAMSize, 1);
AddExState(WRAMData, WRAMSize, 0, "WRAM"); AddExState(WRAMData, WRAMSize, 0, "WRAM");
if (info->battery) { if (info->battery && (info->PRGRamSaveSize || !info->iNES2)) {
info->SaveGame[0] = WRAMData; info->SaveGame[0] = WRAMData;
info->SaveGameLen[0] =WRAMSize; info->SaveGameLen[0] = info->iNES2? info->PRGRamSaveSize: WRAMSize;
} }
} }
CHRRAMSize = info->iNES2? (info->CHRRamSize +info->CHRRamSaveSize): (defaultCHRRAMSizeKiB *1024); CHRRAMSize = info->iNES2? (info->CHRRamSize +info->CHRRamSaveSize): (defaultCHRRAMSizeKiB *1024);
@@ -54,9 +54,9 @@ void CartRAM_init (CartInfo *info, uint8 defaultWRAMSizeKiB, uint8 defaultCHRRAM
CHRRAMData = (uint8*)FCEU_gmalloc(CHRRAMSize); CHRRAMData = (uint8*)FCEU_gmalloc(CHRRAMSize);
SetupCartCHRMapping(0x10, CHRRAMData, CHRRAMSize, 1); SetupCartCHRMapping(0x10, CHRRAMData, CHRRAMSize, 1);
AddExState(CHRRAMData, CHRRAMSize, 0, "CRAM"); AddExState(CHRRAMData, CHRRAMSize, 0, "CRAM");
if (info->battery) { if (info->battery && (info->CHRRamSaveSize || !info->iNES2)) {
info->SaveGame[info->SaveGameLen[0]? 1: 0] = CHRRAMData; info->SaveGame[info->SaveGameLen[0]? 1: 0] = CHRRAMData;
info->SaveGameLen[info->SaveGameLen[0]? 1: 0] =CHRRAMSize; info->SaveGameLen[info->SaveGameLen[0]? 1: 0] = info->iNES2? info->CHRRamSaveSize: CHRRAMSize;
} }
} }
if (WRAMSize || CHRRAMSize) info->Close = CartRAM_close; if (WRAMSize || CHRRAMSize) info->Close = CartRAM_close;

4
src/boards/fifo.c
View File

@@ -31,8 +31,8 @@ void FIFO_init (FIFO *fifo, size_t newCapacity) {
fifo->capacity = newCapacity; fifo->capacity = newCapacity;
fifo->data = (uint8*)FCEU_gmalloc(newCapacity); fifo->data = (uint8*)FCEU_gmalloc(newCapacity);
AddExState(fifo->data, fifo->capacity, 0, "FIFD"); AddExState(fifo->data, fifo->capacity, 0, "FIFD");
AddExState(&fifo->front, 2, 0, "FIFF"); AddExState(&fifo->front, 2 | FCEUSTATE_RLSB, 0, "FIFF");
AddExState(&fifo->back, 2, 0, "FIFB"); AddExState(&fifo->back, 2 | FCEUSTATE_RLSB, 0, "FIFB");
} }
void FIFO_close (FIFO *fifo) { void FIFO_close (FIFO *fifo) {

10
src/boards/msm6585.c
View File

@@ -59,10 +59,10 @@ void MSM6585_init (MSM6585* chip, int32 newHostClock, int (*newGetInput)(void))
chip->getInput = newGetInput; chip->getInput = newGetInput;
AddExState(&chip->whichNibble, 1, 0, "MSMW"); AddExState(&chip->whichNibble, 1, 0, "MSMW");
AddExState(&chip->input, 1, 0, "MSMI"); AddExState(&chip->input, 1, 0, "MSMI");
AddExState(&chip->signal, 2, 0, "MSMO"); AddExState(&chip->signal, 2 | FCEUSTATE_RLSB, 0, "MSMO");
AddExState(&chip->count, 4, 0, "MSMC"); AddExState(&chip->count, 4 | FCEUSTATE_RLSB, 0, "MSMC");
AddExState(&chip->rate, 4, 0, "MSMR"); AddExState(&chip->rate, 4 | FCEUSTATE_RLSB, 0, "MSMR");
AddExState(&chip->step, 2, 0, "MSMS"); AddExState(&chip->step, 2 | FCEUSTATE_RLSB, 0, "MSMS");
} }
void MSM6585_reset (MSM6585* chip) { void MSM6585_reset (MSM6585* chip) {
@@ -78,8 +78,8 @@ void MSM6585_setRate (MSM6585* chip, uint8 rateByte) {
void MSM6585_run (MSM6585* chip) { void MSM6585_run (MSM6585* chip) {
chip->count += chip->rate; chip->count += chip->rate;
while (chip->count >= chip->hostClock) { while (chip->count >= chip->hostClock) {
chip->count -= chip->hostClock;
uint8_t nibble; uint8_t nibble;
chip->count -= chip->hostClock;
if (chip->whichNibble) if (chip->whichNibble)
nibble = chip->input &0x0F; nibble = chip->input &0x0F;
else { else {