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Exponential notation of NES 2.0 ROM sizes; mappers (#480)

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* Support 2 MIB mapper 314 (Y2K 76-in-1)

* Mapper 57: Forgot one Sync() statement

* Mapper 83: Correction for 256 KiB PRG+512 KiB CHR games

* Mapper 114: Use NES 2.0 submapper field if available to differentiate between scrambling patterns

* NES 2.0: Support exponential notation of PRG/CHR sizes, thus adding support for 4 KiB and 8 KiB ROM files.

* Add mapper 553.

* Correct the database regarding the Nanjing game Pegasus Senya

* Add submapper 5 (HST-162) to mapper 176

* Add mapper 436

* Mapper 176.5 has a CNROM latch as well, though it works a bit differently than submapper 1's

* Added mapper 429

* Added mapper 380 submapper 1

* Added mapper 437

* Added mapper 456

* Forgot to include math.h for pow

* Added mapper 434

* Added mapper 452

* Added mapper 438

* Added mappers 391 and 444, corrected the mixup with BS-110 and NC7000M

* Added mapper 443. Added menu-switching funcionality to mapper 444

Co-authored-by: NewRisingSun <8vytz1+dhp372pv94ebg@sharklasers.com>
This commit is contained in:
NRS-NewRisingSun
2022-01-06 08:22:18 +01:00
committed by GitHub
parent c291ceeb13
commit d72c64e5d9
24 changed files with 767 additions and 457 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/boards/fk23c.c
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@@ -29,6 +29,7 @@
2 - 外星 FS005/FS006
3 - JX9003B
4 - GameStar Smart Genius Deluxe
5 - HST-162
Verified on real hardware:
"Legend of Kage" sets CNROM latch 1 and switches between CHR bank 0 and 1 using 5FF2, causing the wrong bank (1 instead of 0) during gameplay.
@@ -87,7 +88,7 @@ static SFORMAT StateRegs[] = {
#define PRG_MODE ( fk23_regs[0] & 0x07)
#define MMC3_EXTENDED !!( fk23_regs[3] & 0x02) /* Extended MMC3 mode, adding extra registers for switching the normally-fixed PRG banks C and E and for eight independent 1 KiB CHR banks. Only available on FK- and FS005 PCBs. */
#define CHR_8K_MODE !!( fk23_regs[0] & 0x40) /* MMC3 CHR registers are ignored, apply outer bank only, and CNROM latch if it exists */
#define CHR_CNROM_MODE (~fk23_regs[0] & 0x20 && subType == 1) /* Only subtype 1 has a CNROM latch, which can be disabled */
#define CHR_CNROM_MODE (~fk23_regs[0] & 0x20 && (subType == 1 || subType == 5)) /* Only subtypes 1 and 5 have a CNROM latch, which can be disabled */
#define CHR_OUTER_BANK_SIZE !!( fk23_regs[0] & 0x10) /* Switch between 256 and 128 KiB CHR, or 32 and 16 KiB CHR in CNROM mode */
#define CHR_MIXED !!(WRAM_EXTENDED && mmc3_wram &0x04) /* First 8 KiB of CHR address space are RAM, then ROM */
@@ -119,7 +120,8 @@ static void SyncCHR(void)
if (CHR_8K_MODE)
{
uint32 mask = (CHR_CNROM_MODE? (CHR_OUTER_BANK_SIZE? 0x01: 0x03): 0x00);
uint32 bank = ((outer & ~mask) | (latch & mask)) << 3; /* Address bits are never OR'd; they either come from the outer bank or from the CNROM latch. */
/* In Submapper 1, address bits come either from outer bank or from latch. In Submapper 5, they are OR'd. Both verified on original hardware. */
uint32 bank = ((subType ==5? outer: (outer & ~mask)) | (latch & mask)) << 3;
cwrap(0x0000, bank + 0);
cwrap(0x0400, bank + 1);
@@ -183,6 +185,9 @@ static void SyncPRG(void)
case 4: /* GameStar Smart Genius Deluxe */
prg_base |= fk23_regs[2] & 0x80;
break;
case 5: /* HST-162 */
prg_base = prg_base &0x1F | fk23_regs[5] <<5;
break;
}
switch (PRG_MODE)
@@ -262,6 +267,11 @@ static void Sync(void)
SyncMIR();
}
static DECLFW(Write4800) /* Only used by submapper 5 (HST-162) */
{
fk23_regs[5] = V; /* Register 4800 is a separate register, but we use one of the ASIC registers that is otherwise unused in submapper 5 */
SyncPRG();
}
static DECLFW(Write5000)
{
if (after_power && A > 0x5010 && A != 0x5FF3) /* Ignore writes from $5000-$500F, in particular to $5008, but not $5FF3 */
@@ -381,7 +391,7 @@ static void Reset(void)
FCEU_printf("BMCFK23C dipswitch set to $%04x\n",0x5000|0x10 << dipswitch);
}
fk23_regs[0] = fk23_regs[1] = fk23_regs[2] = fk23_regs[3] = 0;
fk23_regs[0] = fk23_regs[1] = fk23_regs[2] = fk23_regs[3] = fk23_regs[4] = fk23_regs[5] = fk23_regs[6] = fk23_regs[7] = 0;
mmc3_regs[0] = 0;
mmc3_regs[1] = 2;
mmc3_regs[2] = 4;
@@ -402,7 +412,7 @@ static void Reset(void)
static void Power(void)
{
fk23_regs[0] = fk23_regs[1] = fk23_regs[2] = fk23_regs[3] = 0;
fk23_regs[0] = fk23_regs[1] = fk23_regs[2] = fk23_regs[3] = fk23_regs[4] = fk23_regs[5] = fk23_regs[6] = fk23_regs[7] = 0;
mmc3_regs[0] = 0;
mmc3_regs[1] = 2;
mmc3_regs[2] = 4;
@@ -424,6 +434,9 @@ static void Power(void)
SetWriteHandler(0x5000, 0x5FFF, Write5000);
SetWriteHandler(0x8000, 0xFFFF, Write8000);
if (subType == 5)
SetWriteHandler(0x4800, 0x4FFF, Write4800);
if (WRAMSIZE)
{
SetReadHandler(0x6000, 0x7FFF, CartBR);