Mapper 556: use the modularized ASIC cores.

src/boards/556.c

@@ -19,312 +19,84 @@
  */
 
 /* NES 2.0 Mapper 556
- * Used for the for the 超强小新2+瑪莉家族 7-in-1 (JY-215) multicart.
+ * Used for the for the 餓狼傳說 激鬥篇 HiK 7-in-1 (JY-215) multicart.
  */
 
 #include "mapinc.h"
+#include "asic_mmc3.h"
+#include "asic_vrc2and4.h"
+#include "wram.h"
 
-static uint8 reg[5];
+static uint8 reg[4];
-static uint8 mmc3Reg[8];
+static uint8 index;
-static uint8 mmc3Cmd;
-static uint8 mmc3Mirr;
-static uint8 mmc3Wram;
-static uint8 mmc3IRQLatch;
-static uint8 mmc3IRQCount;
-static uint8 mmc3IRQa;
-static uint8 mmc3IRQReload;
-static uint8 vrc4Prg[2];
-static uint8 vrc4Mirr;
-static uint8 vrc4Misc;
-static uint16 vrc4Chr[8];
-static uint8 vrc4IRQLatch;
-static uint8 vrc4IRQa;
-static uint8 vrc4IRQCount;
-static int16 vrc4IRQCycles;
-static uint8 *WRAM = NULL;
-static uint32 WRAMSIZE = 0;
 
 static SFORMAT StateRegs[] = {
 	{ reg,            5, "REGS" },
-	{ mmc3Reg,        8, "MMC3" },
+	{ &index,         1, "INDX" },
-	{ &mmc3Cmd,       1, "M3IX" },
-	{ &mmc3Mirr,      1, "M3MI" },
-	{ &mmc3Wram,      1, "M3WR" },
-	{ &mmc3IRQLatch,  1, "M3RL" },
-	{ &mmc3IRQCount,  1, "M3CN" },
-	{ &mmc3IRQa,      1, "M3IQ" },
-	{ &mmc3IRQReload, 1, "M3IR" },
-	{ vrc4Prg,        2, "V4PR" },
-	{ &vrc4Mirr,      1, "V4MI" },
-	{ &vrc4Misc,      1, "V4MS" },
-	{ vrc4Chr,       16, "V4CH" },
-	{ &vrc4IRQLatch,  1, "VILA" },
-	{ &vrc4IRQa,      1, "VIMO" },
-	{ &vrc4IRQCount,  1, "VICO" },
-	{ &vrc4IRQCycles, 2, "VICY" },
 	{ 0 },
 };
 
-static void Sync(void) {
+static void sync (void) {
-	uint32 prgmask = ~reg[3] & 0x3F;
+	int prgAND = ~reg[3] &0x3F;
-	uint32 prgbase = ((reg[3] & 0x40) << 2) | reg[1];
+	int chrAND = 0xFF >>(~reg[2] &0xF);
-	uint32 chrmask = 0xFF >> (~reg[2] & 0x0F);
+	int prgOR  = (reg[1] | reg[3] <<2 &0x100) &~prgAND;
-	uint32 chrbase = ((reg[3] & 0x40) << 6) | ((reg[2] & 0xF0) << 4) | reg[0];
+	int chrOR  = (reg[0] | reg[2] <<4 &0x0F00 | reg[3] <<6 &0x1000) &~chrAND;
-	uint32 cbase = 0; /* prg/chr bank flip flag */
+	if (reg[2] &0x80) {
-
+		VRC24_syncWRAM(0);
-	if (~reg[2] & 0x80) {
+		VRC24_syncPRG(prgAND, prgOR);
-		/* MMC3 */
+		VRC24_syncCHR(chrAND, chrOR);
-		cbase = (mmc3Cmd << 8) & 0x4000;
+		VRC24_syncMirror();
-		setprg8(0x8000 ^ cbase, (prgbase & ~prgmask) | (mmc3Reg[6] & prgmask));
-		setprg8(0xA000,         (prgbase & ~prgmask) | (mmc3Reg[7] & prgmask));
-		setprg8(0xC000 ^ cbase, (prgbase & ~prgmask) | (0xFE & prgmask));
-		setprg8(0xE000,         (prgbase & ~prgmask) | (0xFF & prgmask));
-
-		cbase = (mmc3Cmd << 5) & 0x1000;
-		setchr1(0x0000 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[0] & 0xFE) & chrmask));
-		setchr1(0x0400 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[0] | 0x01) & chrmask));
-		setchr1(0x0800 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[1] & 0xFE) & chrmask));
-		setchr1(0x0C00 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[1] | 0x01) & chrmask));
-		setchr1(0x1000 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[2] & chrmask));
-		setchr1(0x1400 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[3] & chrmask));
-		setchr1(0x1800 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[4] & chrmask));
-		setchr1(0x1C00 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[5] & chrmask));
-
-		setmirror((mmc3Mirr & 0x01) ^ 1);
 	} else {
-		/* VRC4 mode */
+		MMC3_syncWRAM(0);
-		cbase = (vrc4Misc << 13) & 0x4000;
+		MMC3_syncPRG(prgAND, prgOR);
-		setprg8(0x8000 ^ cbase, (prgbase & ~prgmask) | (vrc4Prg[0] & prgmask));
+		MMC3_syncCHR(chrAND, chrOR);
-		setprg8(0xA000,         (prgbase & ~prgmask) | (vrc4Prg[1] & prgmask));
+		MMC3_syncMirror();
-		setprg8(0xC000 ^ cbase, (prgbase & ~prgmask) | (0xFE & prgmask));
-		setprg8(0xE000,         (prgbase & ~prgmask) | (0xFF & prgmask));
-
-		setchr1(0x0000,         (chrbase & ~chrmask) | (vrc4Chr[0] & chrmask));
-		setchr1(0x0400,         (chrbase & ~chrmask) | (vrc4Chr[1] & chrmask));
-		setchr1(0x0800,         (chrbase & ~chrmask) | (vrc4Chr[2] & chrmask));
-		setchr1(0x0C00,         (chrbase & ~chrmask) | (vrc4Chr[3] & chrmask));
-		setchr1(0x1000,         (chrbase & ~chrmask) | (vrc4Chr[4] & chrmask));
-		setchr1(0x1400,         (chrbase & ~chrmask) | (vrc4Chr[5] & chrmask));
-		setchr1(0x1800,         (chrbase & ~chrmask) | (vrc4Chr[6] & chrmask));
-		setchr1(0x1C00,         (chrbase & ~chrmask) | (vrc4Chr[7] & chrmask));
-
-		switch (vrc4Mirr & 0x03) {
-		case 0: setmirror(MI_V); break;
-		case 1: setmirror(MI_H); break;
-		case 2: setmirror(MI_0); break;
-		case 3: setmirror(MI_1); break;
-		}
 	}
 }
 
-static DECLFW(writeMMC3) {
+static void applyMode (uint8 clear) {
-	switch (A & 0xE001) {
+	if (reg[2] &0x80)
-	case 0x8000:
+		VRC4_activate(clear, sync, 0x05, 0x0A, 1, NULL, NULL, NULL, NULL, NULL);
-		mmc3Cmd = V;
+	else
-		Sync();
+		MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, NULL);
-		break;
+}
-	case 0x8001:
+
-		mmc3Reg[mmc3Cmd & 7] = V;
+static DECLFW(writeReg) {
-		Sync();
+	if (~reg[3] &0x80) {
-		break;
+		reg[index++ &3] = V;
-	case 0xA000:
+		if (index == 3)
-		mmc3Mirr = V;
+			applyMode(1);
-		Sync();
+		else
-		break;
+			sync();
-	case 0xA001:
-		mmc3Wram = V;
-		Sync();
-		break;
-	case 0xC000:
-		mmc3IRQLatch = V;
-		break;
-	case 0xC001:
-		mmc3IRQReload = 1;
-		break;
-	case 0xE000:
-		mmc3IRQa = 0;
-		X6502_IRQEnd(FCEU_IQEXT);
-		break;
-	case 0xE001:
-		mmc3IRQa = 1;
-		break;
 	}
 }
 
-static DECLFW(writeVRC4) {
+static void reset (void) {
-	uint8 index;
+	reg[0] = reg[1] = reg[3] = 0;
-	A = (A & 0xF000) | ((A >> 2) & 3) | (A & 3);
-	switch (A & 0xF000) {
-	case 0x8000:
-	case 0xA000:
-		vrc4Prg[(A >> 13) & 1] = V;
-		Sync();
-		break;
-	case 0x9000:
-		if (~A & 2) {
-			vrc4Mirr = V;
-		} else if (~A & 1) {
-			vrc4Misc = V;
-		}
-		Sync();
-		break;
-	case 0xF000:
-		switch (A & 3) {
-		case 0:
-			vrc4IRQLatch = (vrc4IRQLatch & 0xF0) | (V & 0x0F);
-			break;
-		case 1:
-			vrc4IRQLatch = (vrc4IRQLatch & 0x0F) | (V << 4);
-			break;
-		case 2:
-			vrc4IRQa = V;
-			if (vrc4IRQa & 0x02) {
-				vrc4IRQCount = vrc4IRQLatch;
-				vrc4IRQCycles = 341;
-			}
-			X6502_IRQEnd(FCEU_IQEXT);
-			break;
-		case 3:
-			vrc4IRQa = (vrc4IRQa & ~0x02) | ((vrc4IRQa << 1) & 0x02);
-			X6502_IRQEnd(FCEU_IQEXT);
-			break;
-		}
-		break;
-	default:
-		index = ((A - 0xB000) >> 11) | ((A >> 1) & 1);
-		if (A & 1) {
-			vrc4Chr[index] = (vrc4Chr[index] & 0x0F) | (V << 4);
-		} else {
-			vrc4Chr[index] = (vrc4Chr[index] & ~0x0F) | (V & 0x0F);
-		}
-		Sync();
-		break;
-	}
-}
-
-static DECLFW(M556WriteReg) {
-	if (~reg[3] & 0x80) {
-		reg[reg[4] & 3] = V;
-		reg[4]++;
-		Sync();
-	}
-}
-
-static DECLFW(M556Write) {
-	if (~reg[2] & 0x80) {
-		writeMMC3(A, V);
-	} else {
-		writeVRC4(A, V);
-	}
-}
-
-static void FP_FASTAPASS(1) M556CPUHook(int a) {
-	int count = a;
-
-	if (~reg[2] & 0x80) {
-		return;
-	}
-
-	/* VRC4 IRQ mode */
-	while (count--) {
-		if ((vrc4IRQa & 0x02) && ((vrc4IRQa & 0x04) || ((vrc4IRQCycles -= 3) <= 0))) {
-			if (~vrc4IRQa & 0x04) {
-				vrc4IRQCycles += 341;
-			}
-			if (!++vrc4IRQCount) {
-				vrc4IRQCount = vrc4IRQLatch;
-				X6502_IRQBegin(FCEU_IQEXT);
-			}
-		}
-	}
-}
-
-static void M556HBHook(void) {
-	int count = mmc3IRQCount;
-
-	if (reg[2] & 0x80) {
-		return;
-	}
-
-	/* MMC3 IRQ mode */
-	if (!count || mmc3IRQReload) {
-		mmc3IRQCount = mmc3IRQLatch;
-	} else {
-		mmc3IRQCount--;
-	}
-	if (count && !mmc3IRQCount && mmc3IRQa) {
-		X6502_IRQBegin(FCEU_IQEXT);
-	}
-	mmc3IRQReload = 0;
-}
-
-static void M556Reset(void) {
-	int i;
-	for (i = 0; i < 5; i++) {
-		reg[i] = 0;
-    }
 	reg[2] = 0x0F;
-	Sync();
+	index = 0;
+	applyMode(1);
 }
 
-static void M556Power(void) {
+static void power (void) {
-	int i;
+	reg[0] = reg[1] = reg[3] = 0;
-	for (i = 0; i < 5; i++) {
-		reg[i] = 0;
-    }
-	for (i = 0; i < 8; i++) {
-		mmc3Reg[i] = 0;
-    }
-	for (i = 0; i < 2; i++) {
-		vrc4Prg[i] = 0;
-    }
-	for (i = 0; i < 8; i++) {
-		vrc4Chr[i] = 0;
-    }
-	mmc3Cmd = mmc3Mirr = mmc3Wram = mmc3IRQLatch = mmc3IRQCount = mmc3IRQa = mmc3IRQReload = 0;
-	vrc4Mirr = vrc4Misc = vrc4IRQLatch = vrc4IRQa = vrc4IRQCount = vrc4IRQCycles = 0;
 	reg[2] = 0x0F;
-	Sync();
+	index = 0;
-
+	SetReadHandler(0x6000, 0xFFFF, CartBR);
-	SetReadHandler(0x8000, 0xFFFF, CartBR);
+	SetWriteHandler(0x5000, 0x5FFF, writeReg);
-	SetWriteHandler(0x5000, 0x5FFF, M556WriteReg);
+	applyMode(1);
-	SetWriteHandler(0x8000, 0xFFFF, M556Write);
-
-	if (WRAM) {
-		setprg8r(0x10, 0x6000, 0);
-		SetReadHandler(0x6000, 0x7FFF, CartBR);
-		SetWriteHandler(0x6000, 0x7FFF, CartBW);
-	}
 }
 
-static void M556Close(void) {
+static void restore (int version) {
-	if (WRAM) {
+	applyMode(0);
-		FCEU_gfree(WRAM);
-	}
-	WRAM = NULL;
 }
 
-static void StateRestore(int version) {
+void Mapper556_Init (CartInfo *info) {
-	Sync();
+	MMC3_addExState();
-}
+	VRC24_addExState();
-
+	WRAM_init(info, 8);
-void Mapper556_Init(CartInfo *info) {
+	info->Reset = reset;
-	info->Reset = M556Reset;
+	info->Power = power;
-	info->Power = M556Power;
+	GameStateRestore = restore;
-	info->Close = M556Close;
-	MapIRQHook = M556CPUHook;
-	GameHBIRQHook = M556HBHook;
-	GameStateRestore = StateRestore;
 	AddExState(StateRegs, ~0, 0, 0);
-
-	WRAMSIZE = info->PRGRamSize + info->PRGRamSaveSize;
-	if (WRAMSIZE) {
-		WRAM = (uint8 *)FCEU_gmalloc(WRAMSIZE);
-		SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
-		AddExState(WRAM, WRAMSIZE, 0, "WRAM");
-		if (info->battery) {
-			info->SaveGame[0] = WRAM;
-			info->SaveGameLen[0] = WRAMSIZE;
-		}
-	}
 }

src/boards/asic_tc3294.c

@@ -37,14 +37,14 @@ void TC3294_syncWRAM (int OR) {
 }
 
 void TC3294_syncPRG (int AND, int OR) {
-	int prgAND =~TC3294_reg[3] &0x3F;
+	int prgAND = ~TC3294_reg[3] &0x3F;
 	int prgOR  = TC3294_reg[1] | TC3294_reg[2] <<2 &0x300;
 	MMC3_syncPRG(prgAND &AND, prgOR &~prgAND &AND | OR &~AND);
 }
 
 void TC3294_syncCHR (int AND, int OR) {
-	int chrAND =0xFF >>(~TC3294_reg[2] &0xF);
+	int chrAND = 0xFF >>(~TC3294_reg[2] &0xF);
-	int chrOR  =TC3294_reg[0] | TC3294_reg[2] <<4 &0xF00;
+	int chrOR  = TC3294_reg[0] | TC3294_reg[2] <<4 &0xF00;
 	MMC3_syncCHR(chrAND &AND, chrOR &~chrAND &AND | OR &~AND);
 }
 
@@ -54,7 +54,7 @@ void TC3294_syncMirror () {
 
 DECLFW(TC3294_write) {
 	if (~TC3294_reg[3] &0x40) {
-		TC3294_reg[TC3294_index++ &3] =V;
+		TC3294_reg[TC3294_index++ &3] = V;
 		TC3294_cbSync();
 	}
 }