Mapper 556: use the modularized ASIC cores.
This commit is contained in:
NewRisingSun
336
src/boards/556.c
336
src/boards/556.c
@@ -19,312 +19,84 @@
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*/
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/* NES 2.0 Mapper 556
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* Used for the for the 超强å°æ–°2+ç‘ªèŽ‰å®¶æ— 7-in-1 (JY-215) multicart.
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* Used for the for the 餓狼傳說 激鬥篇 HiK 7-in-1 (JY-215) multicart.
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*/
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#include "mapinc.h"
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#include "asic_mmc3.h"
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#include "asic_vrc2and4.h"
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#include "wram.h"
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static uint8 reg[5];
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static uint8 mmc3Reg[8];
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static uint8 mmc3Cmd;
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static uint8 mmc3Mirr;
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static uint8 mmc3Wram;
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static uint8 mmc3IRQLatch;
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static uint8 mmc3IRQCount;
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static uint8 mmc3IRQa;
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static uint8 mmc3IRQReload;
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static uint8 vrc4Prg[2];
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static uint8 vrc4Mirr;
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static uint8 vrc4Misc;
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static uint16 vrc4Chr[8];
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static uint8 vrc4IRQLatch;
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static uint8 vrc4IRQa;
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static uint8 vrc4IRQCount;
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static int16 vrc4IRQCycles;
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static uint8 *WRAM = NULL;
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static uint32 WRAMSIZE = 0;
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static uint8 reg[4];
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static uint8 index;
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static SFORMAT StateRegs[] = {
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{ reg, 5, "REGS" },
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{ mmc3Reg, 8, "MMC3" },
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{ &mmc3Cmd, 1, "M3IX" },
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{ &mmc3Mirr, 1, "M3MI" },
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{ &mmc3Wram, 1, "M3WR" },
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{ &mmc3IRQLatch, 1, "M3RL" },
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{ &mmc3IRQCount, 1, "M3CN" },
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{ &mmc3IRQa, 1, "M3IQ" },
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{ &mmc3IRQReload, 1, "M3IR" },
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{ vrc4Prg, 2, "V4PR" },
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{ &vrc4Mirr, 1, "V4MI" },
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{ &vrc4Misc, 1, "V4MS" },
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{ vrc4Chr, 16, "V4CH" },
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{ &vrc4IRQLatch, 1, "VILA" },
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{ &vrc4IRQa, 1, "VIMO" },
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{ &vrc4IRQCount, 1, "VICO" },
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{ &vrc4IRQCycles, 2, "VICY" },
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{ &index, 1, "INDX" },
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{ 0 },
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};
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static void Sync(void) {
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uint32 prgmask = ~reg[3] & 0x3F;
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uint32 prgbase = ((reg[3] & 0x40) << 2) | reg[1];
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uint32 chrmask = 0xFF >> (~reg[2] & 0x0F);
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uint32 chrbase = ((reg[3] & 0x40) << 6) | ((reg[2] & 0xF0) << 4) | reg[0];
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uint32 cbase = 0; /* prg/chr bank flip flag */
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if (~reg[2] & 0x80) {
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/* MMC3 */
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cbase = (mmc3Cmd << 8) & 0x4000;
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setprg8(0x8000 ^ cbase, (prgbase & ~prgmask) | (mmc3Reg[6] & prgmask));
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setprg8(0xA000, (prgbase & ~prgmask) | (mmc3Reg[7] & prgmask));
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setprg8(0xC000 ^ cbase, (prgbase & ~prgmask) | (0xFE & prgmask));
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setprg8(0xE000, (prgbase & ~prgmask) | (0xFF & prgmask));
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cbase = (mmc3Cmd << 5) & 0x1000;
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setchr1(0x0000 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[0] & 0xFE) & chrmask));
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setchr1(0x0400 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[0] | 0x01) & chrmask));
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setchr1(0x0800 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[1] & 0xFE) & chrmask));
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setchr1(0x0C00 ^ cbase, (chrbase & ~chrmask) | ((mmc3Reg[1] | 0x01) & chrmask));
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setchr1(0x1000 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[2] & chrmask));
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setchr1(0x1400 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[3] & chrmask));
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setchr1(0x1800 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[4] & chrmask));
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setchr1(0x1C00 ^ cbase, (chrbase & ~chrmask) | (mmc3Reg[5] & chrmask));
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setmirror((mmc3Mirr & 0x01) ^ 1);
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static void sync (void) {
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int prgAND = ~reg[3] &0x3F;
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int chrAND = 0xFF >>(~reg[2] &0xF);
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int prgOR = (reg[1] | reg[3] <<2 &0x100) &~prgAND;
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int chrOR = (reg[0] | reg[2] <<4 &0x0F00 | reg[3] <<6 &0x1000) &~chrAND;
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if (reg[2] &0x80) {
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VRC24_syncWRAM(0);
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VRC24_syncPRG(prgAND, prgOR);
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VRC24_syncCHR(chrAND, chrOR);
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VRC24_syncMirror();
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} else {
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/* VRC4 mode */
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cbase = (vrc4Misc << 13) & 0x4000;
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setprg8(0x8000 ^ cbase, (prgbase & ~prgmask) | (vrc4Prg[0] & prgmask));
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setprg8(0xA000, (prgbase & ~prgmask) | (vrc4Prg[1] & prgmask));
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setprg8(0xC000 ^ cbase, (prgbase & ~prgmask) | (0xFE & prgmask));
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setprg8(0xE000, (prgbase & ~prgmask) | (0xFF & prgmask));
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setchr1(0x0000, (chrbase & ~chrmask) | (vrc4Chr[0] & chrmask));
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setchr1(0x0400, (chrbase & ~chrmask) | (vrc4Chr[1] & chrmask));
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setchr1(0x0800, (chrbase & ~chrmask) | (vrc4Chr[2] & chrmask));
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setchr1(0x0C00, (chrbase & ~chrmask) | (vrc4Chr[3] & chrmask));
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setchr1(0x1000, (chrbase & ~chrmask) | (vrc4Chr[4] & chrmask));
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setchr1(0x1400, (chrbase & ~chrmask) | (vrc4Chr[5] & chrmask));
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setchr1(0x1800, (chrbase & ~chrmask) | (vrc4Chr[6] & chrmask));
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setchr1(0x1C00, (chrbase & ~chrmask) | (vrc4Chr[7] & chrmask));
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switch (vrc4Mirr & 0x03) {
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case 0: setmirror(MI_V); break;
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case 1: setmirror(MI_H); break;
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case 2: setmirror(MI_0); break;
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case 3: setmirror(MI_1); break;
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}
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MMC3_syncWRAM(0);
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MMC3_syncPRG(prgAND, prgOR);
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MMC3_syncCHR(chrAND, chrOR);
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MMC3_syncMirror();
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}
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}
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static DECLFW(writeMMC3) {
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switch (A & 0xE001) {
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case 0x8000:
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mmc3Cmd = V;
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Sync();
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break;
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case 0x8001:
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mmc3Reg[mmc3Cmd & 7] = V;
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Sync();
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break;
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case 0xA000:
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mmc3Mirr = V;
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Sync();
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break;
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case 0xA001:
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mmc3Wram = V;
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Sync();
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break;
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case 0xC000:
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mmc3IRQLatch = V;
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break;
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case 0xC001:
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mmc3IRQReload = 1;
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break;
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case 0xE000:
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mmc3IRQa = 0;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xE001:
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mmc3IRQa = 1;
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break;
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static void applyMode (uint8 clear) {
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if (reg[2] &0x80)
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VRC4_activate(clear, sync, 0x05, 0x0A, 1, NULL, NULL, NULL, NULL, NULL);
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else
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MMC3_activate(clear, sync, MMC3_TYPE_AX5202P, NULL, NULL, NULL, NULL);
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}
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static DECLFW(writeReg) {
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if (~reg[3] &0x80) {
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reg[index++ &3] = V;
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if (index == 3)
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applyMode(1);
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else
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sync();
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}
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}
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static DECLFW(writeVRC4) {
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uint8 index;
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A = (A & 0xF000) | ((A >> 2) & 3) | (A & 3);
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switch (A & 0xF000) {
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case 0x8000:
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case 0xA000:
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vrc4Prg[(A >> 13) & 1] = V;
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Sync();
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break;
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case 0x9000:
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if (~A & 2) {
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vrc4Mirr = V;
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} else if (~A & 1) {
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vrc4Misc = V;
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}
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Sync();
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break;
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case 0xF000:
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switch (A & 3) {
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case 0:
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vrc4IRQLatch = (vrc4IRQLatch & 0xF0) | (V & 0x0F);
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break;
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case 1:
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vrc4IRQLatch = (vrc4IRQLatch & 0x0F) | (V << 4);
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break;
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case 2:
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vrc4IRQa = V;
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if (vrc4IRQa & 0x02) {
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vrc4IRQCount = vrc4IRQLatch;
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vrc4IRQCycles = 341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3:
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vrc4IRQa = (vrc4IRQa & ~0x02) | ((vrc4IRQa << 1) & 0x02);
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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break;
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default:
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index = ((A - 0xB000) >> 11) | ((A >> 1) & 1);
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if (A & 1) {
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vrc4Chr[index] = (vrc4Chr[index] & 0x0F) | (V << 4);
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} else {
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vrc4Chr[index] = (vrc4Chr[index] & ~0x0F) | (V & 0x0F);
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}
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Sync();
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break;
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}
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}
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static DECLFW(M556WriteReg) {
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if (~reg[3] & 0x80) {
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reg[reg[4] & 3] = V;
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reg[4]++;
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Sync();
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}
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}
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static DECLFW(M556Write) {
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if (~reg[2] & 0x80) {
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writeMMC3(A, V);
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} else {
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writeVRC4(A, V);
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}
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}
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static void FP_FASTAPASS(1) M556CPUHook(int a) {
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int count = a;
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if (~reg[2] & 0x80) {
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return;
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}
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/* VRC4 IRQ mode */
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while (count--) {
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if ((vrc4IRQa & 0x02) && ((vrc4IRQa & 0x04) || ((vrc4IRQCycles -= 3) <= 0))) {
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if (~vrc4IRQa & 0x04) {
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vrc4IRQCycles += 341;
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}
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if (!++vrc4IRQCount) {
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vrc4IRQCount = vrc4IRQLatch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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}
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static void M556HBHook(void) {
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int count = mmc3IRQCount;
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if (reg[2] & 0x80) {
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return;
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}
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/* MMC3 IRQ mode */
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if (!count || mmc3IRQReload) {
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mmc3IRQCount = mmc3IRQLatch;
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} else {
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mmc3IRQCount--;
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}
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if (count && !mmc3IRQCount && mmc3IRQa) {
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X6502_IRQBegin(FCEU_IQEXT);
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}
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mmc3IRQReload = 0;
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}
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static void M556Reset(void) {
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int i;
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for (i = 0; i < 5; i++) {
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reg[i] = 0;
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}
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static void reset (void) {
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reg[0] = reg[1] = reg[3] = 0;
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reg[2] = 0x0F;
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Sync();
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index = 0;
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applyMode(1);
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}
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static void M556Power(void) {
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int i;
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for (i = 0; i < 5; i++) {
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reg[i] = 0;
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}
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for (i = 0; i < 8; i++) {
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mmc3Reg[i] = 0;
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}
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for (i = 0; i < 2; i++) {
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vrc4Prg[i] = 0;
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}
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for (i = 0; i < 8; i++) {
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vrc4Chr[i] = 0;
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}
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mmc3Cmd = mmc3Mirr = mmc3Wram = mmc3IRQLatch = mmc3IRQCount = mmc3IRQa = mmc3IRQReload = 0;
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vrc4Mirr = vrc4Misc = vrc4IRQLatch = vrc4IRQa = vrc4IRQCount = vrc4IRQCycles = 0;
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static void power (void) {
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reg[0] = reg[1] = reg[3] = 0;
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reg[2] = 0x0F;
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Sync();
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x5000, 0x5FFF, M556WriteReg);
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SetWriteHandler(0x8000, 0xFFFF, M556Write);
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if (WRAM) {
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setprg8r(0x10, 0x6000, 0);
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SetReadHandler(0x6000, 0x7FFF, CartBR);
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SetWriteHandler(0x6000, 0x7FFF, CartBW);
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}
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index = 0;
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetWriteHandler(0x5000, 0x5FFF, writeReg);
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applyMode(1);
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}
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static void M556Close(void) {
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if (WRAM) {
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FCEU_gfree(WRAM);
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}
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WRAM = NULL;
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static void restore (int version) {
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applyMode(0);
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}
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static void StateRestore(int version) {
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Sync();
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}
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void Mapper556_Init(CartInfo *info) {
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info->Reset = M556Reset;
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info->Power = M556Power;
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info->Close = M556Close;
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MapIRQHook = M556CPUHook;
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GameHBIRQHook = M556HBHook;
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GameStateRestore = StateRestore;
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void Mapper556_Init (CartInfo *info) {
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MMC3_addExState();
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VRC24_addExState();
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WRAM_init(info, 8);
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info->Reset = reset;
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info->Power = power;
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GameStateRestore = restore;
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AddExState(StateRegs, ~0, 0, 0);
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WRAMSIZE = info->PRGRamSize + info->PRGRamSaveSize;
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if (WRAMSIZE) {
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WRAM = (uint8 *)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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if (info->battery) {
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info->SaveGame[0] = WRAM;
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info->SaveGameLen[0] = WRAMSIZE;
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}
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}
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}
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@@ -37,14 +37,14 @@ void TC3294_syncWRAM (int OR) {
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}
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void TC3294_syncPRG (int AND, int OR) {
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int prgAND =~TC3294_reg[3] &0x3F;
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int prgAND = ~TC3294_reg[3] &0x3F;
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int prgOR = TC3294_reg[1] | TC3294_reg[2] <<2 &0x300;
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MMC3_syncPRG(prgAND &AND, prgOR &~prgAND &AND | OR &~AND);
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}
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void TC3294_syncCHR (int AND, int OR) {
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int chrAND =0xFF >>(~TC3294_reg[2] &0xF);
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int chrOR =TC3294_reg[0] | TC3294_reg[2] <<4 &0xF00;
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int chrAND = 0xFF >>(~TC3294_reg[2] &0xF);
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int chrOR = TC3294_reg[0] | TC3294_reg[2] <<4 &0xF00;
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MMC3_syncCHR(chrAND &AND, chrOR &~chrAND &AND | OR &~AND);
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}
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@@ -54,7 +54,7 @@ void TC3294_syncMirror () {
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DECLFW(TC3294_write) {
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if (~TC3294_reg[3] &0x40) {
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TC3294_reg[TC3294_index++ &3] =V;
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TC3294_reg[TC3294_index++ &3] = V;
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TC3294_cbSync();
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}
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}
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