Add mapper 446 using mapper emulation cores that can be included in other multi-ASIC mappers.
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165
src/boards/asic_h3001.c
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165
src/boards/asic_h3001.c
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2025 NewRisingSun
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "asic_h3001.h"
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static void (*H3001_cbSync)();
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static uint8 H3001_prg[2];
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static uint8 H3001_chr[8];
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static uint8 H3001_layout;
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static uint8 H3001_nt;
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static uint8 H3001_irq;
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static uint16 H3001_reload;
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static uint16 H3001_count;
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static SFORMAT H3001_state[] = {
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{ H3001_prg, 2, "H31P" },
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{ H3001_chr, 8, "H31C" },
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{&H3001_layout, 4, "H31L" },
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{&H3001_nt, 4, "H31M" },
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{&H3001_irq, 4, "H31N" },
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{&H3001_reload, 2, "H31R" },
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{&H3001_count, 2, "H31T" },
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{ 0 }
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};
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static int H3001_getPRGBank (uint8 bank) {
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if (H3001_layout &0x80 && ~bank &1) bank ^= 2;
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return bank &2? 0xFE | bank &1: H3001_prg[bank &1];
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}
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void H3001_syncPRG (int AND, int OR) {
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setprg8(0x8000, H3001_getPRGBank(0) &AND |OR);
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setprg8(0xA000, H3001_getPRGBank(1) &AND |OR);
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setprg8(0xC000, H3001_getPRGBank(2) &AND |OR);
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setprg8(0xE000, H3001_getPRGBank(3) &AND |OR);
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}
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void H3001_syncCHR (int AND, int OR) {
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setchr1(0x0000, H3001_chr[0]);
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setchr1(0x0400, H3001_chr[1]);
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setchr1(0x0800, H3001_chr[2]);
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setchr1(0x0C00, H3001_chr[3]);
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setchr1(0x1000, H3001_chr[4]);
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setchr1(0x1400, H3001_chr[5]);
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setchr1(0x1800, H3001_chr[6]);
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setchr1(0x1C00, H3001_chr[7]);
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}
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void H3001_syncMirror () {
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setmirror(H3001_nt &0x40? (H3001_nt &0x80? MI_1: MI_0): H3001_nt &0x80? MI_H: MI_V);
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}
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DECLFW(H3001_write) {
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switch(A >>12 &7) {
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case 0: case 2:
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H3001_prg[A >>13 &1] = V;
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H3001_cbSync();
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break;
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case 1:
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switch(A &7) {
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case 0:
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H3001_layout = V;
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H3001_cbSync();
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break;
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case 1:
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H3001_nt = V;
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H3001_cbSync();
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break;
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case 3:
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H3001_irq = V;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 4:
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H3001_count = H3001_reload;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 5:
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H3001_reload = H3001_reload &0x00FF | V <<8;
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break;
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case 6:
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H3001_reload = H3001_reload &0xFF00 | V;
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break;
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}
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break;
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case 3:
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H3001_chr[A &7] = V;
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H3001_cbSync();
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break;
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}
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}
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void FP_FASTAPASS(1) H3001_cpuCycle (int a) {
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while (a--) if (H3001_irq &0x80 && !--H3001_count) {
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X6502_IRQBegin(FCEU_IQEXT);
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H3001_irq = 0;
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}
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}
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static void H3001_clear () {
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int i;
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for (i = 0; i < 2; i++) H3001_prg[i] = i;
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for (i = 0; i < 8; i++) H3001_chr[i] = i;
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H3001_layout = H3001_nt = H3001_irq = 0;
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H3001_reload = H3001_count = 0;
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H3001_cbSync();
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}
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static void H3001_setHandlers () {
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SetReadHandler (0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x8000, 0xBFFF, H3001_write);
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MapIRQHook =H3001_cpuCycle;
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}
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static void H3001_configure (void (*sync)()) {
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H3001_cbSync = sync;
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}
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void H3001_activate (uint8 clear, void (*sync)()) {
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H3001_configure(sync);
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H3001_setHandlers();
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if (clear)
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H3001_clear();
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else
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H3001_cbSync();
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}
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void H3001_addExState () {
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AddExState(H3001_state, ~0, 0, 0);
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}
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void H3001_restore (int version) {
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H3001_cbSync();
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}
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void H3001_power () {
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H3001_setHandlers();
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H3001_clear();
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}
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void H3001_init (CartInfo *info, void (*sync)()) {
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H3001_addExState();
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H3001_configure(sync);
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info->Power = H3001_power;
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info->Reset = H3001_cbSync;
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GameStateRestore = H3001_cbSync;
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}
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