Style nits, C89 build fixes
This commit is contained in:
twinaphex
@@ -45,7 +45,7 @@ static uint8 adder;
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static uint8 test;
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static uint8 test;
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static uint8 dipSwitch;
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static uint8 dipSwitch;
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static writefunc cpuWriteHandlers[0x10000]; // Actual write handlers for CPU write trapping as a method fo IRQ clocking
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static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
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static SFORMAT JYASIC_stateRegs[] = {
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static SFORMAT JYASIC_stateRegs[] = {
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{ &irqControl, 1, "IRQM" },
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{ &irqControl, 1, "IRQM" },
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@@ -96,50 +96,69 @@ static void syncPRG (int AND, int OR) {
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prg6000 =rev(prg[3]);
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prg6000 =rev(prg[3]);
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break;
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break;
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}
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}
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if (mode[0] &0x80) // Map ROM
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if (mode[0] &0x80) /* Map ROM */
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setprg8 (0x6000, prg6000 &AND |OR);
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setprg8 (0x6000, prg6000 &AND |OR);
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else
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else
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if (WRAMSIZE) // Otherwise map WRAM if it exists
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if (WRAMSIZE) /* Otherwise map WRAM if it exists */
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setprg8r(0x10, 0x6000, 0);
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setprg8r(0x10, 0x6000, 0);
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}
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}
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static void syncCHR (int AND, int OR) {
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static void syncCHR (int AND, int OR)
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08) // MMC4 mode[0] with 4 KiB CHR mode[0]
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{
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08) /* MMC4 mode[0] with 4 KiB CHR mode[0] */
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else
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
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switch(mode[0] &0x18) {
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else
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case 0x00: // 8 KiB CHR mode[0]
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switch(mode[0] &0x18) {
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setchr8(chr[0] &AND >>3 | OR >>3);
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case 0x00: /* 8 KiB CHR mode[0] */
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break;
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setchr8(chr[0] &AND >>3 | OR >>3);
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case 0x08: // 4 KiB CHR mode[0]
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break;
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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case 0x08: /* 4 KiB CHR mode[0] */
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break;
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for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
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case 0x10:
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break;
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for (int chrBank =0; chrBank <8; chrBank +=2) setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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case 0x10:
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break;
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for (int chrBank =0; chrBank <8; chrBank +=2) setchr2(0x400 *chrBank, chr[chrBank] &AND >>1 | OR >>1);
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case 0x18:
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break;
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for (int chrBank =0; chrBank <8; chrBank +=1) setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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case 0x18:
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break;
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for (int chrBank =0; chrBank <8; chrBank +=1) setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
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}
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break;
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PPUCHRRAM =mode[2] &0x40? 0xFF: 0x00; // Write-protect or write-enable CHR-RAM
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}
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PPUCHRRAM =mode[2] &0x40? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
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}
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}
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static void syncNT (int AND, int OR) {
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static void syncNT (int AND, int OR)
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if (mode[0] &0x20 || mode[1] &0x08) { // ROM nametables or extended mirroring
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{
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// First, set normal CIRAM pages using extended registers ...
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if (mode[0] &0x20 || mode[1] &0x08)
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setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
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{
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/* ROM nametables or extended mirroring */
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/* First, set normal CIRAM pages using extended registers ... */
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setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
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if (mode[0] &0x20) for (int ntBank =0; ntBank <4; ntBank++) { // Then replace with ROM nametables if such are generally enabled
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if (mode[0] &0x20) for (int ntBank =0; ntBank <4; ntBank++)
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40); // ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7
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{
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if (vromHere) setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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/* Then replace with ROM nametables if such are generally enabled */
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}
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int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
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} else
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/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
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switch (mode[1] &0x03) { // Regularly mirrored CIRAM
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if (vromHere)
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case 0: setmirror(MI_V); break;
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setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
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case 1: setmirror(MI_H); break;
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}
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case 2: setmirror(MI_0); break;
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}
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case 3: setmirror(MI_1); break;
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else
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}
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switch (mode[1] &0x03)
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{
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/* Regularly mirrored CIRAM */
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case 0:
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setmirror(MI_V);
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break;
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case 1:
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setmirror(MI_H);
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break;
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case 2:
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setmirror(MI_0);
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break;
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case 3:
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setmirror(MI_1);
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break;
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}
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}
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}
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static void clockIRQ (void) {
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static void clockIRQ (void) {
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@@ -156,51 +175,87 @@ static void clockIRQ (void) {
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}
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}
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}
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}
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static DECLFW(trapCPUWrite) {
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static DECLFW(trapCPUWrite)
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if ((irqControl &0x03) ==0x03) clockIRQ(); // Clock IRQ counter on CPU writes
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{
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if ((irqControl &0x03) ==0x03)
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clockIRQ(); /* Clock IRQ counter on CPU writes */
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cpuWriteHandlers[A](A, V);
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cpuWriteHandlers[A](A, V);
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}
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}
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A) {
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static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A)
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if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A) for (int i =0; i <2; i++) clockIRQ(); // Clock IRQ counter on PPU "reads"
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{
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0)) { // If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ...
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if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A)
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latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); // ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index.
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{
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sync();
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int i;
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}
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for (i =0; i <2; i++)
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lastPPUAddress =A;
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clockIRQ(); /* Clock IRQ counter on PPU "reads" */
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}
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if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0))
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{
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/* If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ... */
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latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); /* ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index. */
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sync();
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}
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lastPPUAddress =A;
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}
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}
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static void ppuScanline(void) {
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static void ppuScanline(void)
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if ((irqControl &0x03) ==0x01) for (int i =0; i <8; i++) clockIRQ(); // Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that.
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{
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if ((irqControl &0x03) ==0x01)
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{
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int i;
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for (i =0; i <8; i++)
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clockIRQ(); /* Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that. */
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}
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}
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}
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void FP_FASTAPASS(1) cpuCycle(int a) {
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void FP_FASTAPASS(1) cpuCycle(int a)
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if ((irqControl &0x03) ==0x00) while (a--) clockIRQ(); // Clock IRQ counter on M2 cycles
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{
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if ((irqControl &0x03) ==0x00)
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while (a--)
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clockIRQ(); /* Clock IRQ counter on M2 cycles */
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}
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}
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static DECLFR(readALU_DIP) {
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static DECLFR(readALU_DIP)
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if ((A &0x3FF) ==0 && A !=0x5800) // 5000, 5400, 5C00: read solder pad setting
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{
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return dipSwitch | X.DB &0x3F;
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if ((A &0x3FF) ==0 && A !=0x5800) /* 5000, 5400, 5C00: read solder pad setting */
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else
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return dipSwitch | X.DB &0x3F;
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if (A &0x800) switch (A &3) { // 5800-5FFF: read ALU
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case 0: return (mul[0] *mul[1]) &0xFF;
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if (A &0x800)
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case 1: return (mul[0] *mul[1]) >>8;
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switch (A &3)
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case 2: return adder;
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{
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case 3: return test;
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/* 5800-5FFF: read ALU */
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}
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case 0:
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// all others
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return (mul[0] *mul[1]) &0xFF;
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return X.DB;
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case 1:
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return (mul[0] *mul[1]) >>8;
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case 2:
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return adder;
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case 3:
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return test;
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}
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/* all others */
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return X.DB;
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}
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}
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static DECLFW(writeALU) {
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static DECLFW(writeALU)
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switch (A &3) {
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{
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case 0: mul[0] =V; break;
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switch (A &3)
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case 1: mul[1] =V; break;
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{
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case 2: adder +=V; break;
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case 0:
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case 3: test =V;
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mul[0] =V;
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adder =0;
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break;
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break;
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case 1:
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}
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mul[1] =V;
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break;
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case 2:
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adder +=V;
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break;
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case 3:
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test = V;
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adder = 0;
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break;
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}
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}
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}
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static DECLFW(writePRG) {
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static DECLFW(writePRG) {
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@@ -226,258 +281,349 @@ static DECLFW(writeNT) {
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sync();
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sync();
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}
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}
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static DECLFW(writeIRQ) {
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static DECLFW(writeIRQ)
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switch (A &7) {
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{
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case 0: irqEnabled =!!(V &1);
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switch (A &7)
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if (!irqEnabled) {
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{
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irqPrescaler =0;
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case 0:
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X6502_IRQEnd(FCEU_IQEXT);
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irqEnabled =!!(V &1);
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}
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if (!irqEnabled)
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break;
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{
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case 1: irqControl =V;
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irqPrescaler =0;
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break;
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X6502_IRQEnd(FCEU_IQEXT);
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case 2: irqEnabled =0;
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}
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irqPrescaler =0;
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break;
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X6502_IRQEnd(FCEU_IQEXT);
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case 1:
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break;
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irqControl =V;
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case 3: irqEnabled =1;
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break;
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break;
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case 2:
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case 4: irqPrescaler =V ^irqXor;
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irqEnabled =0;
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break;
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irqPrescaler =0;
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case 5: irqCounter =V ^irqXor;
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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break;
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case 6: irqXor =V;
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case 3:
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break;
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irqEnabled =1;
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}
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break;
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case 4:
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irqPrescaler =V ^irqXor;
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break;
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case 5:
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irqCounter =V ^irqXor;
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break;
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case 6:
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irqXor =V;
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break;
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}
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}
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}
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static DECLFW(writeMode) {
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static DECLFW(writeMode)
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switch (A &3) {
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{
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case 0: mode[0] =V;
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switch (A &3)
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if (!allowExtendedMirroring) mode[0] &=~0x20;
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{
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break;
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case 0:
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case 1: mode[1] =V;
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mode[0] =V;
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if (!allowExtendedMirroring) mode[1] &=~0x08;
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if (!allowExtendedMirroring)
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break;
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mode[0] &=~0x20;
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case 2: mode[2] =V;
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break;
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break;
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case 1:
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case 3: mode[3] =V;
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mode[1] =V;
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break;
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if (!allowExtendedMirroring)
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}
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mode[1] &=~0x08;
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break;
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case 2:
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mode[2] =V;
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break;
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case 3:
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mode[3] =V;
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break;
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}
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sync();
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sync();
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}
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}
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static void JYASIC_power(void) {
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static void JYASIC_power(void)
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SetWriteHandler(0x5000, 0x5FFF, writeALU);
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{
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SetWriteHandler(0x6000, 0x7fff, CartBW);
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unsigned int i;
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SetWriteHandler(0x8000, 0x87FF, writePRG); // 8800-8FFF ignored
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SetWriteHandler(0x9000, 0x97FF, writeCHRLow); // 9800-9FFF ignored
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SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); // A800-AFFF ignored
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SetWriteHandler(0xB000, 0xB7FF, writeNT); // B800-BFFF ignored
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SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
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SetWriteHandler(0xD000, 0xD7FF, writeMode); // D800-DFFF ignored
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for (unsigned int i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
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SetWriteHandler(0x5000, 0x5FFF, writeALU);
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SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); // Trap all CPU writes for IRQ clocking purposes
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SetWriteHandler(0x6000, 0x7fff, CartBW);
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SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
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SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
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SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
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SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
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SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
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SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
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SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
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for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
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mul[0] = mul[1] = adder = test = dipSwitch = 0;
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SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
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mode[0] = mode[1] = mode[2] = mode[3] =0;
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SetReadHandler(0x6000, 0xFFFF, CartBR);
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irqControl =irqEnabled = irqPrescaler =irqCounter = irqXor = lastPPUAddress = 0;
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memset(prg, 0, sizeof(prg));
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memset(chr, 0, sizeof(chr));
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memset(nt, 0, sizeof(nt));
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latch[0] =0;
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latch[1] =4;
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sync();
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mul[0] = mul[1] = adder = test = dipSwitch = 0;
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mode[0] = mode[1] = mode[2] = mode[3] = 0;
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irqControl =irqEnabled = irqPrescaler =irqCounter = irqXor = lastPPUAddress = 0;
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memset(prg, 0, sizeof(prg));
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memset(chr, 0, sizeof(chr));
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memset(nt, 0, sizeof(nt));
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latch[0] =0;
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latch[1] =4;
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sync();
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}
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}
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static void JYASIC_reset (void) {
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static void JYASIC_reset (void)
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{
|
||||||
dipSwitch = (dipSwitch +0x40) &0xC0;
|
dipSwitch = (dipSwitch +0x40) &0xC0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void JYASIC_restore (int version) {
|
static void JYASIC_restore (int version)
|
||||||
|
{
|
||||||
sync();
|
sync();
|
||||||
}
|
}
|
||||||
|
|
||||||
void JYASIC_init (CartInfo *info) {
|
void JYASIC_init (CartInfo *info)
|
||||||
info->Reset = JYASIC_reset;
|
{
|
||||||
info->Power = JYASIC_power;
|
info->Reset = JYASIC_reset;
|
||||||
PPU_hook = trapPPUAddressChange;
|
info->Power = JYASIC_power;
|
||||||
MapIRQHook = cpuCycle;
|
PPU_hook = trapPPUAddressChange;
|
||||||
GameHBIRQHook2 = ppuScanline;
|
MapIRQHook = cpuCycle;
|
||||||
AddExState(JYASIC_stateRegs, ~0, 0, 0);
|
GameHBIRQHook2 = ppuScanline;
|
||||||
GameStateRestore = JYASIC_restore;
|
AddExState(JYASIC_stateRegs, ~0, 0, 0);
|
||||||
|
GameStateRestore = JYASIC_restore;
|
||||||
|
|
||||||
// WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size
|
/* WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size */
|
||||||
if (info->iNES2)
|
if (info->iNES2)
|
||||||
WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize;
|
WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize;
|
||||||
else
|
else
|
||||||
WRAMSIZE =info->mapper ==35? 8192: 0;
|
WRAMSIZE =info->mapper ==35? 8192: 0;
|
||||||
|
|
||||||
if (WRAMSIZE) {
|
if (WRAMSIZE)
|
||||||
WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
|
{
|
||||||
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
|
WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
|
||||||
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
|
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
|
||||||
}
|
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void syncSingleCart (void) {
|
static void syncSingleCart (void)
|
||||||
syncPRG(0x3F, mode[3] <<5 &~0x3F);
|
{
|
||||||
if (mode[3] &0x20) {
|
syncPRG(0x3F, mode[3] <<5 &~0x3F);
|
||||||
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
if (mode[3] &0x20)
|
||||||
syncNT (0x1FF, mode[3] <<6 &0x600);
|
{
|
||||||
} else {
|
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
syncNT (0x1FF, mode[3] <<6 &0x600);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
}
|
||||||
}
|
else
|
||||||
|
{
|
||||||
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
||||||
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
void Mapper35_Init(CartInfo *info) { // Basically mapper 90/209/211 with WRAM
|
void Mapper35_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Basically mapper 90/209/211 with WRAM */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =syncSingleCart;
|
sync =syncSingleCart;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
void Mapper90_Init(CartInfo *info) { // Single cart, extended mirroring and ROM nametables disabled
|
void Mapper90_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Single cart, extended mirroring and ROM nametables disabled */
|
||||||
allowExtendedMirroring =0;
|
allowExtendedMirroring =0;
|
||||||
sync =syncSingleCart;
|
sync =syncSingleCart;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
void Mapper209_Init(CartInfo *info) { // Single cart, extended mirroring and ROM nametables enabled
|
|
||||||
allowExtendedMirroring =1;
|
void Mapper209_Init(CartInfo *info)
|
||||||
sync =syncSingleCart;
|
{
|
||||||
JYASIC_init(info);
|
/* Single cart, extended mirroring and ROM nametables enabled */
|
||||||
}
|
|
||||||
void Mapper211_Init(CartInfo *info) { // Duplicate of mapper 209
|
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =syncSingleCart;
|
sync =syncSingleCart;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void sync281 (void) {
|
void Mapper211_Init(CartInfo *info)
|
||||||
syncPRG(0x1F, mode[3] <<5);
|
{
|
||||||
syncCHR(0xFF, mode[3] <<8);
|
/* Duplicate of mapper 209 */
|
||||||
syncNT (0xFF, mode[3] <<8);
|
allowExtendedMirroring =1;
|
||||||
|
sync =syncSingleCart;
|
||||||
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
void Mapper281_Init(CartInfo *info) { // Multicart
|
|
||||||
|
static void sync281 (void)
|
||||||
|
{
|
||||||
|
syncPRG(0x1F, mode[3] <<5);
|
||||||
|
syncCHR(0xFF, mode[3] <<8);
|
||||||
|
syncNT (0xFF, mode[3] <<8);
|
||||||
|
}
|
||||||
|
|
||||||
|
void Mapper281_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync281;
|
sync =sync281;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void sync282 (void) {
|
static void sync282 (void)
|
||||||
|
{
|
||||||
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
||||||
if (mode[3] &0x20) {
|
if (mode[3] &0x20)
|
||||||
|
{
|
||||||
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
syncCHR(0x1FF, mode[3] <<6 &0x600);
|
||||||
syncNT (0x1FF, mode[3] <<6 &0x600);
|
syncNT (0x1FF, mode[3] <<6 &0x600);
|
||||||
} else {
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
void Mapper282_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper282_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync282;
|
sync =sync282;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync295 (void) {
|
void sync295 (void)
|
||||||
syncPRG(0x0F, mode[3] <<4);
|
{
|
||||||
syncCHR(0x7F, mode[3] <<7);
|
syncPRG(0x0F, mode[3] <<4);
|
||||||
syncNT (0x7F, mode[3] <<7);
|
syncCHR(0x7F, mode[3] <<7);
|
||||||
|
syncNT (0x7F, mode[3] <<7);
|
||||||
}
|
}
|
||||||
void Mapper295_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper295_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync295;
|
sync =sync295;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync358 (void) {
|
void sync358 (void)
|
||||||
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
{
|
||||||
if (mode[3] &0x20) {
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
||||||
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
if (mode[3] &0x20)
|
||||||
syncNT (0x1FF, mode[3] <<7 &0x600);
|
{
|
||||||
} else {
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
}
|
||||||
}
|
else
|
||||||
|
{
|
||||||
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
void Mapper358_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper358_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync358;
|
sync =sync358;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync386 (void) {
|
void sync386 (void)
|
||||||
syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40);
|
{
|
||||||
if (mode[3] &0x20) {
|
syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40);
|
||||||
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
if (mode[3] &0x20)
|
||||||
syncNT (0x1FF, mode[3] <<7 &0x600);
|
{
|
||||||
} else {
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
}
|
||||||
}
|
else
|
||||||
|
{
|
||||||
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
void Mapper386_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper386_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync386;
|
sync =sync386;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync387 (void) {
|
void sync387(void)
|
||||||
|
{
|
||||||
syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20);
|
syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20);
|
||||||
if (mode[3] &0x20) {
|
if (mode[3] &0x20)
|
||||||
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
{
|
||||||
syncNT (0x1FF, mode[3] <<7 &0x600);
|
syncCHR(0x1FF, mode[3] <<7 &0x600);
|
||||||
} else {
|
syncNT (0x1FF, mode[3] <<7 &0x600);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
void Mapper387_Init(CartInfo *info) { // Multicart
|
|
||||||
allowExtendedMirroring =1;
|
void Mapper387_Init(CartInfo *info)
|
||||||
sync =sync387;
|
{
|
||||||
JYASIC_init(info);
|
/* Multicart */
|
||||||
|
allowExtendedMirroring =1;
|
||||||
|
sync =sync387;
|
||||||
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync388 (void) {
|
void sync388 (void)
|
||||||
syncPRG(0x1F, mode[3] <<3 &0x60);
|
{
|
||||||
if (mode[3] &0x20) {
|
syncPRG(0x1F, mode[3] <<3 &0x60);
|
||||||
syncCHR(0x1FF, mode[3] <<8 &0x200);
|
|
||||||
syncNT (0x1FF, mode[3] <<8 &0x200);
|
if (mode[3] &0x20)
|
||||||
} else {
|
{
|
||||||
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
syncCHR(0x1FF, mode[3] <<8 &0x200);
|
||||||
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
syncNT (0x1FF, mode[3] <<8 &0x200);
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
||||||
|
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
void Mapper388_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper388_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =0;
|
allowExtendedMirroring =0;
|
||||||
sync =sync388;
|
sync =sync388;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync397 (void) {
|
void sync397 (void)
|
||||||
|
{
|
||||||
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
||||||
syncCHR(0x7F, mode[3] <<7);
|
syncCHR(0x7F, mode[3] <<7);
|
||||||
syncNT (0x7F, mode[3] <<7);
|
syncNT (0x7F, mode[3] <<7);
|
||||||
}
|
}
|
||||||
void Mapper397_Init(CartInfo *info) { // Multicart
|
|
||||||
allowExtendedMirroring =1;
|
void Mapper397_Init(CartInfo *info)
|
||||||
sync =sync397;
|
{
|
||||||
JYASIC_init(info);
|
/* Multicart */
|
||||||
|
allowExtendedMirroring =1;
|
||||||
|
sync =sync397;
|
||||||
|
JYASIC_init(info);
|
||||||
}
|
}
|
||||||
|
|
||||||
void sync421 (void) {
|
void sync421 (void)
|
||||||
if (mode[3] &0x04)
|
{
|
||||||
syncPRG(0x3F, mode[3] <<4 &~0x3F);
|
if (mode[3] &0x04)
|
||||||
else
|
syncPRG(0x3F, mode[3] <<4 &~0x3F);
|
||||||
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
else
|
||||||
syncCHR(0x1FF, mode[3] <<8 &0x300);
|
syncPRG(0x1F, mode[3] <<4 &~0x1F);
|
||||||
syncNT (0x1FF, mode[3] <<8 &0x300);
|
syncCHR(0x1FF, mode[3] <<8 &0x300);
|
||||||
|
syncNT (0x1FF, mode[3] <<8 &0x300);
|
||||||
}
|
}
|
||||||
void Mapper421_Init(CartInfo *info) { // Multicart
|
|
||||||
|
void Mapper421_Init(CartInfo *info)
|
||||||
|
{
|
||||||
|
/* Multicart */
|
||||||
allowExtendedMirroring =1;
|
allowExtendedMirroring =1;
|
||||||
sync =sync421;
|
sync =sync421;
|
||||||
JYASIC_init(info);
|
JYASIC_init(info);
|
||||||
|
|||||||
Reference in New Issue
Block a user