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Style nits, C89 build fixes

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This commit is contained in:
twinaphex
2021-04-08 17:46:51 +02:00
parent 41df1a408d
commit 960528aa15
1 changed files with 381 additions and 235 deletions
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376
src/boards/jyasic.c
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@@ -45,7 +45,7 @@ static uint8 adder;
static uint8 test; static uint8 test;
static uint8 dipSwitch; static uint8 dipSwitch;
static writefunc cpuWriteHandlers[0x10000]; // Actual write handlers for CPU write trapping as a method fo IRQ clocking static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */
static SFORMAT JYASIC_stateRegs[] = { static SFORMAT JYASIC_stateRegs[] = {
{ &irqControl, 1, "IRQM" }, { &irqControl, 1, "IRQM" },
@@ -96,22 +96,23 @@ static void syncPRG (int AND, int OR) {
prg6000 =rev(prg[3]); prg6000 =rev(prg[3]);
break; break;
} }
if (mode[0] &0x80) // Map ROM if (mode[0] &0x80) /* Map ROM */
setprg8 (0x6000, prg6000 &AND |OR); setprg8 (0x6000, prg6000 &AND |OR);
else else
if (WRAMSIZE) // Otherwise map WRAM if it exists if (WRAMSIZE) /* Otherwise map WRAM if it exists */
setprg8r(0x10, 0x6000, 0); setprg8r(0x10, 0x6000, 0);
} }
static void syncCHR (int AND, int OR) { static void syncCHR (int AND, int OR)
if (mode[3] &0x80 && (mode[0] &0x18) ==0x08) // MMC4 mode[0] with 4 KiB CHR mode[0] {
if (mode[3] &0x80 && (mode[0] &0x18) ==0x08) /* MMC4 mode[0] with 4 KiB CHR mode[0] */
for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2); for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[latch[chrBank /4]&2 | chrBank] &AND >>2 | OR >>2);
else else
switch(mode[0] &0x18) { switch(mode[0] &0x18) {
case 0x00: // 8 KiB CHR mode[0] case 0x00: /* 8 KiB CHR mode[0] */
setchr8(chr[0] &AND >>3 | OR >>3); setchr8(chr[0] &AND >>3 | OR >>3);
break; break;
case 0x08: // 4 KiB CHR mode[0] case 0x08: /* 4 KiB CHR mode[0] */
for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2); for (int chrBank =0; chrBank <8; chrBank +=4) setchr4(0x400 *chrBank, chr[chrBank] &AND >>2 | OR >>2);
break; break;
case 0x10: case 0x10:
@@ -121,24 +122,42 @@ static void syncCHR (int AND, int OR) {
for (int chrBank =0; chrBank <8; chrBank +=1) setchr1(0x400 *chrBank, chr[chrBank] &AND | OR ); for (int chrBank =0; chrBank <8; chrBank +=1) setchr1(0x400 *chrBank, chr[chrBank] &AND | OR );
break; break;
} }
PPUCHRRAM =mode[2] &0x40? 0xFF: 0x00; // Write-protect or write-enable CHR-RAM PPUCHRRAM =mode[2] &0x40? 0xFF: 0x00; /* Write-protect or write-enable CHR-RAM */
} }
static void syncNT (int AND, int OR) { static void syncNT (int AND, int OR)
if (mode[0] &0x20 || mode[1] &0x08) { // ROM nametables or extended mirroring {
// First, set normal CIRAM pages using extended registers ... if (mode[0] &0x20 || mode[1] &0x08)
{
/* ROM nametables or extended mirroring */
/* First, set normal CIRAM pages using extended registers ... */
setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1); setmirrorw(nt[0] &1, nt[1] &1, nt[2] &1, nt[3] &1);
if (mode[0] &0x20) for (int ntBank =0; ntBank <4; ntBank++) { // Then replace with ROM nametables if such are generally enabled if (mode[0] &0x20) for (int ntBank =0; ntBank <4; ntBank++)
int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40); // ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 {
if (vromHere) setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank); /* Then replace with ROM nametables if such are generally enabled */
int vromHere =(nt[ntBank] &0x80) ^(mode[2] &0x80) |(mode[0] &0x40);
/* ROM nametables are used either when globally enabled via D000.6 or per-bank via B00x.7 vs. D002.7 */
if (vromHere)
setntamem(CHRptr[0] +0x400*((nt[ntBank] &AND | OR) & CHRmask1[0]), 0, ntBank);
} }
} else }
switch (mode[1] &0x03) { // Regularly mirrored CIRAM else
case 0: setmirror(MI_V); break; switch (mode[1] &0x03)
case 1: setmirror(MI_H); break; {
case 2: setmirror(MI_0); break; /* Regularly mirrored CIRAM */
case 3: setmirror(MI_1); break; case 0:
setmirror(MI_V);
break;
case 1:
setmirror(MI_H);
break;
case 2:
setmirror(MI_0);
break;
case 3:
setmirror(MI_1);
break;
} }
} }
@@ -156,48 +175,84 @@ static void clockIRQ (void) {
} }
} }
static DECLFW(trapCPUWrite) { static DECLFW(trapCPUWrite)
if ((irqControl &0x03) ==0x03) clockIRQ(); // Clock IRQ counter on CPU writes {
if ((irqControl &0x03) ==0x03)
clockIRQ(); /* Clock IRQ counter on CPU writes */
cpuWriteHandlers[A](A, V); cpuWriteHandlers[A](A, V);
} }
static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A) { static void FP_FASTAPASS(1) trapPPUAddressChange (uint32 A)
if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A) for (int i =0; i <2; i++) clockIRQ(); // Clock IRQ counter on PPU "reads" {
if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0)) { // If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ... if ((irqControl &0x03) ==0x02 && lastPPUAddress !=A)
latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); // ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index. {
int i;
for (i =0; i <2; i++)
clockIRQ(); /* Clock IRQ counter on PPU "reads" */
}
if (mode[3] &0x80 && (mode[0] &0x18) ==0x08 && ((A &0x2FF0) ==0xFD0 || (A &0x2FF0) ==0xFE0))
{
/* If MMC4 mode[0] is enabled, and CHR mode[0] is 4 KiB, and tile FD or FE is being fetched ... */
latch[A >>12 &1] =(A >>10 &4) | (A >>4 &2); /* ... switch the left or right pattern table's latch to 0 (FD) or 2 (FE), being used as an offset for the CHR register index. */
sync(); sync();
} }
lastPPUAddress =A; lastPPUAddress =A;
} }
static void ppuScanline(void) { static void ppuScanline(void)
if ((irqControl &0x03) ==0x01) for (int i =0; i <8; i++) clockIRQ(); // Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that. {
if ((irqControl &0x03) ==0x01)
{
int i;
for (i =0; i <8; i++)
clockIRQ(); /* Clock IRQ counter on A12 rises (eight per scanline). This should be done in trapPPUAddressChange, but would require more accurate PPU emulation for that. */
}
} }
void FP_FASTAPASS(1) cpuCycle(int a) { void FP_FASTAPASS(1) cpuCycle(int a)
if ((irqControl &0x03) ==0x00) while (a--) clockIRQ(); // Clock IRQ counter on M2 cycles {
if ((irqControl &0x03) ==0x00)
while (a--)
clockIRQ(); /* Clock IRQ counter on M2 cycles */
} }
static DECLFR(readALU_DIP) { static DECLFR(readALU_DIP)
if ((A &0x3FF) ==0 && A !=0x5800) // 5000, 5400, 5C00: read solder pad setting {
if ((A &0x3FF) ==0 && A !=0x5800) /* 5000, 5400, 5C00: read solder pad setting */
return dipSwitch | X.DB &0x3F; return dipSwitch | X.DB &0x3F;
else
if (A &0x800) switch (A &3) { // 5800-5FFF: read ALU if (A &0x800)
case 0: return (mul[0] *mul[1]) &0xFF; switch (A &3)
case 1: return (mul[0] *mul[1]) >>8; {
case 2: return adder; /* 5800-5FFF: read ALU */
case 3: return test; case 0:
return (mul[0] *mul[1]) &0xFF;
case 1:
return (mul[0] *mul[1]) >>8;
case 2:
return adder;
case 3:
return test;
} }
// all others /* all others */
return X.DB; return X.DB;
} }
static DECLFW(writeALU) { static DECLFW(writeALU)
switch (A &3) { {
case 0: mul[0] =V; break; switch (A &3)
case 1: mul[1] =V; break; {
case 2: adder +=V; break; case 0:
case 3: test =V; mul[0] =V;
break;
case 1:
mul[1] =V;
break;
case 2:
adder +=V;
break;
case 3:
test = V;
adder = 0; adder = 0;
break; break;
} }
@@ -226,59 +281,80 @@ static DECLFW(writeNT) {
sync(); sync();
} }
static DECLFW(writeIRQ) { static DECLFW(writeIRQ)
switch (A &7) { {
case 0: irqEnabled =!!(V &1); switch (A &7)
if (!irqEnabled) { {
case 0:
irqEnabled =!!(V &1);
if (!irqEnabled)
{
irqPrescaler =0; irqPrescaler =0;
X6502_IRQEnd(FCEU_IQEXT); X6502_IRQEnd(FCEU_IQEXT);
} }
break; break;
case 1: irqControl =V; case 1:
irqControl =V;
break; break;
case 2: irqEnabled =0; case 2:
irqEnabled =0;
irqPrescaler =0; irqPrescaler =0;
X6502_IRQEnd(FCEU_IQEXT); X6502_IRQEnd(FCEU_IQEXT);
break; break;
case 3: irqEnabled =1; case 3:
irqEnabled =1;
break; break;
case 4: irqPrescaler =V ^irqXor; case 4:
irqPrescaler =V ^irqXor;
break; break;
case 5: irqCounter =V ^irqXor; case 5:
irqCounter =V ^irqXor;
break; break;
case 6: irqXor =V; case 6:
irqXor =V;
break; break;
} }
} }
static DECLFW(writeMode) { static DECLFW(writeMode)
switch (A &3) { {
case 0: mode[0] =V; switch (A &3)
if (!allowExtendedMirroring) mode[0] &=~0x20; {
case 0:
mode[0] =V;
if (!allowExtendedMirroring)
mode[0] &=~0x20;
break; break;
case 1: mode[1] =V; case 1:
if (!allowExtendedMirroring) mode[1] &=~0x08; mode[1] =V;
if (!allowExtendedMirroring)
mode[1] &=~0x08;
break; break;
case 2: mode[2] =V; case 2:
mode[2] =V;
break; break;
case 3: mode[3] =V; case 3:
mode[3] =V;
break; break;
} }
sync(); sync();
} }
static void JYASIC_power(void) { static void JYASIC_power(void)
{
unsigned int i;
SetWriteHandler(0x5000, 0x5FFF, writeALU); SetWriteHandler(0x5000, 0x5FFF, writeALU);
SetWriteHandler(0x6000, 0x7fff, CartBW); SetWriteHandler(0x6000, 0x7fff, CartBW);
SetWriteHandler(0x8000, 0x87FF, writePRG); // 8800-8FFF ignored SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */
SetWriteHandler(0x9000, 0x97FF, writeCHRLow); // 9800-9FFF ignored SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */
SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); // A800-AFFF ignored SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */
SetWriteHandler(0xB000, 0xB7FF, writeNT); // B800-BFFF ignored SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */
SetWriteHandler(0xC000, 0xCFFF, writeIRQ); SetWriteHandler(0xC000, 0xCFFF, writeIRQ);
SetWriteHandler(0xD000, 0xD7FF, writeMode); // D800-DFFF ignored SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */
for (unsigned int i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i); for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i);
SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); // Trap all CPU writes for IRQ clocking purposes SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */
SetReadHandler(0x5000, 0x5FFF, readALU_DIP); SetReadHandler(0x5000, 0x5FFF, readALU_DIP);
SetReadHandler(0x6000, 0xFFFF, CartBR); SetReadHandler(0x6000, 0xFFFF, CartBR);
@@ -295,15 +371,18 @@ static void JYASIC_power(void) {
sync(); sync();
} }
static void JYASIC_reset (void) { static void JYASIC_reset (void)
{
dipSwitch = (dipSwitch +0x40) &0xC0; dipSwitch = (dipSwitch +0x40) &0xC0;
} }
static void JYASIC_restore (int version) { static void JYASIC_restore (int version)
{
sync(); sync();
} }
void JYASIC_init (CartInfo *info) { void JYASIC_init (CartInfo *info)
{
info->Reset = JYASIC_reset; info->Reset = JYASIC_reset;
info->Power = JYASIC_power; info->Power = JYASIC_power;
PPU_hook = trapPPUAddressChange; PPU_hook = trapPPUAddressChange;
@@ -312,164 +391,228 @@ void JYASIC_init (CartInfo *info) {
AddExState(JYASIC_stateRegs, ~0, 0, 0); AddExState(JYASIC_stateRegs, ~0, 0, 0);
GameStateRestore = JYASIC_restore; GameStateRestore = JYASIC_restore;
// WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size /* WRAM is present only in iNES mapper 35, or in mappers with numbers above 255 that require NES 2.0, which explicitly denotes WRAM size */
if (info->iNES2) if (info->iNES2)
WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize; WRAMSIZE =info->PRGRamSize + info->PRGRamSaveSize;
else else
WRAMSIZE =info->mapper ==35? 8192: 0; WRAMSIZE =info->mapper ==35? 8192: 0;
if (WRAMSIZE) { if (WRAMSIZE)
{
WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE); WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1); SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM); FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
} }
} }
static void syncSingleCart (void) { static void syncSingleCart (void)
{
syncPRG(0x3F, mode[3] <<5 &~0x3F); syncPRG(0x3F, mode[3] <<5 &~0x3F);
if (mode[3] &0x20) { if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<6 &0x600); syncCHR(0x1FF, mode[3] <<6 &0x600);
syncNT (0x1FF, mode[3] <<6 &0x600); syncNT (0x1FF, mode[3] <<6 &0x600);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
} }
} }
void Mapper35_Init(CartInfo *info) { // Basically mapper 90/209/211 with WRAM void Mapper35_Init(CartInfo *info)
{
/* Basically mapper 90/209/211 with WRAM */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =syncSingleCart; sync =syncSingleCart;
JYASIC_init(info); JYASIC_init(info);
} }
void Mapper90_Init(CartInfo *info) { // Single cart, extended mirroring and ROM nametables disabled void Mapper90_Init(CartInfo *info)
{
/* Single cart, extended mirroring and ROM nametables disabled */
allowExtendedMirroring =0; allowExtendedMirroring =0;
sync =syncSingleCart; sync =syncSingleCart;
JYASIC_init(info); JYASIC_init(info);
} }
void Mapper209_Init(CartInfo *info) { // Single cart, extended mirroring and ROM nametables enabled
allowExtendedMirroring =1; void Mapper209_Init(CartInfo *info)
sync =syncSingleCart; {
JYASIC_init(info); /* Single cart, extended mirroring and ROM nametables enabled */
}
void Mapper211_Init(CartInfo *info) { // Duplicate of mapper 209
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =syncSingleCart; sync =syncSingleCart;
JYASIC_init(info); JYASIC_init(info);
} }
static void sync281 (void) { void Mapper211_Init(CartInfo *info)
{
/* Duplicate of mapper 209 */
allowExtendedMirroring =1;
sync =syncSingleCart;
JYASIC_init(info);
}
static void sync281 (void)
{
syncPRG(0x1F, mode[3] <<5); syncPRG(0x1F, mode[3] <<5);
syncCHR(0xFF, mode[3] <<8); syncCHR(0xFF, mode[3] <<8);
syncNT (0xFF, mode[3] <<8); syncNT (0xFF, mode[3] <<8);
} }
void Mapper281_Init(CartInfo *info) { // Multicart
void Mapper281_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync281; sync =sync281;
JYASIC_init(info); JYASIC_init(info);
} }
static void sync282 (void) { static void sync282 (void)
{
syncPRG(0x1F, mode[3] <<4 &~0x1F); syncPRG(0x1F, mode[3] <<4 &~0x1F);
if (mode[3] &0x20) { if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<6 &0x600); syncCHR(0x1FF, mode[3] <<6 &0x600);
syncNT (0x1FF, mode[3] <<6 &0x600); syncNT (0x1FF, mode[3] <<6 &0x600);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<6 &0x600);
} }
} }
void Mapper282_Init(CartInfo *info) { // Multicart
void Mapper282_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync282; sync =sync282;
JYASIC_init(info); JYASIC_init(info);
} }
void sync295 (void) { void sync295 (void)
{
syncPRG(0x0F, mode[3] <<4); syncPRG(0x0F, mode[3] <<4);
syncCHR(0x7F, mode[3] <<7); syncCHR(0x7F, mode[3] <<7);
syncNT (0x7F, mode[3] <<7); syncNT (0x7F, mode[3] <<7);
} }
void Mapper295_Init(CartInfo *info) { // Multicart
void Mapper295_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync295; sync =sync295;
JYASIC_init(info); JYASIC_init(info);
} }
void sync358 (void) { void sync358 (void)
{
syncPRG(0x1F, mode[3] <<4 &~0x1F); syncPRG(0x1F, mode[3] <<4 &~0x1F);
if (mode[3] &0x20) { if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<7 &0x600); syncCHR(0x1FF, mode[3] <<7 &0x600);
syncNT (0x1FF, mode[3] <<7 &0x600); syncNT (0x1FF, mode[3] <<7 &0x600);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
} }
} }
void Mapper358_Init(CartInfo *info) { // Multicart
void Mapper358_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync358; sync =sync358;
JYASIC_init(info); JYASIC_init(info);
} }
void sync386 (void) { void sync386 (void)
{
syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40); syncPRG(0x1F, mode[3] <<4 &0x20 | mode[3] <<3 &0x40);
if (mode[3] &0x20) { if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<7 &0x600); syncCHR(0x1FF, mode[3] <<7 &0x600);
syncNT (0x1FF, mode[3] <<7 &0x600); syncNT (0x1FF, mode[3] <<7 &0x600);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
} }
} }
void Mapper386_Init(CartInfo *info) { // Multicart
void Mapper386_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync386; sync =sync386;
JYASIC_init(info); JYASIC_init(info);
} }
void sync387 (void) { void sync387(void)
{
syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20); syncPRG(0x0F, mode[3] <<3 &0x10 | mode[3] <<2 &0x20);
if (mode[3] &0x20) { if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<7 &0x600); syncCHR(0x1FF, mode[3] <<7 &0x600);
syncNT (0x1FF, mode[3] <<7 &0x600); syncNT (0x1FF, mode[3] <<7 &0x600);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<7 &0x600);
} }
} }
void Mapper387_Init(CartInfo *info) { // Multicart
void Mapper387_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync387; sync =sync387;
JYASIC_init(info); JYASIC_init(info);
} }
void sync388 (void) { void sync388 (void)
{
syncPRG(0x1F, mode[3] <<3 &0x60); syncPRG(0x1F, mode[3] <<3 &0x60);
if (mode[3] &0x20) {
if (mode[3] &0x20)
{
syncCHR(0x1FF, mode[3] <<8 &0x200); syncCHR(0x1FF, mode[3] <<8 &0x200);
syncNT (0x1FF, mode[3] <<8 &0x200); syncNT (0x1FF, mode[3] <<8 &0x200);
} else { }
else
{
syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200); syncCHR(0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200); syncNT (0x0FF, mode[3] <<8 &0x100 | mode[3] <<8 &0x200);
} }
} }
void Mapper388_Init(CartInfo *info) { // Multicart
void Mapper388_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =0; allowExtendedMirroring =0;
sync =sync388; sync =sync388;
JYASIC_init(info); JYASIC_init(info);
} }
void sync397 (void) { void sync397 (void)
{
syncPRG(0x1F, mode[3] <<4 &~0x1F); syncPRG(0x1F, mode[3] <<4 &~0x1F);
syncCHR(0x7F, mode[3] <<7); syncCHR(0x7F, mode[3] <<7);
syncNT (0x7F, mode[3] <<7); syncNT (0x7F, mode[3] <<7);
} }
void Mapper397_Init(CartInfo *info) { // Multicart
void Mapper397_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync397; sync =sync397;
JYASIC_init(info); JYASIC_init(info);
} }
void sync421 (void) { void sync421 (void)
{
if (mode[3] &0x04) if (mode[3] &0x04)
syncPRG(0x3F, mode[3] <<4 &~0x3F); syncPRG(0x3F, mode[3] <<4 &~0x3F);
else else
@@ -477,7 +620,10 @@ void sync421 (void) {
syncCHR(0x1FF, mode[3] <<8 &0x300); syncCHR(0x1FF, mode[3] <<8 &0x300);
syncNT (0x1FF, mode[3] <<8 &0x300); syncNT (0x1FF, mode[3] <<8 &0x300);
} }
void Mapper421_Init(CartInfo *info) { // Multicart
void Mapper421_Init(CartInfo *info)
{
/* Multicart */
allowExtendedMirroring =1; allowExtendedMirroring =1;
sync =sync421; sync =sync421;
JYASIC_init(info); JYASIC_init(info);