Initial commit - http://sourceforge.net/p/fceumm/code/160/
This commit is contained in:
203
src/boards/fk23c.c
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203
src/boards/fk23c.c
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2006 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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static uint8 unromchr;
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static uint32 dipswitch = 0;
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static uint8 *CHRRAM = NULL;
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static uint32 CHRRAMSize;
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static void BMCFK23CCW(uint32 A, uint8 V) {
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if (EXPREGS[0] & 0x40)
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setchr8(EXPREGS[2] | unromchr);
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else if (EXPREGS[0] & 0x20) {
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setchr1r(0x10, A, V);
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} else {
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uint16 base = (EXPREGS[2] & 0x7F) << 3;
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if (EXPREGS[3] & 2) {
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int cbase = (MMC3_cmd & 0x80) << 5;
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setchr1(A, V | base);
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setchr1(0x0000 ^ cbase, DRegBuf[0] | base);
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setchr1(0x0400 ^ cbase, EXPREGS[6] | base);
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setchr1(0x0800 ^ cbase, DRegBuf[1] | base);
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setchr1(0x0c00 ^ cbase, EXPREGS[7] | base);
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} else
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setchr1(A, V | base);
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}
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}
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static void BMCFK23CPW(uint32 A, uint8 V) {
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uint32 bank = (EXPREGS[1] & 0x1F);
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uint32 hiblock = ((EXPREGS[0] & 8) << 4) | ((EXPREGS[0] & 0x80) << 1) | (UNIFchrrama ? ((EXPREGS[2] & 0x40) << 3) : 0);
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uint32 block = (EXPREGS[1] & 0x60) | hiblock;
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uint32 extra = (EXPREGS[3] & 2);
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switch (EXPREGS[0] & 7) {
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case 0:
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setprg8(A, (block << 1) | (V & 0x3F));
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if (extra) {
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setprg8(0xC000, EXPREGS[4]);
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setprg8(0xE000, EXPREGS[5]);
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}
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break;
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case 1:
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setprg8(A, ((hiblock | (EXPREGS[1] & 0x70)) << 1) | (V & 0x1F));
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if (extra) {
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setprg8(0xC000, EXPREGS[4]);
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setprg8(0xE000, EXPREGS[5]);
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}
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break;
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case 2:
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setprg8(A, ((hiblock | (EXPREGS[1] & 0x78)) << 1) | (V & 0x0F));
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if (extra) {
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setprg8(0xC000, EXPREGS[4]);
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setprg8(0xE000, EXPREGS[5]);
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}
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break;
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case 3:
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setprg16(0x8000, (bank | block));
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setprg16(0xC000, (bank | block));
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break;
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case 4:
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setprg32(0x8000, (bank | block) >> 1);
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break;
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}
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setprg8r(0x10, 0x6000, A001B & 3);
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}
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static DECLFW(BMCFK23CHiWrite) {
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if (EXPREGS[0] & 0x40) {
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if (EXPREGS[0] & 0x30)
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unromchr = 0;
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else {
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unromchr = V & 3;
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FixMMC3CHR(MMC3_cmd);
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}
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} else {
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if ((A == 0x8001) && (EXPREGS[3] & 2) && (MMC3_cmd & 8)) {
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EXPREGS[4 | (MMC3_cmd & 3)] = V;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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} else
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if (A < 0xC000) {
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if (UNIFchrrama) { // hacky... strange behaviour, must be bit scramble due to pcb layot restrictions
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// check if it not interfer with other dumps
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if ((A == 0x8000) && (V == 0x46))
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V = 0x47;
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else if ((A == 0x8000) && (V == 0x47))
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V = 0x46;
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}
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MMC3_CMDWrite(A, V);
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FixMMC3PRG(MMC3_cmd);
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} else
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MMC3_IRQWrite(A, V);
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}
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}
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static DECLFW(BMCFK23CWrite) {
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// FCEU_printf("lo %04x:%02x\n",A,V);
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if (dipswitch) { // íóëåâîé äèï áåðåò ëþáûå çàïèñè ïî äåôîëòó, äàëüøå èäåò âûáîð
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if (A & (1 << (dipswitch + 3))) {
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EXPREGS[A & 3] = V;
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// FCEU_printf(" reg %d set!\n",A&3);
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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} else {
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EXPREGS[A & 3] = V;
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// FCEU_printf(" reg %d set!\n",A&3);
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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if (EXPREGS[3] & 2)
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EXPREGS[0] &= ~7; // hacky hacky! if someone wants extra banking, then for sure doesn't want mode 4 for it! (allow to run A version boards on normal mapper)
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}
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static void BMCFK23CReset(void) {
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if (dipswitch <= 8)
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dipswitch++;
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else
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dipswitch = 0;
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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EXPREGS[4] = EXPREGS[5] = EXPREGS[6] = EXPREGS[7] = 0xFF;
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MMC3RegReset();
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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static void BMCFK23CPower(void) {
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GenMMC3Power();
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EXPREGS[0] = 4;
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EXPREGS[1] = 0xFF;
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EXPREGS[2] = EXPREGS[3] = 0;
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dipswitch = 0;
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EXPREGS[4] = EXPREGS[5] = EXPREGS[6] = EXPREGS[7] = 0xFF;
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SetWriteHandler(0x5000, 0x5fff, BMCFK23CWrite);
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SetWriteHandler(0x8000, 0xFFFF, BMCFK23CHiWrite);
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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static void BMCFK23CAPower(void) {
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GenMMC3Power();
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dipswitch = 0;
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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EXPREGS[4] = EXPREGS[5] = EXPREGS[6] = EXPREGS[7] = 0xFF;
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SetWriteHandler(0x5000, 0x5fff, BMCFK23CWrite);
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SetWriteHandler(0x8000, 0xFFFF, BMCFK23CHiWrite);
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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static void BMCFK23CAClose(void) {
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if (CHRRAM)
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FCEU_gfree(CHRRAM);
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CHRRAM = NULL;
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}
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void BMCFK23C_Init(CartInfo *info) {
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GenMMC3_Init(info, 512, 256, 128, 0);
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cwrap = BMCFK23CCW;
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pwrap = BMCFK23CPW;
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info->Power = BMCFK23CPower;
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info->Reset = BMCFK23CReset;
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AddExState(EXPREGS, 8, 0, "EXPR");
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AddExState(&unromchr, 1, 0, "UCHR");
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AddExState(&dipswitch, 1, 0, "DPSW");
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}
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void BMCFK23CA_Init(CartInfo *info) {
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GenMMC3_Init(info, 512, 256, 128, 0);
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cwrap = BMCFK23CCW;
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pwrap = BMCFK23CPW;
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info->Power = BMCFK23CAPower;
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info->Reset = BMCFK23CReset;
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info->Close = BMCFK23CAClose;
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CHRRAMSize = 8192;
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CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSize);
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SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSize, 1);
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AddExState(CHRRAM, CHRRAMSize, 0, "CRAM");
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AddExState(EXPREGS, 8, 0, "EXPR");
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AddExState(&unromchr, 1, 0, "UCHR");
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AddExState(&dipswitch, 1, 0, "DPSW");
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}
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