Initial commit - http://sourceforge.net/p/fceumm/code/160/
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twinaphex
355
src/boards/copyfami_emu.c
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355
src/boards/copyfami_emu.c
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2011 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifdef COPYFAMI
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#include "__serial.h"
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#include "mapinc.h"
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#include "mmc3.h"
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//#define DEBUG_SERIAL
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// *** COPY FAMICOM EMULATION ***
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/*
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$0000-$1FFF
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$2000-$200F PPU
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$2010-$3FFB
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$3FFC-$3FFF
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$4000-$7FFF APU /
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$8000-$FFF9 CART/ROM
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$FFFA-$FFFB CART/ NMI
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$FFFE-$FFFF CART/ IRQ
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CTRL R/W $3FFC ---aenic ($00 at reset)
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c -
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0 -
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1 -
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i - IRQ
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0 -
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1 -
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n - NMI
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0 -
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1 -
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e - NMI
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0 -
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1 -
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a - AROM
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0 -
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1 -
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BANK R/W $3FFD ---mbbbb
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b -
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m - ROM
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USBDATA R/W $3FFE dddddddd
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d - /
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STATUS R $3FFF vmnicptr
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r - USB
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0 -
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1 -
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t - USB
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0 -
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1 -
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p - USB
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0 -
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1 -
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c -
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0 -
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1 -
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i - IRQ
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0 -
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1 -
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n - NMI
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0 -
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1 -
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m - 10 VRAM ()
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v - VRAM
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0 -
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1 -
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AROM
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VRAM
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8000-FFFF
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*/
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#define CTRL 0x00
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#define CCART 0x01
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#define CVIRQ 0x02
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#define CVNMI 0x04
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#define CDNMI 0x08
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#define CAROM 0x10
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#define BANK 0x01
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#define BMIRR 0x10
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#define USB 0x02
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#define STATUS 0x03
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#define SRX 0x01
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#define STX 0x02
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#define SPEN 0x04
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#define SCART 0x08
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#define SIRQ 0x10
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#define SNMI 0x20
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#define SA10 0x40
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#define SVRAM 0x80
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#ifdef DEBUG_SERIAL
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static uint8 debug_serial_data[] = {
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0xDE, 0xAD, 0xBE, 0xEF, 0x00,
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0xDE, 0xAD, 0xBE, 0xEF, 0x01,
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0x02,
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0x14, 0x50, 0xB0,
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0x02,
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0x14, 0x50, 0xB0,
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0x02,
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};
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static uint32 debug_serial_data_size = sizeof(debug_serial_data);
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static uint32 debug_serial_data_pos;
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#endif
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static uint8 *CHRRAM = NULL;
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static uint32 CHRRAMSIZE;
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static uint8 regs[4];
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static readfunc def_read_ram, def_read_rom;
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static writefunc def_write_ram;
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static SFORMAT StateRegs[] =
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{
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{ regs, 4, "CREGS" },
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{ 0 }
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};
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static void Sync() {
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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static void MCopyFamiMMC3PW(uint32 A, uint8 V) {
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if (regs[CTRL] & CCART)
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setprg8(A, V);
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else
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setprg32r(1, 0x8000, (regs[BANK] & 0x0F) ^ 0x08);
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}
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static void MCopyFamiMMC3CW(uint32 A, uint8 V) {
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if ((regs[STATUS] & SCART) && (regs[CTRL] & CAROM))
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setchr8r(0x10, 0);
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else
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setchr1r(0, A, V);
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}
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static void MCopyFamiMMC3MW(uint8 V) {
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if (regs[CTRL] & CAROM) {
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setmirror(MI_0 + ((regs[BANK] >> 4) & 1));
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} else {
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A000B = V;
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setmirror((V & 1) ^ 1);
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}
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}
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static uint32 direction = 0xffffffff;
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static uint32 bytes_count = 0;
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static DECLFW(MCopyFamiWriteReg) {
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if (((A & 3) == USB) && !fceuindbg) {
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if (direction != 0) {
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direction = 0;
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bytes_count = 0;
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FCEU_printf(" >");
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}
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#ifndef DEBUG_SERIAL
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while (!SerialSendChar(V)) {
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}
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;
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#endif
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bytes_count++;
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// FCEU_printf(" %02X",V);
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} else {
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regs[A & 3] = V;
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Sync();
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}
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}
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static DECLFR(MCopyFamiReadReg) {
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#ifdef DEBUG_SERIAL
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if (debug_serial_data_pos == debug_serial_data_size)
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regs[STATUS] |= SRX;
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else
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regs[STATUS] &= ~SRX;
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#endif
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if (!fceuindbg) {
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#ifndef DEBUG_SERIAL
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if ((A & 3) == STATUS) {
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int data;
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if ((data = SerialGetChar()) == EOF)
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regs[STATUS] |= SRX;
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else
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regs[STATUS] &= ~SRX;
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regs[USB] = data & 0xff;
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} else
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#endif
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if ((A & 3) == USB) {
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#ifdef DEBUG_SERIAL
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regs[USB] = debug_serial_data[debug_serial_data_pos++];
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#endif
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if (direction != 1) {
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if (direction != 0xffffffff) FCEU_printf(" bytes sent: %08x", bytes_count);
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direction = 1;
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bytes_count = 0;
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FCEU_printf("\n<");
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}
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FCEU_printf(" %02X", regs[USB]);
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}
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}
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return regs[A & 3];
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}
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static DECLFW(MCopyFamiMMC3Write) {
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if (regs[CTRL] & CAROM) {
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regs[BANK] = V & 0x1F;
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Sync();
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} else {
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if (A >= 0xC000)
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MMC3_IRQWrite(A, V);
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else
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MMC3_CMDWrite(A, V);
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}
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}
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static DECLFW(MCopyFamiMMC3WriteNMI) {
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if (regs[CTRL] & CVNMI)
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def_write_ram(0x3FFC + (A & 1), V);
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else
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MCopyFamiMMC3Write(A, V);
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}
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static DECLFW(MCopyFamiMMC3WriteIRQ) {
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if (regs[CTRL] & CVIRQ)
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def_write_ram(0x3FFE + (A & 1), V);
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else
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MCopyFamiMMC3Write(A, V);
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}
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static DECLFR(MCopyFamiReadNMI) {
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if (regs[CTRL] & CVNMI)
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return def_read_ram(0x3FFC + (A & 1));
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else
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return def_read_rom(A);
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}
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static DECLFR(MCopyFamiReadIRQ) {
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if (regs[CTRL] & CVIRQ)
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return def_read_ram(0x3FFE + (A & 1));
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else
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return def_read_rom(A);
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}
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static void MCopyFamiMMC3Power(void) {
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regs[CTRL] = regs[USB] = 0;
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regs[STATUS] = SIRQ | SNMI | SVRAM;
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regs[BANK] = 0x08;
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#ifdef DEBUG_SERIAL
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debug_serial_data_pos = 0;
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#endif
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GenMMC3Power();
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Sync();
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def_write_ram = GetWriteHandler(0x3FFC);
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SetWriteHandler(0x3FFC, 0x3FFF, MCopyFamiWriteReg);
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def_read_ram = GetReadHandler(0x3FFC);
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SetReadHandler(0x3FFC, 0x3FFF, MCopyFamiReadReg);
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SetWriteHandler(0x8000, 0xFFF9, MCopyFamiMMC3Write);
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SetWriteHandler(0xFFFA, 0xFFFB, MCopyFamiMMC3WriteNMI);
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SetWriteHandler(0xFFFE, 0xFFFF, MCopyFamiMMC3WriteIRQ);
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def_read_rom = GetReadHandler(0xFFFA);
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SetReadHandler(0xFFFA, 0xFFFB, MCopyFamiReadNMI);
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SetReadHandler(0xFFFE, 0xFFFF, MCopyFamiReadIRQ);
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}
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static void MCopyFamiMMC3Reset(void) {
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regs[CTRL] = regs[USB] = 0;
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regs[STATUS] = SIRQ | SNMI | SVRAM;
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regs[BANK] = 0x08;
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#ifdef DEBUG_SERIAL
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debug_serial_data_pos = 0;
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#endif
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MMC3RegReset();
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Sync();
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}
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static void MCopyFamiClose(void) {
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if (CHRRAM)
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FCEU_gfree(CHRRAM);
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CHRRAM = NULL;
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SerialClose();
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}
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static void StateRestore(int version) {
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Sync();
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}
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void MapperCopyFamiMMC3_Init(CartInfo *info) {
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GenMMC3_Init(info, 512, 512, 8, 0);
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cwrap = MCopyFamiMMC3CW;
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pwrap = MCopyFamiMMC3PW;
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mwrap = MCopyFamiMMC3MW;
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info->Reset = MCopyFamiMMC3Reset;
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info->Power = MCopyFamiMMC3Power;
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info->Close = MCopyFamiClose;
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GameStateRestore = StateRestore;
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CHRRAMSIZE = 8192;
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CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE);
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SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1);
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AddExState(CHRRAM, CHRRAMSIZE, 0, "CRAM");
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#ifndef DEBUG_SERIAL
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FCEU_printf("WAITING FOR PORT...\n");
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while (!SerialOpen(20, 921600)) {
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}
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FCEU_printf("PORT READY.\n");
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#endif
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AddExState(&StateRegs, ~0, 0, 0);
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}
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#endif
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