Rewrite mapper 398 to use modular VRC2/4 emulation; initialize VRC2/4 registers on power-on.
This commit is contained in:
NewRisingSun
committed by
LibretroAdmin
LibretroAdmin
parent
74170b9efb
commit
77e5efca21
183
src/boards/398.c
183
src/boards/398.c
@@ -1,7 +1,7 @@
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/* FCE Ultra - NES/Famicom Emulator
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/* FCE Ultra - NES/Famicom Emulator
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*
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*
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* Copyright notice for this file:
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* Copyright notice for this file:
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* Copyright (C) 2023
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* Copyright (C) 2025 NewRisingSun
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@@ -18,168 +18,47 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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/* NES 2.0 Mapper 398 - PCB YY840820C
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* 1995 Super HiK 5-in-1 - 新系列米奇老鼠組合卡 (JY-048)
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*/
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#include "mapinc.h"
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#include "mapinc.h"
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#include "vrc2and4.h"
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static uint8 latch;
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static uint8 reg;
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static uint8 PPUCHRBus;
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static uint8 vrc4Prg[2];
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static uint8 vrc4Mirr;
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static uint8 vrc4Misc;
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static uint16 vrc4Chr[8];
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static uint8 vrc4IRQLatch;
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static uint8 vrc4IRQa;
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static uint8 vrc4IRQCount;
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static int16 vrc4IRQCycles;
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static SFORMAT StateRegs[] = {
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static SFORMAT Mapper398_stateRegs[] ={
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{ &latch, 1, "GAME" },
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{ ®, 1, "EXP0" },
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{ &PPUCHRBus, 1, "CHRB" },
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{ 0 }
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{ vrc4Prg, 2, "V4PR" },
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{ &vrc4Mirr, 1, "V4MI" },
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{ &vrc4Misc, 1, "V4MS" },
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{ vrc4Chr, 16, "V4CH" },
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{ &vrc4IRQLatch, 1, "VILA" },
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{ &vrc4IRQa, 1, "VIMO" },
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{ &vrc4IRQCount, 1, "VICO" },
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{ &vrc4IRQCycles, 2, "VICY" },
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{ 0 },
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};
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};
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static void Sync(void) {
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static void sync () {
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if (latch & 0x80) {
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if (reg &0x80) {
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/* GNROM-like */
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setprg32(0x8000, reg >>5 &6 | VRC24_chr[0] >>2 &1);
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setprg32(0x8000, ((latch >> 5) & 0x06) | ((vrc4Chr[PPUCHRBus] >> 2) & 0x01));
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setchr8(0x40 | reg >>3 &8 | VRC24_chr[0] &7);
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setchr8(0x40 | ((latch >> 3) & 0x08) | (vrc4Chr[PPUCHRBus] & 0x07));
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} else {
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} else {
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uint32 cbase = (vrc4Misc << 13) & 0x4000;
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VRC24_syncPRG(0x0F, 0x00);
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VRC24_syncCHR(0x1FF, 0x000);
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setprg8(0x8000 ^ cbase, (vrc4Prg[0] & 0x0F));
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setprg8(0xA000, (vrc4Prg[1] & 0x0F));
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setprg8(0xC000 ^ cbase, ((~1) & 0x0F));
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setprg8(0xE000, ((~0) & 0x0F));
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setchr1(0x0000, (vrc4Chr[0] & 0x1FF));
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setchr1(0x0400, (vrc4Chr[1] & 0x1FF));
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setchr1(0x0800, (vrc4Chr[2] & 0x1FF));
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setchr1(0x0C00, (vrc4Chr[3] & 0x1FF));
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setchr1(0x1000, (vrc4Chr[4] & 0x1FF));
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setchr1(0x1400, (vrc4Chr[5] & 0x1FF));
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setchr1(0x1800, (vrc4Chr[6] & 0x1FF));
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setchr1(0x1C00, (vrc4Chr[7] & 0x1FF));
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}
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switch (vrc4Mirr & 0x03) {
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case 0: setmirror(MI_V); break;
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case 1: setmirror(MI_H); break;
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case 2: setmirror(MI_0); break;
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case 3: setmirror(MI_1); break;
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}
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}
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VRC24_syncMirror();
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}
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}
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static DECLFW(writeVRC4) {
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DECLFW(Mapper398_writeReg) {
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uint8 index;
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reg =A &0xFF;
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latch = A & 0xFF;
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VRC24_Sync();
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A &= 0xF003;
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VRC24_writeReg(A, V);
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switch (A & 0xF000) {
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case 0x8000:
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case 0xA000:
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vrc4Prg[(A >> 13) & 1] = V;
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break;
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case 0x9000:
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if (~A & 2) {
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vrc4Mirr = V;
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} else if (~A & 1) {
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vrc4Misc = V;
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}
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break;
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case 0xF000:
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switch (A & 3) {
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case 0: vrc4IRQLatch = (vrc4IRQLatch & 0xF0) | (V & 0x0F); break;
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case 1: vrc4IRQLatch = (vrc4IRQLatch & 0x0F) | (V << 4); break;
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case 2:
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vrc4IRQa = V;
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if (vrc4IRQa & 0x02) {
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vrc4IRQCount = vrc4IRQLatch;
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vrc4IRQCycles = 341;
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 3:
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vrc4IRQa = (vrc4IRQa & ~0x02) | ((vrc4IRQa << 1) & 0x02);
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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}
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break;
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default:
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index = ((A - 0xB000) >> 11) | ((A >> 1) & 1);
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if (A & 1) {
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vrc4Chr[index] = (vrc4Chr[index] & 0x0F) | (V << 4);
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} else {
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vrc4Chr[index] = (vrc4Chr[index] & ~0x0F) | (V & 0x0F);
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}
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break;
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}
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Sync();
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}
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}
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static void FP_FASTAPASS(1) M398CPUHook(int a) {
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void Mapper398_power(void) {
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int count = a;
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reg =0xC0;
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while (count--) {
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VRC24_power();
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if ((vrc4IRQa & 0x02) && ((vrc4IRQa & 0x04) || ((vrc4IRQCycles -= 3) <= 0))) {
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SetWriteHandler(0x8000, 0xFFFF, Mapper398_writeReg);
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if (~vrc4IRQa & 0x04) {
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vrc4IRQCycles += 341;
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}
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if (!++vrc4IRQCount) {
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vrc4IRQCount = vrc4IRQLatch;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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}
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}
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}
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static void FP_FASTAPASS(1) M398PPUHook(uint32 A) {
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void Mapper398_reset(void) {
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uint8 bank = (A & 0x1FFF) >> 10;
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reg =0xC0;
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if ((PPUCHRBus != bank) && ((A & 0x3000) != 0x2000)) {
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VRC24_Sync();
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PPUCHRBus = bank;
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}
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Sync();
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}
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void Mapper398_Init (CartInfo *info) {
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}
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VRC24_init(info, sync, 0x01, 0x02, 1, 1, 0);
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info->Power =Mapper398_power;
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static void M398Reset(void) {
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info->Reset =Mapper398_reset;
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latch = 0xC0;
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AddExState(Mapper398_stateRegs, ~0, 0, 0);
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Sync();
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}
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static void M398Power(void) {
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int i;
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for (i = 0; i < 2; i++)
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vrc4Prg[i] = 0;
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for (i = 0; i < 8; i++)
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vrc4Chr[i] = 0;
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vrc4Mirr = vrc4Misc = vrc4IRQLatch = vrc4IRQa = vrc4IRQCount = vrc4IRQCycles = 0;
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PPUCHRBus = 0;
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latch = 0xC0;
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Sync();
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetWriteHandler(0x8000, 0xFFFF, writeVRC4);
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}
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static void StateRestore(int version) {
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Sync();
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}
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void Mapper398_Init(CartInfo *info) {
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info->Reset = M398Reset;
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info->Power = M398Power;
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MapIRQHook = M398CPUHook;
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PPU_hook = M398PPUHook;
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GameStateRestore = StateRestore;
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AddExState(StateRegs, ~0, 0, 0);
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}
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}
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@@ -188,6 +188,9 @@ void FP_FASTAPASS(1) VRC4_cpuCycle(int a) {
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}
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}
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void VRC24_power(void) {
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void VRC24_power(void) {
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VRC24_prg[0] =0; VRC24_prg[1] =0;
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VRC24_chr[0] =0; VRC24_chr[1] =1; VRC24_chr[2] =2; VRC24_chr[3] =3; VRC24_chr[4] =4; VRC24_chr[5] =5; VRC24_chr[6] =6; VRC24_chr[7] =7;
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VRC24_mirroring =VRC24_misc =VRC2_pins =VRC4_latch =VRC4_mode =VRC4_count =VRC4_cycles =0;
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SetReadHandler(0x6000, 0x7FFF, VRC24_wramRead);
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SetReadHandler(0x6000, 0x7FFF, VRC24_wramRead);
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SetWriteHandler(0x6000, 0x7FFF, VRC24_wramWrite);
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SetWriteHandler(0x6000, 0x7FFF, VRC24_wramWrite);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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SetReadHandler(0x8000, 0xFFFF, CartBR);
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