diff --git a/src/boards/jyasic.c b/src/boards/jyasic.c index 0d1cdf1..cfc1b3b 100644 --- a/src/boards/jyasic.c +++ b/src/boards/jyasic.c @@ -21,6 +21,7 @@ */ #include "mapinc.h" +#include "mmc3.h" void (*sync)(void); static uint8 allowExtendedMirroring; @@ -45,6 +46,7 @@ static uint8 adder; static uint8 test; static uint8 dipSwitch; +static uint8 cpuWriteHandlersSet; static writefunc cpuWriteHandlers[0x10000]; /* Actual write handlers for CPU write trapping as a method fo IRQ clocking */ static SFORMAT JYASIC_stateRegs[] = { @@ -373,6 +375,16 @@ static DECLFW(writeMode) sync(); } +static void JYASIC_restoreWriteHandlers(void) +{ + int i; + if (cpuWriteHandlersSet) + { + for (i =0; i <0x10000; i++) SetWriteHandler(i, i, cpuWriteHandlers[i]); + cpuWriteHandlersSet =0; + } +} + static void JYASIC_power(void) { unsigned int i; @@ -386,8 +398,10 @@ static void JYASIC_power(void) SetWriteHandler(0xC000, 0xCFFF, writeIRQ); SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */ + JYASIC_restoreWriteHandlers(); for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i); SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */ + cpuWriteHandlersSet =1; SetReadHandler(0x5000, 0x5FFF, readALU_DIP); SetReadHandler(0x6000, 0xFFFF, CartBR); @@ -423,6 +437,7 @@ static void JYASIC_restore (int version) void JYASIC_init (CartInfo *info) { + cpuWriteHandlersSet =0; info->Reset = JYASIC_reset; info->Power = JYASIC_power; info->Close = JYASIC_close; @@ -669,3 +684,114 @@ void Mapper421_Init(CartInfo *info) sync =sync421; JYASIC_init(info); } + +/* Mapper 394: HSK007 circuit board that can simulate J.Y. ASIC, MMC3, and NROM. */ +static uint8 HSK007Reg[4]; +void sync394 (void) /* Called when J.Y. ASIC is active */ +{ + int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F; + int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F; + int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020; + int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100; + syncPRG(0x1F, prgOR); + syncCHR(0xFF, chrOR); + syncNT (0xFF, chrOR); +} +static void Mapper394_PWrap(uint32 A, uint8 V) +{ + int prgAND =HSK007Reg[3] &0x10? 0x1F: 0x0F; + int prgOR =HSK007Reg[3] <<1 &0x010 | HSK007Reg[1] <<5 &0x020; + if (HSK007Reg[1] &0x08) + setprg8(A, V &prgAND | prgOR &~prgAND); + else + if (A ==0x8000) + setprg32(A, (prgOR | HSK007Reg[3] <<1 &0x0F) >>2); + +} +static void Mapper394_CWrap(uint32 A, uint8 V) +{ + int chrAND =HSK007Reg[3] &0x80? 0xFF: 0x7F; + int chrOR =HSK007Reg[3] <<1 &0x080 | HSK007Reg[1] <<8 &0x100; + setchr1(A, V &chrAND | chrOR &~chrAND); +} +static DECLFW(Mapper394_Write) +{ + uint8 oldMode =HSK007Reg[1]; + A &=3; + HSK007Reg[A] =V; + if (A ==1) + { + if (~oldMode &0x10 && V &0x10) JYASIC_power(); + if ( oldMode &0x10 && ~V &0x10) + { + JYASIC_restoreWriteHandlers(); + GenMMC3Power(); + } + } + else + { + if (HSK007Reg[1] &0x10) + sync(); + else + { + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } + + } +} +static void Mapper394_restore (int version) +{ + int i; + JYASIC_restoreWriteHandlers(); + if (HSK007Reg[1] &0x10) + { + SetWriteHandler(0x5000, 0x5FFF, writeALU); + SetWriteHandler(0x6000, 0x7fff, CartBW); + SetWriteHandler(0x8000, 0x87FF, writePRG); /* 8800-8FFF ignored */ + SetWriteHandler(0x9000, 0x97FF, writeCHRLow); /* 9800-9FFF ignored */ + SetWriteHandler(0xA000, 0xA7FF, writeCHRHigh); /* A800-AFFF ignored */ + SetWriteHandler(0xB000, 0xB7FF, writeNT); /* B800-BFFF ignored */ + SetWriteHandler(0xC000, 0xCFFF, writeIRQ); + SetWriteHandler(0xD000, 0xD7FF, writeMode); /* D800-DFFF ignored */ + + for (i =0; i <0x10000; i++) cpuWriteHandlers[i] =GetWriteHandler(i); + SetWriteHandler(0x0000, 0xFFFF, trapCPUWrite); /* Trap all CPU writes for IRQ clocking purposes */ + cpuWriteHandlersSet =1; + + SetReadHandler(0x5000, 0x5FFF, readALU_DIP); + SetReadHandler(0x6000, 0xFFFF, CartBR); + sync(); + } + else + { + SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite); + SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite); + SetReadHandler(0x8000, 0xFFFF, CartBR); + FixMMC3PRG(MMC3_cmd); + FixMMC3CHR(MMC3_cmd); + } +} +static void Mapper394_power(void) +{ + HSK007Reg[0] =0x00; + HSK007Reg[1] =0x0F; + HSK007Reg[2] =0x00; + HSK007Reg[3] =0x10; + GenMMC3Power(); + SetWriteHandler(0x5000, 0x5FFF, Mapper394_Write); +} + +void Mapper394_Init(CartInfo *info) +{ + allowExtendedMirroring =1; + sync =sync394; + JYASIC_init(info); + GenMMC3_Init(info, 128, 128, 0, 0); + pwrap =Mapper394_PWrap; + cwrap =Mapper394_CWrap; + info->Reset = Mapper394_power; + info->Power = Mapper394_power; + AddExState(HSK007Reg, 4, 0, "HSK "); + GameStateRestore = Mapper394_restore; +} diff --git a/src/ines.c b/src/ines.c index 97ddef7..bdd384a 100644 --- a/src/ines.c +++ b/src/ines.c @@ -784,10 +784,11 @@ INES_BOARD_BEGIN() INES_BOARD( "Realtec 8031", 390, Mapper390_Init ) INES_BOARD( "BS-110", 391, Mapper391_Init ) INES_BOARD( "820720C", 393, Mapper393_Init ) + INES_BOARD( "HSK007", 394, Mapper394_Init ) INES_BOARD( "Realtec 8210", 395, Mapper395_Init ) - INES_BOARD( "YY850437C", 396, Mapper396_Init ) + INES_BOARD( "YY850437C", 396, Mapper396_Init ) INES_BOARD( "YY850439C", 397, Mapper397_Init ) - INES_BOARD( "BMC Super 19-in-1 (VIP19)", 401, Mapper401_Init ) + INES_BOARD( "BMC Super 19-in-1 (VIP19)",401, Mapper401_Init ) INES_BOARD( "831019C J-2282", 402, J2282_Init ) INES_BOARD( "89433", 403, Mapper403_Init ) INES_BOARD( "JY012005", 404, Mapper404_Init ) diff --git a/src/ines.h b/src/ines.h index 7a568dd..e6ed97b 100644 --- a/src/ines.h +++ b/src/ines.h @@ -294,6 +294,7 @@ void Mapper389_Init(CartInfo *); void Mapper390_Init(CartInfo *); void Mapper391_Init(CartInfo *); void Mapper393_Init(CartInfo *); +void Mapper394_Init(CartInfo *); void Mapper395_Init(CartInfo *); void Mapper396_Init(CartInfo *); void Mapper397_Init(CartInfo *);