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Simplify mapper 219 emulation; add outer bank register.

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NewRisingSun
2021-10-20 23:03:19 +02:00
parent cb3a22daf0
commit 5a10da375e
1 changed files with 68 additions and 38 deletions
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106
src/boards/a9746.c
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@@ -21,55 +21,85 @@
#include "mapinc.h" #include "mapinc.h"
#include "mmc3.h" #include "mmc3.h"
static DECLFW(UNLA9746Write) { static void UNLA9746PWrap(uint32 A, uint8 V) {
/* FCEU_printf("write raw %04x:%02x\n",A,V); */ setprg8(A, EXPREGS[1] <<4 | V &0x0F);
switch (A & 0xE003) { }
case 0x8000: EXPREGS[1] = V; EXPREGS[0] = 0; break;
case 0x8002: EXPREGS[0] = V; EXPREGS[1] = 0; break; static void UNLA9746CWrap(uint32 A, uint8 V) {
case 0x8001: setchr1(A, EXPREGS[1] <<7 | V &0x7F);
{ }
uint8 bits_rev = ((V & 0x20) >> 5) | ((V & 0x10) >> 3) | ((V & 0x08) >> 1) | ((V & 0x04) << 1);
switch (EXPREGS[0]) { static DECLFW(UNLA9746WriteOuter) {
case 0x26: setprg8(0x8000, bits_rev); break; switch(A &1) {
case 0x25: setprg8(0xA000, bits_rev); break; case 0: EXPREGS[1] =EXPREGS[1] &~1 | V >>3 &1; break;
case 0x24: setprg8(0xC000, bits_rev); break; case 1: EXPREGS[1] =EXPREGS[1] &~2 | V >>4 &2; break;
case 0x23: setprg8(0xE000, bits_rev); break; }
FixMMC3PRG(MMC3_cmd);
FixMMC3CHR(MMC3_cmd);
}
static DECLFW(UNLA9746WriteASIC) {
int index;
if (A &1)
{ /* Register data */
if (~EXPREGS[0] &0x20)
{ /* Scrambled mode inactive */
MMC3_CMDWrite(A, V);
} }
switch (EXPREGS[1]) { else
case 0x0a: { /* Scrambled mode active */
case 0x08: EXPREGS[2] = (V << 4); break; if (MMC3_cmd >=0x08 && MMC3_cmd <=0x1F)
case 0x09: setchr1(0x0000, EXPREGS[2] | (V >> 1)); break; { /* Scrambled CHR register */
case 0x0b: setchr1(0x0400, EXPREGS[2] | (V >> 1) | 1); break; index = (MMC3_cmd -8) >>2;
case 0x0c: if (MMC3_cmd &1)
case 0x0e: EXPREGS[2] = (V << 4); break; { /* LSB nibble */
case 0x0d: setchr1(0x0800, EXPREGS[2] | (V >> 1)); break; DRegBuf[index] &=~0x0F;
case 0x0f: setchr1(0x0c00, EXPREGS[2] | (V >> 1) | 1); break; DRegBuf[index] |=V >>1 &0x0F;
case 0x10: }
case 0x12: EXPREGS[2] = (V << 4); break; else
case 0x11: setchr1(0x1000, EXPREGS[2] | (V >> 1)); break; { /* MSB nibble */
case 0x14: DRegBuf[index] &=~0xF0;
case 0x16: EXPREGS[2] = (V << 4); break; DRegBuf[index] |=V <<4 &0xF0;
case 0x15: setchr1(0x1400, EXPREGS[2] | (V >> 1)); break; }
case 0x18: FixMMC3CHR(MMC3_cmd);
case 0x1a: EXPREGS[2] = (V << 4); break; }
case 0x19: setchr1(0x1800, EXPREGS[2] | (V >> 1)); break; else
case 0x1c: if (MMC3_cmd >=0x25 && MMC3_cmd <=0x26)
case 0x1e: EXPREGS[2] = (V << 4); break; { /* Scrambled PRG register */
case 0x1d: setchr1(0x1c00, EXPREGS[2] | (V >> 1)); break; DRegBuf[6 | MMC3_cmd &1] =V >>5 &1 | V >>3 &2 | V >>1 &4 | V <<1 &8;
FixMMC3PRG(MMC3_cmd);
}
} }
} }
break; else
{ /* Register index */
MMC3_CMDWrite(A, V);
if (A &2) EXPREGS[0] =V;
} }
} }
static void UNLA9746Power(void) { static void UNLA9746Power(void) {
GenMMC3Power(); GenMMC3Power();
SetWriteHandler(0x8000, 0xbfff, UNLA9746Write); SetWriteHandler(0x5000, 0x5FFF, UNLA9746WriteOuter);
SetWriteHandler(0x8000, 0xBFFF, UNLA9746WriteASIC);
EXPREGS[0] = 0;
EXPREGS[1] = 3;
MMC3RegReset();
}
static void UNLA9746Reset(void) {
EXPREGS[0] = 0;
EXPREGS[1] = 3;
MMC3RegReset();
} }
void UNLA9746_Init(CartInfo *info) { void UNLA9746_Init(CartInfo *info) {
GenMMC3_Init(info, 128, 256, 0, 0); GenMMC3_Init(info, 128, 128, 0, 0);
pwrap = UNLA9746PWrap;
cwrap = UNLA9746CWrap;
info->Power = UNLA9746Power; info->Power = UNLA9746Power;
AddExState(EXPREGS, 6, 0, "EXPR"); info->Reset = UNLA9746Reset;
AddExState(EXPREGS, 2, 0, "EXPR");
} }