Add new mappers
Added iNES 1.0/2.0 mappers 134 - replaced Mapper134_init with Bs5652_Init 391 - NC7000M 402 - 831019C J-2282 Added UNIF boards: AB-G1L BS-110 WELL-NO-DG450 KG256
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negativeExponent
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src/boards/Bs5652.c
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260
src/boards/Bs5652.c
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2008 -2020 dragon2snow,loong2snow from www.nesbbs.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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#include "crc32.h"
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extern uint8 *WRAM;
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extern uint32 WRAMSIZE;
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//extern uint8 *CHRRAM;
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//extern uint32 CHRRAMSIZE;
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uint8 mmc3_reg[8];
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uint8 exRegs[8];
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uint8 pointer;
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uint8 locked;
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uint8 readDIP;
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uint16 prgAND;
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uint16 chrAND;
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uint16 prgOR;
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uint16 chrOR;
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uint8 nrom;
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uint8 nrom128;
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uint8 dipswitch;
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static SFORMAT BS5652_StateRegs[] =
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{
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{ exRegs, 8, "REGS" },
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{ mmc3_reg, 8, "MMC3R" },
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{ &pointer, 1, "POINT" },
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{ &readDIP, 1, "RDIP" },
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{ &prgAND, 1, "PRGAND" },
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{ &chrAND, 1, "CHRAND" },
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{ &prgOR, 1, "PRGOR" },
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{ &chrOR, 1, "CHROR" },
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{ &nrom, 1, "NROM" },
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{ &nrom128, 1, "N128" },
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{ &dipswitch, 1, "DIP" },
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{ 0 }
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};
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void Bs5652AnalyzeReg()
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{
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locked = exRegs[0] & 0x80;
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readDIP = exRegs[0] & 0x40;
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prgAND = exRegs[1] & 0x04 ? 0x0F : 0x1F;
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chrAND = exRegs[1] & 0x40 ? 0x7F : 0xFF;
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prgOR = (exRegs[1] & 0x03) << 4;
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chrOR = (exRegs[1] & 0x30) << 3 ;
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nrom = exRegs[0] & 0x08;
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nrom128 = exRegs[1] & 0x08;
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}
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int Bs5652GetPRGBank(int bank)
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{
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if (~bank & 1 && (pointer & 0x40)) bank ^= 2;
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return bank & 2 ? 0xFE | bank & 1 : mmc3_reg[6 | bank & 1];
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}
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void Bs5652SyncPRG_GNROM(int A14, int AND, int OR) {
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setprg8(0x8000, (Bs5652GetPRGBank(0) &~A14) &AND | OR);
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setprg8(0xA000, (Bs5652GetPRGBank(1) &~A14) &AND | OR);
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setprg8(0xC000, (Bs5652GetPRGBank(0) | A14) &AND | OR);
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setprg8(0xE000, (Bs5652GetPRGBank(1) | A14) &AND | OR);
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}
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static void Bs5652CW(uint32 A, uint8 V) {
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if (exRegs[0] & 0x08)
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setchr8((exRegs[2] & 0x0F) | (exRegs[4] & 0x03) | (((exRegs[1] >> 4) & 7) << 4));
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else
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setchr1(A, (V & chrAND) | chrOR );
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}
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static void Bs5652PW(uint32 A, uint8 V) {
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if (nrom)
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{
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if (exRegs[3] & 0x8)// 20190504 up2
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{
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if ((exRegs[1] >> 3) & 0x01)
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{
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uint8 _bank = ((exRegs[2] >> 1) & 0x07) | ((exRegs[1] & 3) << 3);
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setprg16(0x8000, _bank);
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setprg16(0xC000, _bank);
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}
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else
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{
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setprg32(0x8000,((exRegs[2] >> 2) & 0x03) | ((exRegs[1] & 3) << 2));
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}
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}
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else
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{
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Bs5652SyncPRG_GNROM(nrom128 ? 0 : 2, prgAND, prgOR);
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}
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}
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else
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{
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if (((exRegs[1] >> 7) & 0x01))
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{
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setprg32(0x8000,((Bs5652GetPRGBank(0) >> 2) & 0x03) | ((exRegs[1] & 3) << 2));
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}
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else
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setprg8(A, prgOR | (V & prgAND));
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}
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}
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static DECLFW(Bs5652WriteHi) {
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A = A & 0xE001;
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if (A < 0xC000)
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{
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if(A==0x8000)
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pointer = MMC3_cmd ^ V;
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if(A==0x8001)
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mmc3_reg[MMC3_cmd & 0x07] = V;
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MMC3_CMDWrite(A, V);
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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else
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{
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MMC3_IRQWrite(A, V);
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}
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}
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static DECLFW(Bs5652WriteLo) {
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if (!locked) {
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exRegs[A & 3] = V;
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Bs5652AnalyzeReg();
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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else
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{
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if ((exRegs[0] & 0x08))
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{
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exRegs[4] = V;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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else
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{
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WRAM[A - 0x6000] = V;
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}
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}
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}
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static DECLFR(Bs5652ReadHi)
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{
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if (readDIP)
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{
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return dipswitch;
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}
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else
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return CartBR(A);
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}
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static void Bs5652Power(void) {
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dipswitch = 0;
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mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02;
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mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07;
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mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01;
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int i=0;
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for(i=0;i<4;i++)
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{
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exRegs[i]=0;
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}
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Bs5652AnalyzeReg();
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GenMMC3Power();
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SetWriteHandler(0x6000, 0x7FFF, Bs5652WriteLo);
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SetWriteHandler(0x8000, 0xFFFF, Bs5652WriteHi);
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SetReadHandler(0x8000, 0xFFFF, Bs5652ReadHi);
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}
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static void Bs5652Reset(void) {
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dipswitch++;
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mmc3_reg[0] = 0x00; mmc3_reg[1] = 0x02;
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mmc3_reg[2] = 0x04; mmc3_reg[3] = 0x05; mmc3_reg[4] = 0x06; mmc3_reg[5] = 0x07;
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mmc3_reg[6] = 0x00; mmc3_reg[7] = 0x01;
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int i=0;
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for(i=0;i<4;i++)
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{
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exRegs[i]=0;
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}
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Bs5652AnalyzeReg();
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MMC3RegReset();
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}
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static void Bs5652Close(void) {
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if (WRAM)
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FCEU_gfree(WRAM);
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WRAM = NULL;
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}
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void Bs5652_Init(CartInfo *info) {
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GenMMC3_Init(info, 512, 512, 0, 0);
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pwrap = Bs5652PW;
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cwrap = Bs5652CW;
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info->Power = Bs5652Power;
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info->Reset = Bs5652Reset;
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info->Close = Bs5652Close;
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WRAMSIZE = 8192;
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WRAM = (uint8*)FCEU_gmalloc(WRAMSIZE);
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SetupCartPRGMapping(0x10, WRAM, WRAMSIZE, 1);
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AddExState(WRAM, WRAMSIZE, 0, "WRAM");
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//CHRRAMSIZE = 8192;
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//CHRRAM = (uint8*)FCEU_gmalloc(CHRRAMSIZE);
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//SetupCartCHRMapping(0x10, CHRRAM, CHRRAMSIZE, 1);
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//AddExState(CHRRAM, CHRRAMSIZE, 0, "CHRR");
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uint32 unif_crc = CalcCRC32(0, PRGptr[0], PRGsize[0]);
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if (unif_crc == 0xb97641b5) //Fix my own error, unif CHR 0 error
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{
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if ((CHRsize[0] == 0x2000) && (CHRsize[1] > 0x2000))
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{
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CHRsize[0] = CHRsize[1];
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CHRptr[0] = (uint8*)FCEU_gmalloc(CHRsize[1]);
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memcpy(CHRptr[0], CHRptr[1], CHRsize[1]);
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SetupCartCHRMapping(0, CHRptr[0], CHRsize[0], 0);
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}
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}
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AddExState(EXPREGS, 3, 0, "EXPR");
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AddExState(BS5652_StateRegs, ~0, 0, 0);
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}
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