475 lines
13 KiB
C
475 lines
13 KiB
C
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/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2002 Xodnizel
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* Copyright (C) 2005 CaH4e3
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mapinc.h"
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//#define DEBUG90
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// Mapper 090 is simpliest mapper hardware and have not extended nametable control and latched chr banks in 4k mode
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// Mapper 209 much compicated hardware with decribed above features disabled by default and switchable by command
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// Mapper 211 the same mapper 209 but with forced nametable control
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static int is209;
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static int is211;
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static uint8 IRQMode; // from $c001
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static uint8 IRQPre; // from $c004
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static uint8 IRQPreSize; // from $c007
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static uint8 IRQCount; // from $c005
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static uint8 IRQXOR; // Loaded from $C006
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static uint8 IRQa; // $c002, $c003, and $c000
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static uint8 mul[2];
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static uint8 regie;
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static uint8 tkcom[4];
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static uint8 prgb[4];
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static uint8 chrlow[8];
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static uint8 chrhigh[8];
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static uint8 chr[2];
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static uint16 names[4];
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static uint8 tekker;
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static SFORMAT Tek_StateRegs[] = {
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{ &IRQMode, 1, "IRQM" },
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{ &IRQPre, 1, "IRQP" },
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{ &IRQPreSize, 1, "IRQR" },
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{ &IRQCount, 1, "IRQC" },
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{ &IRQXOR, 1, "IRQX" },
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{ &IRQa, 1, "IRQA" },
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{ mul, 2, "MUL" },
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{ ®ie, 1, "REGI" },
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{ tkcom, 4, "TKCO" },
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{ prgb, 4, "PRGB" },
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{ chr, 2, "CLTC" },
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{ chrlow, 4, "CHRL" },
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{ chrhigh, 8, "CHRH" },
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{ &names[0], 2 | FCEUSTATE_RLSB, "NMS0" },
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{ &names[1], 2 | FCEUSTATE_RLSB, "NMS1" },
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{ &names[2], 2 | FCEUSTATE_RLSB, "NMS2" },
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{ &names[3], 2 | FCEUSTATE_RLSB, "NMS3" },
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{ &tekker, 1, "TEKR" },
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{ 0 }
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};
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static void mira(void) {
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if ((tkcom[0] & 0x20 && is209) || is211) {
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int x;
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if (tkcom[0] & 0x40) { // Name tables are ROM-only
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for (x = 0; x < 4; x++)
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setntamem(CHRptr[0] + (((names[x]) & CHRmask1[0]) << 10), 0, x);
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} else { // Name tables can be RAM or ROM.
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for (x = 0; x < 4; x++) {
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if ((tkcom[1] & 0x80) == (names[x] & 0x80)) // RAM selected.
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setntamem(NTARAM + ((names[x] & 0x1) << 10), 1, x);
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else
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setntamem(CHRptr[0] + (((names[x]) & CHRmask1[0]) << 10), 0, x);
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}
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}
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} else {
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switch (tkcom[1] & 3) {
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case 0: setmirror(MI_V); break;
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case 1: setmirror(MI_H); break;
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case 2: setmirror(MI_0); break;
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case 3: setmirror(MI_1); break;
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}
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}
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}
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static void tekprom(void) { // TODO: verify for single, small multi and large multi
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uint32 bankmode = ((tkcom[3] & 6) << 5);
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switch (tkcom[0] & 7) {
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case 00:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (((prgb[3] << 2) + 3) & 0x3F) | bankmode);
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setprg32(0x8000, (prgb[3] & 7) | ((tkcom[3] & 7) << 3));
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break;
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case 01:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (((prgb[3] << 1) + 1) & 0x3F) | bankmode);
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setprg16(0x8000, (prgb[1] & 0x0F) | ((tkcom[3] & 7) << 4));
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setprg16(0xC000, 0x0F | ((tkcom[3] & 7) << 4));
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break;
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case 03: // bit reversion
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case 02:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (prgb[3] & 0x1F) | ((tkcom[3] & 7) << 5)); // 45in1 multy has different bits, seems board was hacked to support big data banks
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setprg8(0x8000, (prgb[0] & 0x1F) | ((tkcom[3] & 7) << 5));
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setprg8(0xa000, (prgb[1] & 0x1F) | ((tkcom[3] & 7) << 5));
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setprg8(0xc000, (prgb[2] & 0x1F) | ((tkcom[3] & 7) << 5));
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setprg8(0xe000, 0x1F | ((tkcom[3] & 7) << 5));
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// setprg8(0xe000,(prgb[3]&0x0F)|((tkcom[3]&6)<<3));
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// setprg32(0x8000,((prgb[0]&0x0F)>>2)|((tkcom[3]&6)<<3));
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break;
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case 04:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (((prgb[3] << 2) + 3) & 0x3F) | bankmode);
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setprg32(0x8000, (prgb[3] & 0x0F) | ((tkcom[3] & 6) << 3));
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break;
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case 05:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (((prgb[3] << 1) + 1) & 0x3F) | bankmode);
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setprg16(0x8000, (prgb[1] & 0x1F) | ((tkcom[3] & 6) << 4));
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setprg16(0xC000, (prgb[3] & 0x1F) | ((tkcom[3] & 6) << 4));
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break;
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case 07: // bit reversion
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case 06:
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if (tkcom[0] & 0x80)
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setprg8(0x6000, (prgb[3] & 0x3F) | bankmode);
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setprg8(0x8000, (prgb[0] & 0x3F) | bankmode);
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setprg8(0xa000, (prgb[1] & 0x3F) | bankmode);
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setprg8(0xc000, (prgb[2] & 0x3F) | bankmode);
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setprg8(0xe000, (prgb[3] & 0x3F) | bankmode);
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break;
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}
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}
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static void tekvrom(void) {
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int x, bank = 0, mask = 0xFFFF;
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if (!(tkcom[3] & 0x20)) {
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bank = (tkcom[3] & 1) | ((tkcom[3] & 0x18) >> 2);
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switch (tkcom[0] & 0x18) {
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case 0x00: bank <<= 5; mask = 0x1F; break;
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case 0x08: bank <<= 6; mask = 0x3F; break;
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case 0x10: bank <<= 7; mask = 0x7F; break;
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case 0x18: bank <<= 8; mask = 0xFF; break;
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}
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}
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switch (tkcom[0] & 0x18) {
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case 0x00: // 8KB
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setchr8(((chrlow[0] | (chrhigh[0] << 8)) & mask) | bank);
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break;
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case 0x08: // 4KB
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// for(x=0;x<8;x+=4)
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// setchr4(x<<10,((chrlow[x]|(chrhigh[x]<<8))&mask)|bank);
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setchr4(0x0000, ((chrlow[chr[0]] | (chrhigh[chr[0]] << 8)) & mask) | bank);
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setchr4(0x1000, ((chrlow[chr[1]] | (chrhigh[chr[1]] << 8)) & mask) | bank);
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break;
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case 0x10: // 2KB
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for (x = 0; x < 8; x += 2)
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setchr2(x << 10, ((chrlow[x] | (chrhigh[x] << 8)) & mask) | bank);
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break;
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case 0x18: // 1KB
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for (x = 0; x < 8; x++)
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setchr1(x << 10, ((chrlow[x] | (chrhigh[x] << 8)) & mask) | bank);
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break;
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}
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}
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static DECLFW(M90TekWrite) {
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switch (A & 0x5C03) {
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case 0x5800: mul[0] = V; break;
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case 0x5801: mul[1] = V; break;
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case 0x5803: regie = V; break;
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}
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}
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static DECLFR(M90TekRead) {
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switch (A & 0x5C03) {
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case 0x5800: return(mul[0] * mul[1]);
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case 0x5801: return((mul[0] * mul[1]) >> 8);
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case 0x5803: return(regie);
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default: return tekker;
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}
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return(0xff);
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}
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static DECLFW(M90PRGWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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prgb[A & 3] = V;
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tekprom();
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}
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static DECLFW(M90CHRlowWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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chrlow[A & 7] = V;
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tekvrom();
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}
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static DECLFW(M90CHRhiWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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chrhigh[A & 7] = V;
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tekvrom();
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}
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static DECLFW(M90NTWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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if (A & 4) {
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names[A & 3] &= 0x00FF;
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names[A & 3] |= V << 8;
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} else {
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names[A & 3] &= 0xFF00;
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names[A & 3] |= V;
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}
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mira();
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}
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static DECLFW(M90IRQWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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switch (A & 7) {
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case 00:
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// FCEU_printf("%s IRQ (C000)\n",V&1?"Enable":"Disable");
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IRQa = V & 1;
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if (!(V & 1))
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 02:
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// FCEU_printf("Disable IRQ (C002) scanline=%d\n", scanline);
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IRQa = 0; X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 03:
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// FCEU_printf("Enable IRQ (C003) scanline=%d\n", scanline);
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IRQa = 1;
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break;
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case 01:
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IRQMode = V;
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/*FCEU_printf("IRQ Count method: ");
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switch (IRQMode&3)
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{
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case 00: FCEU_printf("M2 cycles\n");break;
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case 01: FCEU_printf("PPU A12 toggles\n");break;
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case 02: FCEU_printf("PPU reads\n");break;
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case 03: FCEU_printf("Writes to CPU space\n");break;
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}
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FCEU_printf("Counter prescaler size: %s\n",(IRQMode&4)?"3 bits":"8 bits");
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FCEU_printf("Counter prescaler size adjust: %s\n",(IRQMode&8)?"Used C007":"Normal Operation");
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if((IRQMode>>6)==2) FCEU_printf("Counter Down\n");
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else if((IRQMode>>6)==1) FCEU_printf("Counter Up\n");
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else FCEU_printf("Counter Stopped\n");*/
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break;
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case 04:
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// FCEU_printf("Pre Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
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IRQPre = V ^ IRQXOR;
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break;
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case 05:
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// FCEU_printf("Main Counter Loaded and Xored wiht C006: %d\n",V^IRQXOR);
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IRQCount = V ^ IRQXOR;
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break;
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case 06:
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// FCEU_printf("Xor Value: %d\n",V);
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IRQXOR = V;
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break;
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case 07:
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// if(!(IRQMode&8)) FCEU_printf("C001 is clear, no effect applied\n");
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// else if(V==0xFF) FCEU_printf("Prescaler is changed for 12bits\n");
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// else FCEU_printf("Counter Stopped\n");
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IRQPreSize = V;
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break;
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}
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}
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static DECLFW(M90ModeWrite) {
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// FCEU_printf("bs %04x %02x\n",A,V);
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tkcom[A & 3] = V;
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tekprom();
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tekvrom();
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mira();
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#ifdef DEBUG90
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switch (A & 3) {
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case 00:
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FCEU_printf("Main Control Register:\n");
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FCEU_printf(" PGR Banking mode: %d\n", V & 7);
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FCEU_printf(" CHR Banking mode: %d\n", (V >> 3) & 3);
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FCEU_printf(" 6000-7FFF addresses mapping: %s\n", (V & 0x80) ? "Yes" : "No");
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FCEU_printf(" Nametable control: %s\n", (V & 0x20) ? "Enabled" : "Disabled");
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if (V & 0x20)
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FCEU_printf(" Nametable can be: %s\n", (V & 0x40) ? "ROM Only" : "RAM or ROM");
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break;
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case 01:
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FCEU_printf("Mirroring mode: ");
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switch (V & 3) {
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case 0: FCEU_printf("Vertical\n"); break;
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case 1: FCEU_printf("Horizontal\n"); break;
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case 2: FCEU_printf("Nametable 0 only\n"); break;
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case 3: FCEU_printf("Nametable 1 only\n"); break;
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}
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FCEU_printf("Mirroring flag: %s\n", (V & 0x80) ? "On" : "Off");
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break;
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case 02:
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if ((((tkcom[0]) >> 5) & 3) == 1)
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FCEU_printf("Nametable ROM/RAM select mode: %d\n", V >> 7);
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break;
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case 03:
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FCEU_printf("CHR Banking mode: %s\n", (V & 0x20) ? "Entire CHR ROM" : "256Kb Switching mode");
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if (!(V & 0x20)) FCEU_printf("256K CHR bank number: %02x\n", (V & 1) | ((V & 0x18) >> 2));
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FCEU_printf("512K PRG bank number: %d\n", (V & 6) >> 1);
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FCEU_printf("CHR Bank mirroring: %s\n", (V & 0x80) ? "Swapped" : "Normal operate");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static DECLFW(M90DummyWrite) {
|
||
|
|
// FCEU_printf("bs %04x %02x\n",A,V);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void CCL(void) {
|
||
|
|
if ((IRQMode >> 6) == 1) { // Count Up
|
||
|
|
IRQCount++;
|
||
|
|
if ((IRQCount == 0) && IRQa) {
|
||
|
|
X6502_IRQBegin(FCEU_IQEXT);
|
||
|
|
}
|
||
|
|
} else if ((IRQMode >> 6) == 2) { // Count down
|
||
|
|
IRQCount--;
|
||
|
|
if ((IRQCount == 0xFF) && IRQa) {
|
||
|
|
X6502_IRQBegin(FCEU_IQEXT);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ClockCounter(void) {
|
||
|
|
uint8 premask;
|
||
|
|
|
||
|
|
if (IRQMode & 0x4)
|
||
|
|
premask = 0x7;
|
||
|
|
else
|
||
|
|
premask = 0xFF;
|
||
|
|
if ((IRQMode >> 6) == 1) { // Count up
|
||
|
|
IRQPre++;
|
||
|
|
if ((IRQPre & premask) == 0) CCL();
|
||
|
|
} else if ((IRQMode >> 6) == 2) { // Count down
|
||
|
|
IRQPre--;
|
||
|
|
if ((IRQPre & premask) == premask) CCL();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void FP_FASTAPASS(1) CPUWrap(int a) {
|
||
|
|
int x;
|
||
|
|
if ((IRQMode & 3) == 0) for (x = 0; x < a; x++) ClockCounter();
|
||
|
|
}
|
||
|
|
|
||
|
|
static void SLWrap(void) {
|
||
|
|
int x;
|
||
|
|
if ((IRQMode & 3) == 1) for (x = 0; x < 8; x++) ClockCounter();
|
||
|
|
}
|
||
|
|
|
||
|
|
static uint32 lastread;
|
||
|
|
static void FP_FASTAPASS(1) M90PPU(uint32 A) {
|
||
|
|
if ((IRQMode & 3) == 2) {
|
||
|
|
if (lastread != A) {
|
||
|
|
ClockCounter();
|
||
|
|
ClockCounter();
|
||
|
|
}
|
||
|
|
lastread = A;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (is209) {
|
||
|
|
uint8 l, h;
|
||
|
|
h = A >> 8;
|
||
|
|
if (h < 0x20 && ((h & 0x0F) == 0xF)) {
|
||
|
|
l = A & 0xF0;
|
||
|
|
if (l == 0xD0) {
|
||
|
|
chr[(h & 0x10) >> 4] = ((h & 0x10) >> 2);
|
||
|
|
tekvrom();
|
||
|
|
} else if (l == 0xE0) {
|
||
|
|
chr[(h & 0x10) >> 4] = ((h & 0x10) >> 2) | 2;
|
||
|
|
tekvrom();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
chr[0] = 0;
|
||
|
|
chr[1] = 4;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void togglie() {
|
||
|
|
tekker += 0x40;
|
||
|
|
tekker &= 0xC0;
|
||
|
|
FCEU_printf("tekker=%02x\n", tekker);
|
||
|
|
memset(tkcom, 0x00, sizeof(tkcom));
|
||
|
|
memset(prgb, 0xff, sizeof(prgb));
|
||
|
|
tekprom();
|
||
|
|
tekvrom();
|
||
|
|
}
|
||
|
|
|
||
|
|
static void M90Restore(int version) {
|
||
|
|
tekprom();
|
||
|
|
tekvrom();
|
||
|
|
mira();
|
||
|
|
}
|
||
|
|
|
||
|
|
static void M90Power(void) {
|
||
|
|
SetWriteHandler(0x5000, 0x5fff, M90TekWrite);
|
||
|
|
SetWriteHandler(0x8000, 0x8ff0, M90PRGWrite);
|
||
|
|
SetWriteHandler(0x9000, 0x9fff, M90CHRlowWrite);
|
||
|
|
SetWriteHandler(0xA000, 0xAfff, M90CHRhiWrite);
|
||
|
|
SetWriteHandler(0xB000, 0xBfff, M90NTWrite);
|
||
|
|
SetWriteHandler(0xC000, 0xCfff, M90IRQWrite);
|
||
|
|
SetWriteHandler(0xD000, 0xD5ff, M90ModeWrite);
|
||
|
|
SetWriteHandler(0xE000, 0xFfff, M90DummyWrite);
|
||
|
|
|
||
|
|
SetReadHandler(0x5000, 0x5fff, M90TekRead);
|
||
|
|
SetReadHandler(0x6000, 0xffff, CartBR);
|
||
|
|
|
||
|
|
mul[0] = mul[1] = regie = 0xFF;
|
||
|
|
|
||
|
|
memset(tkcom, 0x00, sizeof(tkcom));
|
||
|
|
memset(prgb, 0xff, sizeof(prgb));
|
||
|
|
memset(chrlow, 0xff, sizeof(chrlow));
|
||
|
|
memset(chrhigh, 0xff, sizeof(chrhigh));
|
||
|
|
memset(names, 0x00, sizeof(names));
|
||
|
|
|
||
|
|
if (is211)
|
||
|
|
tekker = 0xC0;
|
||
|
|
else
|
||
|
|
tekker = 0x00;
|
||
|
|
|
||
|
|
tekprom();
|
||
|
|
tekvrom();
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void Mapper90_Init(CartInfo *info) {
|
||
|
|
is211 = 0;
|
||
|
|
is209 = 0;
|
||
|
|
info->Reset = togglie;
|
||
|
|
info->Power = M90Power;
|
||
|
|
PPU_hook = M90PPU;
|
||
|
|
MapIRQHook = CPUWrap;
|
||
|
|
GameHBIRQHook2 = SLWrap;
|
||
|
|
GameStateRestore = M90Restore;
|
||
|
|
AddExState(Tek_StateRegs, ~0, 0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void Mapper209_Init(CartInfo *info) {
|
||
|
|
is211 = 0;
|
||
|
|
is209 = 1;
|
||
|
|
info->Reset = togglie;
|
||
|
|
info->Power = M90Power;
|
||
|
|
PPU_hook = M90PPU;
|
||
|
|
MapIRQHook = CPUWrap;
|
||
|
|
GameHBIRQHook2 = SLWrap;
|
||
|
|
GameStateRestore = M90Restore;
|
||
|
|
AddExState(Tek_StateRegs, ~0, 0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void Mapper211_Init(CartInfo *info) {
|
||
|
|
is211 = 1;
|
||
|
|
info->Reset = togglie;
|
||
|
|
info->Power = M90Power;
|
||
|
|
PPU_hook = M90PPU;
|
||
|
|
MapIRQHook = CPUWrap;
|
||
|
|
GameHBIRQHook2 = SLWrap;
|
||
|
|
GameStateRestore = M90Restore;
|
||
|
|
AddExState(Tek_StateRegs, ~0, 0, 0);
|
||
|
|
}
|